Patent Application
20080160800
Pin grid array (PGA) packages typically utilize pins to form external interconnects. However, pins may become bent during CPU or other package assembling and/or testing process. While pin reworking may recover some bent pins, other bent pins may be unrecoverable and scrapped. Since bent pins are necessary for pin material and test process, they can not be eliminated. Unfortunately, testing the units with bent pins that can not be recovered increases UPH time.
The invention described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
In the following detailed description, references is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numbers refer to the same or similar functionality throughout the several views.
References in the specification to “one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The following description may include terms, such as upper, lower, top, bottom, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting.
The memory 130 may comprise memory devices providing addressable storage locations that a memory controller 122 may read data from and/or write data to. The memory 130 may comprise one or more different types of memory devices such as, for example, dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, read-only memory (ROM) devices, or any other volatile or non-volatile memory devices.
The computing device 100 may further comprise a chipset 120. The chipset 120 may comprise one or more integrated circuit (IC) packages or chips that couple the processors 110 to memory 130, Basic Input/Output System (BIOS) 140, one or more storage devices 160, and other components (for example, mouse, keyboard, video controller, or other I/O devices of the computing device 100, etc.). The chipset 130 may receive transactions from the processors 110 and to issue transactions to the processors 110 via a processor bus 112. The memory controller 122 may issue transactions to the memory 140 via a memory bus 132.
In one embodiment, the storage device 160 may store archive information, such as code, programs, files, data, applications, or operating systems, etc. An example of the storage device 160 may comprise a tape, hard disk (HD) drive, a floppy diskette, a compact disk (CD) ROM, a flash memory device, any other mass storage device, any other magnetic storage media, any other optical storage media, any other non-volatile memory devices, etc. The chipset 120 may comprise one or more storage device interfaces 128 that may access each storage device 160 via a bus 142.
In one embodiment, the BIOS 140 may be used for system initialization and/or configuration of the computing device 100. In another embodiment, the BIOS 140 may collect information that may be selectively used by an operation system. For example, the information may comprise a data structure that may be used by the operation system to look up one or more devices in the computing device 100. In another embodiment, the BIOS 140 may comprise routines which the computing device 100 may execute during system backup or recovery. The BIOS 140 may further handle communications in the computing device 100, e.g., between software running on the computing device 100 and/or devices in the computing device 100, such as CPUs, disk drives, or printers, etc. The BIOS 140 may further comprise routines or drivers which the computing device 100 may execute to communicate with one or more components in the computing device 100.
In another embodiment, the computing device 100 may comprise a BIOS memory to store BIOS code or data. The BIOS memory may be implemented with non-volatile memory devices, such as read-only memory (ROM) devices, flash memory, and any other memories. The BIOS 140 may further contain a BIOS USB driver and other drivers. The BIOS 140 may be implemented in a firmware. In one embodiment, the BIOS 140 may comprise a legacy BIOS, extensible firmware interface (EFI) BIOS, or other BIOS. The chipset 130 may comprise a BIOS interface 124 that may access the BIOS 140 via a bus 142. While
In one embodiment, the computing device 100 may communicate with one or more networks 170 via a network bus 172. The chipset 130 may comprise a network controller 126 to control the communication between the computing device 100 and the networks 170. The chipset 130 may further comprise one or more other component interfaces (not shown) to access the other components 160 via one or more buses 142 such as, for example, peripheral component interconnect (PCI) buses, accelerated graphics port (AGP) buses, universal serial bus (USB) buses, low pin count (LPC) buses, and/or other I/O buses.
Any suitable methods may be utilized to mount a pin 210 to the chip 200. In one embodiment, the pins 210 may be coupled to one or more conductive circuitry 206 that may each comprise a pin bonding site, pad, opening or aperture (not shown). The conductive circuitry 206 may be coupled with one or more IC devices 204 such as semiconductor circuits, dies on a substrate 202 that may be coupled to the IC devices 204 via wire bonds, bumps or any other interconnects. In one embodiment, the pins 210 may pass through the one or more circuitry 206. In another embodiment, the pins 210 may extend through the substrate 202 by openings or apertures 208. In another embodiment, the pins 210 may protrude from the chip 200. In yet another embodiment, a cover component 212 may be provided to protect the chip 200 or the IC devices 204. In another embodiment, an encapsulant or molding compound such as epoxy resin may be used to encapsulate IC devices or dies, substrates, or interconnects, in the chip 200. In another embodiment, a pin 210 may be soldered or brazed to the conductive circuitry 206 in the chip 200.
In one embodiment, the pin 210 may be formed from one or more shape memory alloys (SMA) or metals. In another embodiment, a protruded portion or lower end of the pin 210 may be made from one or more SMA. For example, the SMA may comprise one or more metals. In another embodiment, the SMA may revert to its original shapes under a temperature, e.g., a transformation temperature. For example, if a straight pin made from SMA is bent, the bent pin may become straight under a transformation temperature of the SMA. In another embodiment, the material for a pin 210 may further comprise one or more other metals such as copper, silver or tin, etc. The composition and/or percentage by weight of the SMA in pin material may be varied based on a desired mechanical and/or electrical performance. Examples of the SMA may comprise NiTi SMA, copper based SMA, or any other SMA. In another embodiment, the pin 210 may be coated with another metal or metals such as gold to enhance conductivity, solderability and/or adhesion. In another embodiment, a method similar to that for producing a copper pin may be utilized to provide the pin 210 made from SMA. Any suitable package or chips may utilize pins made from SMA, such as package in line (PIL) package, plastic leaded chip carrier (PLCC), thin small outline package (TSOP), plastic pin grid array (PPGA) package, flip chip package grid array (FCPGA) package, metal pin grid array package or any other suitable packages or chips.
In another embodiment, one or more system components of the computing system 100 of
While the methods of
While certain features of the invention have been described with reference to embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.
