Patent Application
20250056718
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2023-128273, filed Aug. 7, 2023, the entire contents of which are incorporated herein by reference.
The present invention relates to a printed wiring board.
Japanese Patent Application Laid-Open Publication No. 2015-126103 describes a printed wiring board having a first conductor layer, an insulating layer formed on the first conductor layer, and a second conductor layer formed on the insulating layer. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a printed wiring board includes a first conductor layer, a resin insulating layer laminated on the first conductor layer, a second conductor layer formed on a surface of the resin insulating layer, and a via conductor formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer. The resin insulating layer includes resin and inorganic particles including first particles and second particles such that the first particles have flat exposed portions, the second particles are embedded in the resin, and the surface of the resin insulating layer includes the resin and the flat exposed portions of the first particles.
According to another aspect of the present invention, a method of manufacturing a printed wiring board includes forming a resin insulating layer on a first conductor layer, forming a second conductor layer on a surface of the resin insulating layer, and forming a via conductor in the resin insulating layer such that the via conductor connects the first conductor layer and the second conductor layer. The resin insulating layer includes resin and inorganic particles including first particles and second particles such that the first particles have flat exposed portions, the second particles are embedded in the resin, and the surface of the resin insulating layer includes the resin and the flat exposed portions of the first particles.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
The insulating layer 4 is formed using a resin. The insulating layer 4 may contain inorganic particles such as silica particles. The insulating layer 4 may contain a reinforcing material such as a glass cloth. The insulating layer 4 has a third surface 6 and a fourth surface 8 on an opposite side with respect to the third surface 6.
The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes a signal wiring 12 and a pad 14. Although not illustrated in the drawings, the first conductor layer 10 also includes conductor circuits other than the signal wiring 12 and the pad 14. The first conductor layer 10 is mainly formed of copper. The first conductor layer 10 is formed of a seed layer (10a) on the insulating layer 4 and an electrolytic plating layer (10b) on the seed layer (10a). The seed layer (10a) has a thickness of less than 0.5 μm. The seed layer (10a) is formed of a first layer (11a) on the third surface 6 and a second layer (11b) on the first layer (11a). The first layer (11a) is in contact with the insulating layer 4. A ratio of a thickness of the first layer (11a) to a thickness of the second layer (11b) ((the thickness of the first layer)/(the thickness of the second layer)) is 0.25 or more and 0.7 or less. The second layer (11b) is preferably thicker than the first layer (11a).
The first layer (11a) is formed of an alloy (copper alloy) containing copper and a metal other than copper. For example, the first layer (11a) is formed of an alloy containing copper and aluminum. The first layer (11a) is formed of an alloy containing copper, aluminum, and a specific metal. Examples of the specific metal include nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one type of specific metal, or two types of specific metals, or three types of specific metals. An example of the specific metal is silicon. A content of aluminum in the alloy is 1.0 at % or more and 15.0 at % or less. When the alloy contains a specific metal, a content of the specific metal in the alloy is 0.5 at % or more and 10.0 at % or less. The first layer (11a) may contain impurities. Examples of the impurities include oxygen and carbon. The first layer (11a) can contain oxygen or carbon. The first layer (11a) can contain oxygen and carbon. In the embodiment, the alloy further contains carbon. A content of carbon in the alloy is 50 ppm or less. The alloy further contains oxygen. A content of oxygen in the alloy is 100 ppm or less. The values of the contents of the elements described above are examples. Among the elements forming the first layer (11a), copper has the largest content. The content of aluminum is the next largest. When the alloy contains a specific metal, the content of the specific metal is less than the content of aluminum. Therefore, copper is a primary metal, aluminum is a first secondary metal, and the specific metal is a second secondary metal. A content of the impurities is smaller than the content of the specific metal.
The second layer (11b) is formed of copper. The electrolytic plating layer (10b) is formed of copper.
The content of copper in the copper alloy forming the first layer (11a) is greater than 90 at %. The content of copper in the alloy is less than 99 at %. The content of copper in the copper alloy is 98 at % or less. A content of copper forming the second layer (11b) is 99.9 at % or more. The content of copper in the second layer (11b) is preferably 99.95 at % or more. The electrolytic plating layer (10b) is formed of copper. A content of copper forming the electrolytic plating layer (10b) is 99.9 at % or more. The content of copper in the electrolytic plating layer (10b) is preferably 99.95 at % or more.
The resin insulating layer (first resin insulating layer) 20 is formed on the third surface 6 of the insulating layer 4 and on the first conductor layer 10. The first resin insulating layer 20 has a first surface 22 and a second surface 24 on an opposite side with respect to the first surface 22. The second surface 24 of the first resin insulating layer 20 faces the first conductor layer 10. The first resin insulating layer 20 has an opening (via conductor opening) 26 that exposes the pad 14. The opening 26 has a bottom diameter of 20 μm or more and 50 μm or less. The resin insulating layer (first resin insulating layer) 20 is formed of a resin 80 and a large number of inorganic particles 90 dispersed in the resin 80. The resin 80 has an upper surface (80R) and a lower surface (80S) on an opposite side with respect to the upper surface (80R). The upper surface (80R) forms the first surface 22, and the lower surface (80S) forms the second surface 24. The resin 80 is an epoxy resin. Examples of the resin include a thermosetting resin and a photocurable resin. The inorganic particles 90 are, for example, glass particles or alumina particles. The inorganic particles 90 preferably contain oxygen elements. The inorganic particles 90 have an average particle size of 0.5 μm or less. An amount of the inorganic particles 90 in the resin insulating layer 20 is 70 wt % or more.
As illustrated in
The first surface 22 has an arithmetic mean roughness (Ra) of less than 0.08 μm. The roughness (Ra) of the first surface 22 is preferably 0.05 μm or less. The roughness (Ra) of the first surface 22 is more preferably 0.03 μm or less. The upper surface (80R) has an arithmetic mean roughness (Ra) of less than 0.08 μm. The roughness (Ra) of the upper surface (80R) is preferably 0.05 μm or less. The roughness (Ra) of the upper surface (80R) is more preferably 0.03 μm or less.
The first surface 22 can have steps (first steps) between the first exposed surfaces (91x) and the upper surface (80R). The first exposed surfaces (91x) protrude relative to the upper surface (80R). Or, the first exposed surfaces (91x) are recessed relative to the upper surface (80R). Preferably, the first exposed surfaces (91x) protrude relative to the upper surface (80R). Sizes of the steps (first steps) (distances between the first exposed surfaces (91x) and the upper surface (80R) of the resin 80) are 5 μm or less. The sizes of the first steps are preferably 3 μm or less. The sizes of the first steps are more preferably 1.5 μm or less. Even when the steps (first steps) are formed, since the steps are small, the first exposed surfaces (91x) and the upper surface (80R) of the resin 80 form a substantially common surface. For example, the sizes of the steps are represented by a maximum value.
A ratio (R) of a volume of a first inorganic particle 91 to a volume of a sphere (assumed sphere) predicted from the first inorganic particle 91 ((volume of a first inorganic particle)/(volume of an assumed sphere)) is 0.6 or more and less than 1. The ratio (R) is preferably 0.8 or more. The ratio (R) is more preferably 0.9 or more. The ratio (R) is most preferably 0.95 or more. The ratio (R) is preferably 0.97 or less. A thermal expansion coefficient of the resin 80 near the upper surface (80R) is controlled.
As illustrated in
The inner wall surface 27 can have steps (second steps) between the flat parts (93a) and the surface (80a) of the resin 80 that forms the inner wall surface 27. The exposed surfaces (second exposed surfaces) (93b) of the flat parts (93a) protrude relative to the surface (80a) of the resin 80 that forms the inner wall surface 27. Or, the exposed surfaces (93b) of the flat parts (93a) are recessed relative to the surface (80a) of the resin 80 that forms the inner wall surface 27. Preferably, the exposed surfaces (93b) protrude relative to the surface (80a). Sizes of the steps (second steps) (distances between the exposed surfaces (93b) of the flat parts (93a) and the surface (80a) of the resin 80 that forms the inner wall surface 27) are 5 μm or less. The sizes of the second steps are preferably 3 μm or less. The sizes of the second steps are more preferably 1.5 μm or less. Even when the steps (second steps) are formed, since the steps are small, the exposed surfaces (93b) of the flat parts (93a) and the surface (80a) of the resin 80 that forms the inner wall surface 27 form a substantially common surface. When the first exposed surfaces (91x) protrude, the second exposed surfaces (93b) also protrude. When the first exposed surfaces (91x) are recessed, the second exposed surfaces (93b) also are recessed.
As illustrated in
The conductor layer (second conductor layer) 30 is mainly formed of copper. The second conductor layer 30 is formed of a seed layer (30a) on the first surface 22 and an electrolytic plating layer (30b) on the seed layer (30a). The seed layer (30a) is formed of a first layer (31a) on the first surface 22 and a second layer (31b) on the first layer (31a). The seed layer (30a) has a thickness of less than 0.5 μm. The first conductor layer 10 and the second conductor layer 30 are similar. A relationship between the thickness of the first layer (31a) and the thickness of the second layer (31b) is similar to the relationship between the thickness of the first layer (11a) and the thickness of the second layer (11b). The first layer (31a) and the second layer (31b) form the second conductor layer 30, and the first layer (11a) and the second layer (11b) form the first conductor layer 10. The first layer (31a) is formed of an alloy (copper alloy) similar to the first layer (11a). The second layer (31b) is formed of copper. The electrolytic plating layer (30b) is formed of copper. The first layer (31a) is in contact with the first surface 22.
The via conductor (first via conductor) 40 is formed in the opening (via conductor opening) 26. The opening 26 penetrates the first resin insulating layer 20 and reaches the first conductor layer 10. The via conductor (first via conductor) 40 connects the first conductor layer 10 and the second conductor layer 30. In
The first layer (11a) forming the first conductor layer 10, the first layer (31a) forming the second conductor layer 30, and the first layer (31a) forming the via conductor 40 are similar. The first layers (11a, 31a) are formed of the same elements. Contents of each of the elements forming the first layers (11a, 31a) are similar. The second layer (11b) forming the first conductor layer 10, the second layer (31b) forming the second conductor layer 30, and the second layer (31b) forming the via conductor 40 are similar. The second layers (11b, 31b) are formed of the same elements. The second layers (11b, 31b) are formed of substantially the same amounts of the elements. The electrolytic plating layer (10b) forming the first conductor layer 10, the electrolytic plating layer (30b) forming the second conductor layer 30, and the electrolytic plating layer (30b) forming the via conductor 40 are similar. The electrolytic plating layers (10b, 30b) are formed of the same elements. The electrolytic plating layers (10b, 30b) are formed of substantially the same amounts of the elements.
As illustrated in
The smooth film 102 has a substantially uniform thickness (T). The thickness (T) of the smooth film 102 is 10 nm or more and 120 nm or less. A ratio (S1/S2) of an area (S1) of the smooth film 102 exposed from the protruding parts 104 to an area (S2) of the adhesive layer 100 is 0.1 or more and 0.5 or less. The smooth film 102 on the second surface of the second conductor layer 30 is formed substantially along a shape of the second surface of the second conductor layer 30. When undulations are formed on the upper and side surfaces of the second conductor layer 30, the smooth film 102 follows the undulations.
The protruding parts 104 are each formed of multiple protrusions 106. Due to the multiple protrusions 106, unevenness is formed on upper surfaces of the protruding parts 104. The number of the protrusions 106 per 1 mm2 is 5 or more and 15 or less. The protruding parts 104 have heights (H1, H2) between the upper surface of the smooth film 102 and top parts of the protruding parts 104. A maximum value of the heights (H1, H2) is 10 times or more and 30 times or less the thickness (T) of the smooth film 102. The heights (H1, H2) are 200 nm or more and 450 nm or less.
The second resin insulating layer 120 is formed on the second conductor layer 30 and the first surface 22 of the first resin insulating layer 20. The second resin insulating layer 120 is formed on the second conductor layer 30 via the adhesive layer 100. The second resin insulating layer 120 has a first surface 122 and a second surface 124 on an opposite side with respect to the first surface 122. The second surface 124 of the second resin insulating layer 120 faces the second conductor layer 30. The second resin insulating layer 120 has an opening (via conductor opening) 126. The opening 126 penetrates the second resin insulating layer 120 and reaches the second conductor layer 30.
The second resin insulating layer 120 is formed of a resin 80 and inorganic particles 90. The first resin insulating layer 20 and the second resin insulating layer 120 are similar. Therefore, the resin 80 forming the second resin insulating layer 120 and the resin 80 forming the first resin insulating layer 20 are similar. The inorganic particles 90 forming the second resin insulating layer 120 and the inorganic particles 90 forming the first resin insulating layer 20 are similar. Similar to the first resin insulating layer 20, the inorganic particles 90 forming the second resin insulating layer 120 include first inorganic particles 91, second inorganic particles 92 and third inorganic particles 93. The first inorganic particles 91 in the first resin insulating layer 20 and the first inorganic particles 91 in the second resin insulating layer 120 are similar. The second inorganic particles 92 in the first resin insulating layer 20 and the second inorganic particles 92 in the second resin insulating layer 120 are similar. The third inorganic particles 93 in the first resin insulating layer 20 and the third inorganic particles 93 in the second resin insulating layer 120 are similar.
The first surface 22 of the first resin insulating layer 20 and the first surface 122 of the second resin insulating layer 120 are similar. The first surface 122 of the resin insulating layer (second resin insulating layer) 120 is formed by an upper surface (second upper surface) of the resin 80 forming the resin insulating layer (second resin insulating layer) 120 and exposed surfaces (third exposed surfaces) of exposed portions of the first inorganic particles 91 forming the resin insulating layer (second resin insulating layer) 120. The second upper surface and the third exposed surfaces form a substantially common surface. Similar to the first surface 22 of the first resin insulating layer 20, the first surface 122 of the second resin insulating layer 120 can have steps (third steps) between the second upper surface and the third exposed surfaces. The first steps and the third steps are similar. The sizes of the first steps and sizes of the third steps are similar. Even when the first surface 122 has the steps, since the sizes of the steps are small, the upper surface (second upper surface) of the resin 80 and the exposed surfaces (third exposed surfaces) of the first inorganic particles 91 are positioned substantially on the same surface.
The opening (via conductor opening) 126 penetrating the second resin insulating layer 120 and the opening (via conductor opening) 26 penetrating the first resin insulating layer 20 are similar. Therefore, an inner wall surface (second inner wall surface) 127 of the opening 126 and the inner wall surface (first inner wall surface) 27 of the opening 26 are similar. The second inner wall surface 127 is formed by the resin 80 and the flat parts (93a) of the third inorganic particles 93. Similar to the first inner wall surface 27, the second inner wall surface 127 is formed by the surface (second resin surface) of the resin 80 forming the second inner wall surface 127 and the flat parts of the third inorganic particles 93 forming the second resin insulating layer 120. Similar to the flat parts (93a) of the third inorganic particles 93 forming the first resin insulating layer 20, the flat parts of the third inorganic particles 93 forming the second resin insulating layer 120 each have an exposed surface (fourth exposed surface). The second resin surface and the fourth exposed surfaces forming the inner wall surface 127 form a substantially common surface. Similar to the first inner wall surface 27, the second inner wall surface 127 can have steps (fourth steps) between the second resin surface and the fourth exposed surfaces. The second steps and the fourth steps are similar. Sizes of the fourth steps and the sizes of the second steps are similar. Thus, even when the second inner wall surface 127 has the fourth steps, the second resin surface and the fourth exposed surfaces form a substantially common surface.
As illustrated in
A length of each side of the printed wiring board 2 is 50 mm or more. The length of each side is preferably 100 mm or more. The length of each side is 250 mm or less.
The printed wiring board 2 can have a solder resist layer on the first surface 122 of the second resin insulating layer 120 and on the third conductor layer 130. The insulating layer 4 may form a core material. The embodiment may have an adhesive layer 100 covering the second surface of the third conductor layer 130. The adhesive layer 100 is sandwiched between the third conductor layer 130 and the solder resist layer.
As illustrated in
The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. An example of the protective film 50 is a film formed of polyethylene terephthalate (PET). A release agent is formed between the protective film 50 and the resin insulating layer 20.
As illustrated in
The protective film is removed. After removing the protective film 50, the first surface 22 of the resin insulating layer 20 is cleaned. The resin 80 forming the first surface 22 is removed by a dry process. For example, the first surface 22 of the resin insulating layer 20 is cleaned by reverse sputtering. For example, cleaning the first surface 22 of the resin insulating layer 20 is performed by sputtering using an argon gas (argon sputtering).
In order to control a shape of the inner wall surface, the inner wall surface (27b) after the laser irradiation is treated. In order to control a shape of the first surface, the first surface (22b) after the cleaning is treated. It is preferable that the first protruding particles and the third protruding particles are selectively removed. As a result, the first inorganic particles 91 are formed from the inorganic particles 90. The third inorganic particles 93 are formed from the inorganic particles 90. For example, the first protruding particles and the third protruding particles are selectively removed by treating the inner wall surface (27b) after the laser irradiation and the first surface (22b) after the cleaning with a chemical. Or, the first protruding particles and the third protruding particles are selectively removed by treating the inner wall surface (27b) after the laser irradiation and the first surface (22b) after the cleaning with plasma. The selectively removing includes that an etching rate of the inorganic particles 90 is greater than an etching rate of the resin 80. For example, a difference in etching rate between the two is 10 or more times. Or, the difference in etching rate between the two is 50 or more times. Or, the difference in etching rate between the two is 100 or more times. By treating the first surface (22b) after the cleaning, the first inorganic particles 91 having the exposed portions (91P) are obtained. By treating the inner wall surface (27b) after the laser irradiation, the third inorganic particles 93 having the flat parts (93a) are obtained. By controlling conditions for treating the first surface (22b) after the cleaning, the embodiment can control the shape of the first surface 22. By controlling conditions for treating the inner wall surface (27b) after the laser irradiation, the embodiment can control the shape of the inner wall surface 27. Examples of the conditions are a temperature, a concentration, a time, a type of gas, and a pressure. The etching rate of the inorganic particles 90 and the etching rate of the resin are controlled.
The inner wall surface (27b) after the laser irradiation is treated. For example, the inner wall surface (27b) is treated with plasma of a gas containing tetrafluoromethane. By selectively removing the protruding portions (P), the inner wall surface 27 of the embodiment is formed. The third inorganic particles 93 are formed from the second inorganic particles 92. By selectively removing the protruding portions (P), the third inorganic particles 93 having the flat parts (93a) are formed. The surface forming the flat parts (93a) is a substantially flat surface. The surface forming the flat parts (93a) is a substantially curved surface. When the second inorganic particles 92 having spherical shapes are cut along a flat surface, the shapes of the third inorganic particles 93 are obtained. Or, the second inorganic particles 92 are cut along a curved surface. The third inorganic particles 93 each have a substantially spherical segment shape. The inner wall surface 27 is formed by the flat parts (93a) and the surface (80a) of the resin 80. Exposed surfaces (93b) of the flat parts (93a) and the surface (80a) of the resin 80 are positioned substantially on the same plane. For example, when the seed layer (30a) is formed on the inner wall surface (27b) by sputtering, the protruding portions (P) inhibit growth of a sputtered film. For example, it is difficult to form a continuous seed layer (30a) on the inner wall surface (27b). Or, the seed layer (30a) is increased in thickness. It is thought that in a printed wiring board having the third protruding particles, fine conductive circuits cannot be formed on the first surface 22. In the embodiment, the protruding portions (P) are removed. The embodiment can reduce the thickness of the seed layer (30a) formed by sputtering. Even when the seed layer (30a) formed by sputtering is thin, a continuous seed layer (30a) can be obtained. The seed layer (30a) has a thickness of 0.05 μm or more and less than 0.5 μm.
Forming the opening 26 includes forming the inorganic particles 90 (the second inorganic particles 92) having the protruding portions (P). The protruding portions (P) protrude from the resin 80 that forms the inner wall surface (27b) of the opening 26. The third inorganic particles 93 are formed by removing the protruding portions (P) of the inorganic particles 90 (the second inorganic particles 92). The inner wall surface 27 of the opening 26 includes the exposed surfaces (93b) of the third inorganic particles 93. The exposed surfaces (93b) of the third inorganic particles 93 are formed by removing the protruding portions (P).
Obtaining the shapes of the third inorganic particles 93 by cutting the second inorganic particles 92 having spherical shapes along a flat surface includes removing the protruding portions (P) of the inorganic particles 90. The inner wall surface 27 of the opening 26 is actually a substantially curved surface. Since the flat parts (93a) are formed by removing the protruding portions (P), the exposed surfaces (93b) of the flat parts (93a) each include a curved surface. That is, forming a common surface with the flat parts (93a) and the resin 80 includes forming the inner wall surface 27 formed with a substantially curved surface.
The first surface (22b) after the cleaning is treated. For example, the first surface (22b) is treated with plasma of a gas containing tetrafluoromethane. By selectively removing the first portions (91a), the first surface 22 of the embodiment is formed. The first inorganic particles 91 are formed from the second inorganic particles 92. As illustrated in
Forming the first surface 22 includes forming the inorganic particles (second inorganic particles 92) 90 having the first portions (91a). The first portions (91a) protrude from the upper surface (80R) of the resin 80. The first inorganic particles 91 are formed by removing the first portions (91a) of the inorganic particles (second inorganic particles 92) 90. The first surface 22 includes the exposed surfaces (91x) of the first inorganic particles 91. The exposed surfaces (91x) of the first inorganic particles 91 are formed by removing the first portions (91a).
Obtaining the shapes of the first inorganic particles 91 by cutting the second inorganic particles 92 having spherical shapes along a flat surface includes removing the first portions (91a) of the inorganic particles 90. Since the exposed portions (91P) are formed by removing the first portions (91a), the exposed surfaces (91x) of the exposed portions (91P) each include a curved surface. That is, the exposed surfaces (91x) each include a substantially curved surface.
For example, using
The inner wall surface (27b) after the laser irradiation and the first surface (22b) after the cleaning are treated at the same time. The inner wall surface (27b) after the laser irradiation and the first surface (22b) after the cleaning are treated separately. When treated separately, both are treated using the same method. Or, the two are treated using different methods.
When the inner wall surface (27b) after the laser irradiation is treated, the surface is substantially not roughened. The inner wall surface 27 has substantially no unevenness. The inner wall surface 27 is formed smooth. The surface (80a) of the resin 80 that forms the inner wall surface 27 is formed smooth. The surface (80a) of the resin 80 has substantially no unevenness. The surface (80a) of the resin 80 has an arithmetic mean roughness (Ra) of 0.2 μm or less. By controlling the conditions for treating the inner wall surface (27b) after the laser irradiation, a size of unevenness is controlled.
When the first surface (22b) after the cleaning is treated, the first surface 22 is substantially not roughened. The first surface 22 has substantially no unevenness. The first surface 22 is formed smooth. The upper surface (80R) of the resin 80 that forms the first surface 22 is formed smooth. The upper surface (80R) of the resin 80 has substantially no unevenness. The upper surface (80R) of the resin 80 has an arithmetic mean roughness (Ra) of 0.2 μm or less. By controlling the conditions for treating the first surface (22b) after the cleaning, a size of the unevenness is controlled.
The embodiment can clean the inside of the opening 26. The cleaning of the inside of the opening 26 is performed using plasma. That is, the cleaning is performed by a dry process. The cleaning includes a desmear treatment. When treating the inner wall surface (27b) after the laser irradiation includes cleaning the inside of the opening 26, the embodiment can omit the cleaning of the inside of the opening 26. When treating the first surface (22b) after the cleaning includes cleaning the inside of the opening 26, the embodiment can omit the cleaning of the inside of the opening 26. The embodiment can omit the desmear treatment.
As illustrated in
The first surface 22 has substantially no recesses. The inner wall surface 27 has substantially no recesses. The first surface 22 is formed substantially smooth. The inner wall surface 27 is formed substantially smooth. Therefore, even when the sputtered films (the first layer (31a) and the second layer (31b)) are thin, the embodiment can form a continuous seed layer (30a). As a result, the embodiment can form fine wirings.
A plating resist is formed on the seed layer (30a). The plating resist has openings for forming the first signal wiring 32, the second signal wiring 34, and the land 36. When the first surface 22 has recesses, air caused by the recesses is likely to be trapped between the plating resist and the seed layer (30a). However, in the embodiment, the first surface 22 has substantially no recesses. Therefore, the seed layer (30a) on the first surface 22 is formed substantially flat. The seed layer (30a) has substantially no recesses. Air is unlikely to remain between the plating resist and the seed layer (30a). A contact area between the plating resist and the seed layer (30a) is large. Even when a width of the plating resist for forming a space between the first signal wiring 32 and the second signal wiring 34 is 10 μm or less, the plating resist is unlikely to peel off from an upper surface of the seed layer (30a). Even when the width of the plating resist is 3 μm or more and 8 μm or less, the embodiment can form the plating resist on the seed layer (30a). Even when the width of the plating resist is 6 μm or less, the plating resist is unlikely to peel off from the seed layer (30a).
The electrolytic plating layer (30b) is formed on the seed layer (30a) exposed from the plating resist. The electrolytic plating layer (30b) is formed of copper. The electrolytic plating layer (30b) fills the opening 26. The first signal wiring 32, the second signal wiring 34, and the land 36 are formed by the seed layer (30a) and the electrolytic plating film (30b) on the first surface 22. The second conductor layer 30 is formed. The via conductor (first via conductor) 40 is formed by the seed layer (30a) and the electrolytic plating film (30b) in the opening 26. The via conductor 40 connects the pad 14 and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring. The first via conductor 40 connects the conductor layer (first conductor layer) 10 and the conductor layer (second conductor layer) 30.
The plating resist is removed. The seed layer (30a) exposed from the electrolytic plating layer (30b) is removed. The seed layer (30a) is removed by wet etching. An etching solution used in the wet etching is an aqueous solution containing hydrogen peroxide and sulfuric acid. By the wet etching, the first layer (31a) and the second layer (31b) are removed at the same time. The second conductor layer 30 and the via conductor 40 are formed at the same time.
The adhesive layer 100 is formed on upper and side surfaces of the second conductor layer 30. The adhesive layer 100 is formed by immersing an intermediate substrate having the second conductor layer 30 and the via conductor 40 in a chemical solution containing a nitrogen-based organic compound. The chemical solution has a pH or 7 or less. By immersing the intermediate substrate in the chemical solution, the adhesive layer 100 including the smoothing film 102 and the protruding parts 104 is formed on the upper and side surfaces of the second conductor layer 30. Before the intermediate substrate is immersed in the chemical solution, an oxide film on the upper and side surfaces of the second conductor layer 30 is removed. In a modified example, the adhesive layer 100 is formed by applying a chemical solution on the second conductor layer 30. When the adhesive layer 100 is formed, the intermediate substrate is taken out from the chemical solution. The adhesive layer 100 is dried. The upper surface of the adhesive layer 100 before the drying may be smooth. In this case, by the drying, a part of the adhesive layer aggregates. By the aggregating, the adhesive layer 100 including the smooth film 102 and the protruding parts 104 is formed.
The resin insulating layer (second resin insulating layer) 120 is formed on the first surface 22 of the first resin insulating layer 20 and on the second conductor layer 30, which is covered by the adhesive layer 100, using the same method as the first resin insulating layer 20. The second resin insulating layer 120 has the first surface 122, the second surface 124 on an opposite side with respect to the first surface 122, and the opening (via conductor opening) 126. The second surface 124 of the second resin insulating layer 120 faces the second conductor layer 30. When the opening 126 is formed in the resin insulating layer 120 using the laser (L), the laser (L) removes the adhesive layer 100 covering the second conductor layer 30. Or, the adhesive layer 100 is not completely removed by the laser (L). In this case, by cleaning the inside of the opening 126, the adhesive layer 100 at the bottom of the opening 126 is removed. The second conductor layer 30 is exposed by the opening 126. The conductor layer (third conductor layer) 130 is formed on the first surface 122 of the second resin insulating layer 120 using the same method as the second conductor layer 30. The via conductor (second via conductor) 140 that connects the second conductor layer 30 and the third conductor layer 130 is formed in the opening (second opening) 126 using the same method as the first via conductor 40. The printed wiring board 2 of the embodiment is obtained.
The resin insulating layers are each formed of a resin 80 and inorganic particles 90. The resin forming each of the resin insulating layers and the resin 80 forming the first resin insulating layer 20 are similar. The inorganic particles forming each of the resin insulating layers and the inorganic particles 90 forming the first resin insulating layer 20 are similar. The resin insulating layers each include first inorganic particles, second inorganic particles, and third inorganic particles. The particles in each of the resin insulating layers and the particles in the first resin insulating layer 20 are similar. The resin insulating layers each have a first surface. The first surface of each of the resin insulating layers and the first surface 22 of the first resin insulating layer 20 are similar. The resin insulating layers each have an opening (via conductor opening). The opening penetrating each of the resin insulating layers and the opening 26 penetrating the first resin insulating layer are similar. An inner wall surface of the opening penetrating each of the resin insulating layers and the inner wall surface 27 of the opening 26 penetrating the first resin insulating layer 20 are similar.
The conductor layers are each formed of a seed layer and an electrolytic plating layer on the seed layer. The seed layer forming each of the conductor layers and the seed layer (30a) forming the second conductor layer 30 are similar. The first layer forming each of the conductor layers and the first layer (31a) forming the second conductor layer 30 are similar. The second layer forming each of the conductor layers and the second layer (31b) forming the second conductor layer 30 are similar. The electrolytic plating layer forming each of the conductor layers and the electrolytic plating layer (30b) forming the second conductor layer 30 are similar.
The via conductors are each formed of a seed layer and an electrolytic plating layer on the seed layer. The seed layer forming each of the via conductors and the seed layer (30a) forming the first via conductor 40 are similar. The first layer forming each of the via conductors and the first layer (31a) forming the first via conductor 40 are similar. The second layer forming each of the via conductors and the second layer (31b) forming the first via conductor 40 are similar. The electrolytic plating layer forming each of the via conductors and the electrolytic plating layer (30b) forming the first via conductor 40 are similar.
In the printed wiring board 2 of the embodiment, even when a sputtered film is thin, the embodiment can form a continuous seed layer (30a). The inner wall surface 27 of the opening 26 is formed by the flat parts (93a) of the third inorganic particles 93 and the resin 80. The flat parts (93a) and the surface (80a) of the resin 80 that forms the inner wall surface 27 form a common surface. The inner wall surface 27 is formed smooth. Therefore, the seed layer (30a) having a uniform thickness is formed on the inner wall surface 27 of the opening 26. The seed layer (30a) is formed thin. The first surface 22 is formed by the exposed portions (91P) of the first inorganic particles 91 and the upper surface (80R) of the resin 80. The exposed surfaces (91x) and the upper surface (80R) of the resin 80 form a common surface. The first surface 22 is formed smooth. Therefore, the seed layer (30a) having a uniform thickness is formed on the first surface 22. The seed layer (30a) is formed thin. When the seed layer (30a) is removed, an etching amount is small. Therefore, an etching amount of the electrolytic plating layer (30b) is small. The second conductor layer 30 having the first signal wiring 32 and the second signal wiring 34 has a width as designed. Fine wirings are formed. A high quality printed wiring board 2 is provided.
When the first layer (31a) of the seed layer (30a) contains aluminum and the third inorganic particles 93 contain oxygen elements, the embodiment can increase the adhesive strength between the first layer (31a) and the inner wall surface 27. Even when the opening 26 has a small diameter, the via conductor 40 is unlikely to peel off from the inner wall surface 27. Therefore, connection resistance via the via conductor 40 is unlikely to increase. As illustrated in
The embodiment can reduce the thickness of the first layer (31a) forming the via conductor 40. The embodiment can reduce the thickness of the second layer (31b) forming the via conductor 40. The first layer (31a) and the second layer (31b) form the seed layer (30a). The embodiment can increase a volume of the via conductor opening after the formation of the seed layer. The via conductor opening after the formation of the seed layer may be referred to as a post-seed layer formation opening. By forming an electrolytic plating layer in the post-seed layer formation opening, a via conductor formed of the seed layer and the electrolytic plating layer is formed. Even when the via conductor opening has a small diameter, an electrolytic plating solution can easily enter the post-seed layer formation via conductor opening. The electrolytic plating layer forming the via conductor is unlikely to contain a void. A low resistance via conductor is formed. An example of a post-seed layer formation opening 260 is illustrated in
The embodiment can reduce the thickness of the first layer (31a) formed of an alloy containing aluminum. In the signal wirings, a content of aluminum is low and a content of copper is high. The embodiment can provide low-resistance signal wirings. The embodiment can provide low-resistance signal wirings with high adhesion to the resin insulating layers.
In the printed wiring board 2 of the embodiment, the first surface 22 of the resin insulating layer 20 has substantially no recesses. An increase in standard deviation of a relative permittivity in a portion near the first surface 22 of the resin insulating layer 20 is suppressed. The relative permittivity of the first surface 22 of the resin insulating layer 20 does not significantly vary depending on a location. Even when the multiple signal wirings are in contact with the first surface 22 of the resin insulating layer 20, the embodiment can reduce a difference in electrical signal propagation speed between the signal wirings. Therefore, in the printed wiring board 2 of the embodiment, noise is suppressed. Even when a logic IC is mounted on the printed wiring board 2 of the embodiment, data transmitted via the signal wirings reaches the logic IC substantially simultaneously. The embodiment can suppress malfunction of the logic IC. Even when the signal wirings each have a length of 5 mm or more, the embodiment can reduce the difference in propagation speed. Even when the signal wirings each have a length of 10 mm or more and 20 mm or less, the embodiment can suppress malfunction of the logic IC. The first surface 122 of the second resin insulating layer 120 is also similar to the first surface 22 of the resin insulating layer 20. Therefore, signal wirings in the third conductor layer 130 also have similar effects as the signal wirings in the second conductor layer 30. A high quality printed wiring board 2 is provided.
The printed wiring board 2 of the embodiment has an adhesive layer between a conductor layer and a resin insulating layer. The adhesive layer adheres the conductor layer and the resin insulating layer. Therefore, even when upper and side surfaces of a signal wiring are smooth, the resin insulating layer is unlikely to peel off from the signal wiring. Preferably, the upper and side surfaces of the signal wiring are not roughened. The adhesive layer 100 is formed of the smooth film 102, which is substantially smooth, and the protruding parts 104 protruding from the smooth film 102. The adhesive layer 100 has unevenness formed by the protruding parts 104 and the smooth film 102. The adhesive layer 100 has unevenness formed by the multiple protrusions 106. Therefore, the second conductor layer 30 and the second resin insulating layer 120 are sufficiently adhered to each other via the adhesive layer 100. A high quality printed wiring board 2 is provided. For example, even when each side of the printed wiring board 2 has a length of 50 mm or more, the second resin insulating layer 120 is unlikely to peel off from the second conductor layer 30. Even when each side of the printed wiring board 2 has a length of 100 mm or more, a crack caused by the adhesive layer 100 is unlikely to occur in the second resin insulating layer 120. Even when the second conductor layer 30 includes a conductor circuit having a width of 5 μm or less, the second resin insulating layer 120 is unlikely to peel off from the second conductor layer 30. Even when the second conductor layer 30 includes a conductor circuit having a width of 3 μm or less, a crack caused by the adhesive layer 100 is unlikely to occur in the second resin insulating layer 120.
When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and the third inorganic particles 93 on the inner wall surface contain silicon. The first layer on the first surface and the first inorganic particles 91 contain silicon. It is thought that the two are strongly bonded to each other via silicon. The seed layer formed of an alloy containing copper, aluminum, and silicon is unlikely to peel off from the inner wall surface. The seed layer is unlikely to peel off from the first surface. The seed layer is unlikely to peel off from the resin insulating layer.
When the first layer contains aluminum and the inorganic particles 90 (the first inorganic particles 91, the second inorganic particles 92, and the third inorganic particles 93) contain oxygen, it is thought that the first layer and the inorganic particles 90 (oxygen-containing inorganic particles such as glass particles) are strongly bonded to each other. When the first layer contains aluminum and the inorganic particles 90 contain oxygen, the first layer may be formed of copper, aluminum, and impurities.
In a first alternative example of the embodiment, the specific metal is selected from titanium, nickel, chromium, tin and calcium.
In a second alternative example of the embodiment, the first layers (11a, 31a) of the seed layers (10a, 30a) are each formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, and calcium. The first layers (11a, 31a) are formed of an alloy containing copper. The second layers (11b, 31b) are formed of copper. A content of copper forming the second layers (11b, 31b) is 99.9 at % or more, The content of copper is preferably 99.95 at % or more.
The four resin insulating layers include a first resin insulating layer 20, a second resin insulating layer 120, a third resin insulating layer 220, and a fourth resin insulating layer 320. The first resin insulating layer 20 and second resin insulating layer 120 are the same as those of the embodiment. The third resin insulating layer 220 and the fourth resin insulating layer 320 have the same structure (resin and inorganic particles) as the first resin insulating layer 20. The first resin insulating layer 20, the second resin insulating layer 120, the third resin insulating layer 220, and the fourth resin insulating layer 320 are formed using the same method as that for the resin insulating layer 20 of the embodiment. The first resin insulating layer 20, the second resin insulating layer 120, the third resin insulating layer 220, and the fourth resin insulating layer 320 respectively have openings (26, 126, 226, 326).
The build-up layer 500 has four via conductors (40, 140, 240, 340). The via conductor 40 is formed in the opening 26 and connects the first conductor layer 10 and the second conductor layer 30. The via conductor 140 is formed in the opening 126 and connects the second conductor layer 30 and the third conductor layer 130. The via conductor 240 is formed in the opening 226 and connects the third conductor layer 130 and the fourth conductor layer 230. The via conductor 340 is formed in the opening 326 and connects the fourth conductor layer 230 and the fifth conductor layer 330. The openings (via conductor openings) (26, 126, 226, 326) that are respectively formed in the resin insulating layers (20, 120, 220, 320) are similar and have similar inner wall surfaces. The three via conductors (140, 240, 340) are stacked directly on the via conductor 40. The four via conductors (40, 140, 240, 340) form a stacked via.
The printed wiring board 502 of the modified example includes the five conductor layers (10, 30, 130, 230, 330) and the stacked via formed by the four via conductors (40, 140, 240, 340). When the printed wiring board 502 is used, a large stress is applied to a connecting portion between the lowermost via conductor 40 and the first conductor layer 10 such as the pad 14. However, in the modified example, connection reliability between the via conductor 40 and the first conductor layer 10 is high. Connection resistance via the via conductor 40 is unlikely to increase.
The build-up layer 500 includes 5 or more conductor layers. The build-up layer 500 preferably has 10 or more conductor layers. The number of the conductor layers is 20 or less.
The cross-sectional views are each obtained by cutting the printed wiring board 2 along a plane perpendicular to the first surface 22. When a cross-sectional view includes a conductor circuit, a side surface of the conductor circuit is perpendicular to the cross-sectional view.
In the present specification, the term “flat surface” is used with respect to the shape of the inner wall surface 27, the shapes of the flat parts (93a), and the shapes of the third inorganic particles 93. The meaning of the “flat surface” used with respect to these is illustrated in
Japanese Patent Application Laid-Open Publication No. 2015-126103 describes a printed wiring board having a first conductor layer, an insulating layer formed on the first conductor layer, and a second conductor layer formed on the insulating layer. The insulating layer has a via conductor through hole exposing the first conductor layer. A via conductor connecting the first conductor layer and the second conductor layer is formed in the through hole. The via conductor is formed of an electroless plating layer and an electrolytic plating layer. The insulating layer contains a resin and inorganic particles.
As illustrated in FIG. 17 of Japanese Patent Application Laid-Open Publication No. 2015-126103, in Japanese Patent Application Laid-Open Publication No. 2015-126103, an intermediate layer is provided on a wall surface (inner circumferential surface) of the through hole. The intermediate layer has a complex uneven surface due to gaps formed between the inorganic particles. The inorganic particles contained in the intermediate layer are the same as the inorganic particles contained in the insulating layer. As illustrated in FIG. 18 of Japanese Patent Application Laid-Open Publication No. 2015-126103, in Japanese Patent Application Laid-Open Publication No. 2015-126103, an electroless plating film is formed in the through hole. The electroless plating film follows the unevenness formed in the intermediate layer. Or, the gaps formed in the intermediate layer are filled with the electroless plating film. However, when the unevenness is complex, it is thought to be difficult to completely fill the gaps with the electroless plating film. When the electroless plating film is deposited, it is thought that a gas generated by a reaction inhibits the filling of the gaps. When the gaps are not completely filled with the electroless plating film, it is thought that voids are generated between the wall surface of the through hole and the electroless plating film. When the voids expand due to heat, it is thought that the electroless plating film peels off from the wall surface of the through hole.
A printed wiring board according to an embodiment of the present invention includes: a first conductor layer; a resin insulating layer that has a first surface and a second surface on an opposite side with respect to the first surface, an opening extending from the first surface to the second surface, and is laminated on the first conductor layer such that the second surface faces the first conductor layer; a second conductor layer that is formed on the first surface of the resin insulating layer; and a via conductor that is formed in the opening and connects the first conductor layer and the second conductor layer. The resin insulating layer contains a resin and inorganic particles. The inorganic particles include first inorganic particles forming the first surface and second inorganic particles embedded in the resin. The first inorganic particles each have a substantially flat exposed portion. The resin has an upper surface forming the first surface. The first surface is formed by the upper surface of the resin and the exposed portions of the first inorganic particles.
In a printed wiring board according to an embodiment of the present invention, substantially no recesses are formed on the first surface of the resin insulating layer. Therefore, when a seed layer is formed by sputtering on the resin insulating layer, the embodiment can form a continuous seed layer even when a sputtered film is thin. As a result, when the seed layer is removed, the embodiment can reduce an etching amount. The embodiment can form fine signal wirings.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-128273 | Aug 2023 | JP | national |
