Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same

Abstract

High quality epitaxial layers of monocrystalline materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer (104) on a silicon wafer (102). The accommodating buffer layer (104) is a layer of monocrystalline material spaced apart from the silicon wafer (102) by an amorphous interface layer (108) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Utilizing this technique permits the fabrication of thin film pyroelectric devices (150) on a monocrystalline silicon substrate.

Description

FIELD OF THE INVENTION

This invention relates generally to semiconductor structures and devices and to a method for their fabrication, and more specifically to pyroelectric devices and integrated circuits fabricated on a monocrystalline material.

BACKGROUND OF THE INVENTION

Various metallic oxides, such as perovskites, exhibit desirable characteristics such as piezoelectric, pyroelectric, ferroelectric, ferromagnetic, colossal magnetic resistance, and super conductivity properties. Such oxides may be included or used in connection with microelectronic devices that take advantage of these characteristics. For example, metallic oxides may be used to form pyroelectric imaging devices and the like.

For many years attempts have been made to grow thin films of various metallic oxide materials on a foreign substrate because of the desirable characteristics of the metallic oxide materials, and because of their present generally high cost and low availability in bulk form. To achieve optimal characteristics of metallic oxide material, however, a monocrystalline film of high crystalline quality is desired. Attempts have been made, for example, to grow layers of a monocrystalline metallic oxide material on substrates such as silicon. These attempts have generally been unsuccessful because lattice mismatches between the host crystal and the grown crystal have caused the resulting thin film of metallic oxide material to be of low crystalline quality. Metallic oxides of higher quality have been grown over oxide substrates such as bulk strontium titanate. Metallic oxides grown over oxide substrates are often expensive because, in part, the oxide substrate is small and expensive.

If a large area thin film of high quality monocrystalline metallic oxide material was available at low cost, a variety of semiconductor devices could advantageously be fabricated using that film at a low cost compared to the cost of fabricating such devices on a bulk wafer of the metallic oxide material or in an epitaxial film of such material on a bulk wafer of oxide material. In addition, if a thin film of high quality monocrystalline metallic oxide material could be realized on a bulk wafer such as a silicon wafer, an integrated device structure could be achieved that took advantage of the best properties of both the silicon and the metallic oxide material.

Several perovskite thin films are known to have at room temperature pyroelectric properties that are suitable for infrared detection devices. Pyroelectric detectors are designed to absorb infrared radiation that gives rise to a temperature increase which causes a change in the polarization of the pyroelectric materials. The change in polarization results in current production that can be detected by an integrated circuit. Critical factors for selecting a pyroelectric detector include pyroelectric current and response time. The sensitivity of a pyroelectric detector is primarily dependent on the magnitude of the pyroelectric coefficient, p, according to the equation:

I=pAΔT/Δt

where I is the current produced by the pyroelectric device, A is the area of the pyroelectric device, ΔT is the change in temperature detected by the pyroelectric device and Δt is the change in time of a given measurement. The magnitude of the pyroelectric coefficient p is dependent on the crystalline quality of the pyroelectric materials. Monocrystalline films have a higher pyroelectric coefficient compared to polycrystalline films. Thus, the sensitivity of the temperature detection may increase and the device area may decrease while still maintaining the same sensitivity level.

Sandia National Laboratories has successfully integrated a polycrystalline Pb(Zr, Ti)O 3 pyroelectric thin film into a CMOS architecture using an aerogel thermal isolation layer. See “Investigation of PZT//LSCO//Pt//Aerogel Thin Film Composites For Uncooled Pyroelectric IR Detectors,” Mat. Res. Soc. Symp., Vol. 541, pg. 661 (1999). However, the integration of monocrystalline pyroelectric thin films using PZT, Pb(Se, Ta)O 3 and other perovskite films on a substrate, has not been obtained.

Accordingly, a need exists for a pyroelectric detection device formed using a thin film of high quality monocrystalline oxide material formed on a bulk wafer. A need further exists for a thin film perovskite pyroelectric detection device that is monolithically integrated with a CMOS device on a monocrystalline substrate and that does not require cooling to operate.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements, and in which:

FIGS. 1-2 illustrate schematically, in cross section, device structures in accordance with various embodiments of the invention;

FIG. 3 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer;

FIG. 4 illustrates schematically, in cross-section, an exemplary embodiment of a pyroelectric detector fabricated on a semiconductor substrate according to the present invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically, in cross section, a portion of a microelectronic structure 20 in accordance with an embodiment of the invention. Microelectronic structure 20 includes a monocrystalline substrate 22 , accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline conductive oxide material. In this context, the term “monocrystalline” shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.

In accordance with one embodiment of the invention, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24 . Structure 20 may also include a template layer 30 between the accommodating buffer layer and monocrystalline oxide layer 26 . As will be explained more fully below, the template layer helps to initiate the growth of the conductive oxide layer on the accommodating buffer layer. The amorphous intermediate layer helps to relieve the strain in the accommodating buffer layer and, by doing so, aids in the growth of a high crystalline quality accommodating buffer layer.

Substrate 22 , in accordance with an embodiment of the invention, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Substrate 22 can also be of a compound semiconductor material. The compound semiconductor material of substrate 22 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II(A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs), gallium indium arsenide (GaInAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP), cadmium sulfide (CdS), cadmium mercury telluride (CdHgTe), zinc selenide (ZnSe), zinc sulfur selenide (ZnSSe), and the like.

Preferably, substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate. In accordance with one embodiment of the invention, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer by the oxidation of substrate 22 during the growth of layer 24 . The amorphous intermediate layer serves to relieve strain that might otherwise occur in the monocrystalline accommodating buffer layer as a result of differences in the lattice constants of the substrate and the buffer layer. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by the amorphous intermediate layer, the strain may cause defects in the crystalline structure of the accommodating buffer layer. Defects in the crystalline structure of the accommodating buffer layer, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline conductive oxide layer 26 .

Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with the underlying substrate and with the overlying conductive oxide material. For example, the material could be an oxide or nitride having a lattice structure closely matched to the substrate and to the subsequently applied conductive oxide material. Materials that are suitable for the accommodating buffer layer include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for the accommodating buffer layer. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements and have a perovskite crystalline structure. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.

Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22 , and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 24 . Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm.

The conductive oxide material of layer 26 can be selected, as desired for a particular structure or application. For example, layer 26 can include perovskite materials such as (La, Sr)CoO 3 , SrRuO 3 , SrVO 3 , BaRuO 3 , BaVO 3 and (La, Ca)MnO 3 , having a thickness in the range of about 2 to 200 nm.

Suitable template materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent conductive oxide layer 26 . When used, template layer 30 has a thickness ranging from about 1 to about 10 monolayers.

FIG. 2 illustrates, in cross section, a portion of a microelectronic structure 40 in accordance with a further embodiment of the invention. Structure 40 is similar to the previously described semiconductor structure 20 , except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline layer 26 . Specifically, the additional buffer layer is positioned between template layer 30 and the overlying layer 26 . The additional buffer layer serves to provide a lattice compensation when the lattice constant of the accommodating buffer layer cannot be adequately matched to the overlying monocrystalline layer. The additional buffer layer 32 also serves as thermal insulator, blocking heat that may adversely affect an integrated circuit (described below) formed in substrate 22 .

The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20 and 40 in accordance with various alternative embodiments of the invention. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.

EXAMPLE 1

In accordance with one embodiment of the invention, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction. The silicon substrate can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment of the invention, accommodating buffer layer 24 is a monocrystalline layer of Sr z Ba 1−z TiO 3 where z ranges from 0 to 1 and the amorphous intermediate layer is a layer of silicon oxide (SiO x ) formed at the interface between the silicon substrate and the accommodating buffer layer. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer 26 . The accommodating buffer layer can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 5 nm. In general, it is desired to have an accommodating buffer layer thick enough to isolate the conductive layer from the substrate to obtain the desired properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1 to 2 nm.

In accordance with this embodiment of the invention, conductive material layer 26 is a layer of (La,Sr)CoO 3 having a thickness of about 2 to about 200 nm and preferably a thickness of about 10 to about 100 nm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the (La,Sr)CoO 3 on the monocrystalline oxide, a template layer is formed by capping the oxide layer.

EXAMPLE 2

In accordance with another embodiment of the invention, a structure is provided that is suitable for the growth of an epitaxial film of pyroelectric material overlying a conductive material as illustrated in FIG. 2 . The substrate is preferably a silicon wafer as described above. A suitable accommodating buffer layer material is Sr x Ba 1−x TiO 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The conducting oxide can be (La, Sr)CoO 3 , having a thickness of about 2 to about 200 nm and preferably a thickness of about 10 to about 100 nm. A template layer to facilitate growth of an additional layer of monocrystalline material may be formed. The additional layer of monocrystalline material can be SrTiO 3 having a thickness of 2 to 200 nm and preferably a thickness of about 10 to 100 nm. A layer of pyroelectric material may be deposited overlying the conducting oxide layer and may include Pb(Ti, Zr)O 3 , having a thickness of about 2 to about 200 nm and preferably a thickness of about 100 to about 1000 nm.

Referring again to FIGS. 1-2 , substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of the accommodating buffer layer and the monocrystalline substrate must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms “substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.

FIG. 3 graphically illustrates the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal. Curve 42 illustrates the boundary of high crystalline quality material. The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.

In accordance with one embodiment of the invention, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material by 45° with respect to the crystal orientation of the silicon substrate wafer. The inclusion in the structure of amorphous interface layer 28 , a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer that might result from any mismatch in the lattice constants of the host silicon wafer and the grown titanate layer. As a result, in accordance with an embodiment of the invention, a high quality, thick, monocrystalline titanate layer is achievable.

Still referring to FIGS. 1-2 , layer 26 is a layer of epitaxially grown conductive oxide material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22 . To achieve high crystalline quality in this epitaxially grown monocrystalline layer, the accommodating buffer layer must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26 , substantial matching between the crystal lattice constant of the host crystal, in this case, the monocrystalline accommodating buffer layer, and the grown crystal is desired. With properly selected materials, this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of the grown crystal with respect to the orientation of the host crystal. In some instances, a crystalline buffer layer between the host oxide and the grown conductive oxide layer can be used to reduce strain in the grown monocrystalline conductive oxide layer that might result from small differences in lattice constants. Better crystalline quality in the grown monocrystalline conductive oxide layer can thereby be achieved.

The following example illustrates a process, in accordance with one embodiment of the invention, for fabricating a microelectronic structure such as the structures depicted in FIGS. 1-2 . The process starts by providing a monocrystalline semiconductor substrate comprising silicon or germanium. In accordance with a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer having a (100) orientation. The substrate is preferably oriented on axis or, at most, about 4° off axis. At least a portion of the semiconductor substrate has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term “bare” in this context means that the surface in the portion of the substrate has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term “bare” is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process in accordance with the invention. In order to epitaxially grow a monocrystalline oxide layer overlying the monocrystalline substrate, the native oxide layer must first be removed to expose the crystalline structure of the underlying substrate. The following process is preferably carried out by molecular beam epitaxy (MBE), although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate is then heated to a temperature of about 850° C. to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2×1 structure, includes strontium, oxygen, and silicon. The ordered 2×1 structure forms a template for the ordered growth of an overlying layer of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer.

In accordance with an alternate embodiment of the invention, the native silicon oxide can be converted and the substrate surface can be prepared for the growth of a monocrystalline oxide layer by depositing an alkali earth metal oxide, such as strontium oxide, strontium barium oxide, or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 850° C. At this temperature, a solid state reaction takes place between the strontium oxide and the native silicon oxide, causing the reduction of the native silicon oxide and leaving an ordered 2×1 structure with strontium, oxygen, and silicon remaining on the substrate surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer.

Following the removal of the silicon oxide from the surface of the substrate, in accordance with one embodiment of the invention, the substrate is cooled to a temperature in the range of about 200-800° C. and a layer of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stoichiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer at the interface between the underlying substrate and the growing strontium titanate layer. The growth of the silicon oxide layer results from the diffusion of oxygen through the growing strontium titanate layer to the interface where the oxygen reacts with silicon at the surface of the underlying substrate. The strontium titanate grows as an ordered monocrystal with the crystalline orientation rotated by 45° with respect to the ordered 2×1 crystalline structure of the underlying substrate. Strain that otherwise might exist in the strontium titanate layer because of the small mismatch in lattice constant between the silicon substrate and the growing crystal is relieved in the amorphous silicon oxide intermediate layer.

After the strontium titanate layer has been grown to the desired thickness, the monocrystalline strontium titanate may be capped by a template layer that is conducive to the subsequent growth of an epitaxial layer of a desired conductive oxide material. For example, the MBE growth of the strontium titanate monocrystalline layer can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of the template (if one is formed), the conductive oxide material is grown using MBE or other suitable techniques.

The process described above illustrates a process for forming a semiconductor structure including a silicon substrate, an overlying oxide layer, and a monocrystalline conductive oxide layer by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer epitaxy (ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), or the like. Further, by a similar process, other monocrystalline accommodating buffer layers such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other conductive oxide layers can be deposited overlying the monocrystalline oxide accommodating buffer layer.

Each of the variations of conductive oxide layers, pyroelectric layers, and monocrystalline oxide accommodating buffer layers may use an appropriate template for initiating the growth of the respective layer. In such a case, suitable template materials may be grown according to the methods described above in connection with growing layer 26 .

FIG. 4 illustrates a device structure 150 in accordance with a further embodiment of the present invention. Structure 150 includes a first region 152 in which an electrical component 114 is formed within a substrate 102 and a second region 154 in which a pyroelectric element 100 is formed using a pyroelectric layer 110 . To fabricate pyroelectric element 100 , a monocrystalline substrate 102 such as silicon functions as the starting material. A monocrystalline perovskite accommodating buffer layer 104 is then grown epitaxially over substrate 102 and an amorphous intermediate layer 106 may be formed between substrate 102 and layer 104 by the oxidation of substrate 102 during the growth of layer 104 . Element 100 is similar to structure 20 , except that a template layer is not illustrated in FIG. 4 . Nevertheless, element 100 may include a template layer between any adjacent monocrystalline layers as described herein. In a preferred embodiment, substrate 102 is a silicon substrate, and layer 104 is an insulative oxide layer of perovskite, as discussed above in connection with layer 24 , illustrated in FIGS. 1-2 above. In a particularly preferred embodiment, layer 104 may be formed from material from the group which includes, but is not limited to, BaTiO 3 , SrTiO 3 , and CaTiO 3 and may have a thickness in the range of about 2-100 nm.

Next, a monocrystalline perovskite-conducting layer 108 is epitaxially deposited over accommodating buffer layer 104 . Conducting layer 108 behaves as either a metallic conductor or a semiconductor. In a preferred embodiment, conducting layer 108 is a monocrystalline perovskite oxide material. Exemplary materials suitable for forming conducting layer 108 include, but are not limited to, (La, Sr)CoO 3 , SrRuO 3 , SrVO 3 , BaRuO 3 , BaVO 3 , and (La, Ca)MnO 3 . Conducting layer 108 preferably exhibits a thickness in the range of about 2 nm to 200 nm.

A pyroelectric layer 110 is deposited on conducting layer 108 . Exemplary pyroelectric materials suitable for pyroelectric layer 110 include perovskite metallic oxides such as Pb(Ti, Zr)O 3 , PbTiO 3 , BaTiO 3 , Pb(Sc, Ta)O 3 , Bi(Ti, Zr) 3 O 12 , SrBi 2 (Ta, Nb) 2 O 9 , and YMnO 3 . Pyroelectric layer 110 preferably exhibits a thickness in the range of about 2 to 200 nm.

An electrode layer 112 is formed overlying pyroelectric layer 110 . Electrode layer 112 can be formed of any suitable conductive material such as Ni, Cr, Pt, Ir, Ti and the like and preferably absorbs infrared radiation of a wavelength in the range of about 8 μm to 12 μm. Alternatively, electrode layer 112 may also be formed of a monocrystalline perovskite conducting oxide, such as those materials used to form conducting layer 108 , for example, (La, Sr)CoO 3 .

Pyroelectric element 100 is coupled to a CMOS device 114 via a suitable interconnect 116 to form a pyroelectric imaging device, such as those used for motion detection or thermal imaging. CMOS device 114 may comprise a device such as a MOSFET which is formed by conventional semiconductor processing as is well known and widely practiced in the semiconductor industry. To enhance contact between pyroelectric device 100 and CMOS device 114 , a metal layer (not shown) may be deposited overlying conducting layer 108 before pyroelectric layer 110 is deposited thereon. A plurality of pyroelectric imaging devices which detect the same or different wavelengths of infrared radiation may then be combined in an array which produces an image corresponding to the received infrared radiation.

To reduce the thermal capacity and thermal conduction into substrate 102 , a portion of substrate 102 is preferably removed proximate pyroelectric element 100 . In accordance with one embodiment of the invention, the portion of substrate 102 is removed using an etch which selectively etches material of substrate 102 relative to material comprising layer 104 , that is, layer 104 may serve as an etch-stop. In another alternative embodiment of the invention, if layer 104 is formed sufficiently thick, it may serve as a thermal insulating layer, thereby thermally isolating substrate 102 from the pyroelectric layer 110 and reducing the thermal conduction of substrate 102 . Accordingly, it may not be necessary to remove a portion of substrate 102 proximate pyroelectric element 100 . Similarly, in yet another alternative embodiment, a thermal insulation layer such as BaTiO 3 , SrTiO 3 and CaTiO 3 may be epitaxially grown on accommodating buffer layer 104 before the formation of conduction layer 108 . The thermal insulation layer would serve to thermally insulate substrate 102 , thereby rendering the selective etching of substrate 102 proximate to the pyroelectric device unnecessary.

It should be noted that the steps of epitaxially growing or depositing the various layers includes epitaxially growing or depositing layers by processes such as MBE, MOCVD, MEE, CVD, PVD, CSD and ALE as previously indicated with respect to the processing steps described above for fabricating the structures shown in FIGS. 1-3 .

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, solution to occur or become more pronounced are not to be constructed as critical, required, or essential features or elements of any or all of the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A pyroelectric detector circuit comprising:a monocrystalline silicon substrate; a portion of a MOS circuit formed in the monocrystalline silicon substrate; a first monocrystalline perovskite layer formed of material selected from the group comprising BaTiO3, SrTiO3, and CaTiO3 and epitaxially grown overlying the silicon substrate; a second monocrystalline perovskite layer formed of material selected from the group comprising (La, Sr)CoO3, SrRuO3, SrVO3, BaRuO3, BaVO3 and (La, Ca)MnO3 overlying the first monocrystalline pyroelectric layer; a monocrystalline pyroelectric layer formed of perovskite material from the group comprising Pb(Ti, Zr)O3, PbTiO3, BaTiO3, Pb(Sc, Ta)O3, Bi(Ti, Zr)3O12, SrBi2(Ta, Nb)2O9 and YMnO3; and an electrical connection electrically coupling the portion of a MOS circuit and the second monocrystalline perovskite layer.

2. The pyroelectric detector circuit of claim 1, further comprising a metal layer overlying the monocrystalline pyroelectric layer.

3. The pyroelectric detector circuit of claim 1, further comprising a third monocrystalline perovskite layer overlying the monocrystalline pyroelectric layer.

4. The pyroelectric detector circuit of claim 1, further comprising an amorphous layer of silicon oxide overlying the monocrystalline silicon substrate.

5. The pyroelectric detector circuit of claim 2, wherein the metal layer is formed from material selected from the group comprising Ni, Cr, Pt, Sr, and Ti.

6. The pyroelectric detector circuit of claim 3, wherein the third monocrystalline perovskite layer is formed of material selected from the group comprising (La,Sr)CoO3, SrRuO3, SrVO3, BaRuO3, BaVO3, and (La,Ca)MnO3.