Patent Application
20160377554
This disclosure relates to a quality evaluation method for a silicon wafer, and a silicon wafer and a method of producing a silicon wafer using the method. This disclosure relates in particular to a quality evaluation method for a silicon wafer making it possible to determine with high accuracy whether or not slip dislocations are formed after heat treatment is performed in a device fabrication process, and a silicon wafer and a method of producing a silicon wafer using the method.
For example, commonly, oxygen inevitably contained in a polished wafer made by the Czochralski (CZ) process is partly precipitated to form a gettering site in the device fabrication process.
Here, when heat treatment is performed on a silicon wafer, oxygen contained in the wafer reacts with silicon to form oxygen precipitates (bulk micro defects, BMDs), It is known that if this oxygen precipitation excessively proceeds, the mechanical strength of the silicon wafer decreases, slip dislocations are formed even under low load stress in the device fabrication process, and the wafer is warped (for example, see NPL 1 (B. Leroy and C. Plougonven, Journal of the Electrochemical Society, 1980, Vol. 127, p. 961) and NPL 2 (Hirofumi Shimizu, Tetsuo Watanabe and Yoshiharu
Kakui, Japanese Journal of Applied Physics, 1985, Vol. 24, p. 815)). Further, PL 3 (Koji Sueoka, Masanori Akatsuka, Katahama and Naoshi Adachi, Japanese Journal of Applied Physics, 1997, Vol. 36, p. 7095) describes that a larger size of BMDs increases the formation of slip dislocations caused when a thermal stress is applied to a wafer.
Since such a formation of slip dislocations caused in a device fabrication process reduces the yield of silicon devices, it is important to provide a silicon wafer in which slip dislocations are not formed even after heat treatment in the device fabrication process is performed. With respect to the control of such slip dislocations, WO 2006/003812 A (PTL 1) describes that a reduced size of BMDs increases the stress causing the formation of slip dislocations from the BMDs, which suppresses the reduction in the strength of the silicon wafer caused by oxygen precipitations.
Further, JP 2008-103673 A (PTL 2) describes that BMDs having a small size are densely formed in the wafer and the density of BMDs having a large size is minimized, thereby effectively suppressing the formation of slip dislocations.
PTL 1: W( )2006/003812 A
PTL 2: JP 2008-103673 A
NPL 1: B. Leroy and C. Plougonven, Journal of the Electrochemical Society, 1980, Vol. 127, p. 961
NPL 2: Hirofumi Shimizu, Tetsuo Watanabe and Yoshiharu Kakui, Japanese Journal of Applied Physics, 1985, Vol. 24, p. 815
NPL 3: Koji Sueoka, Masanori Akatsuka, Hisashi Katahama and Naoshi Adachi, Japanese Journal of Applied Physics, 1997, Vol. 36, p. 7095
In recent years, since rapid heating and cooling processes are mostly used in silicon device fabrication processes, silicon wafers are subjected to more severe thermal stress than conventional ones, which results in an environment in which slip dislocations are easily formed in the silicon wafers.
PTLs 1 and 2 describe the association of the size and the density of
BMDs with the formation of slip dislocations; however, the methods of PTLs 1 and 2 are not sufficiently capable of preventing the formation of slip dislocations under such a severe environment.
Given the facts, it could be helpful to propose a quality evaluation method for a silicon wafer making it possible to determine with high accuracy whether or not slip dislocations are formed after heat treatment is performed in a device fabrication process, and a silicon wafer and a method of producing a silicon wafer using the method.
The inventors of this disclosure diligently studied ways to solve the above problems. In a previous application (JP 2011-238664 A, JP 5533210 B), the inventors proposed a heat treatment method in which suitable heat treatment is performed on a silicon wafer in the wafer production stage in order to prevent slip dislocations from being formed in a device fabrication process. Further, they found that the critical shear stress τcri at which slip dislocations are formed in the device fabrication process is closely related to the ratio of the residual oxygen concentration Co (concentration of oxygen left in a wafer having been subjected to heat treatment performed in the wafer production stage) with respect to the BMD size L, expressed as Co/L (that is, the product of the reciprocal of L, i.e., l/L and Co)
However, whereas the size L of BMDs in a silicon wafer increases as time passes, the residual oxygen concentration Co decreases. In other words, as time passes, the critical shear stress τcri at which slip dislocations are formed decreases, which causes slip dislocations to be easily formed. Accordingly, in order to produce a silicon wafer in which slip dislocations are not formed in the device fabrication process, considering the change of the BMD size L and the residual oxygen concentration Co in the device fabrication process, it is important to find the critical shear stress τcri based on the BMD size L and the residual oxygen concentration Co “after the heat treatment performed in the device fabrication process”.
The BMD size L is typically measured using a transmission electron microscope (TEM), which results in the variations in the measured values and furthermore takes a long time for the measurement. To address these problems, the inventors conceived of measuring the precipitated oxygen concentration ΔOi in place of the BMD size L. That is, the BMD size L and the precipitated oxygen concentration ΔOi have a ratio of 1:1, and the BMI) size L is proportional to the precipitated oxygen concentration ΔOi. Further, since the measurement of the precipitated oxygen concentration ΔOi is performed by measuring the value of the whole bulk using a Fourier transform infrared spectrometer (FT-IR), the measured values are less varied and the measurement itself is significantly simple. For this reason, they conceived of measuring the precipitated oxygen concentration ΔOi in place of the BMD size L.
Further, as a result of further studies to determine the critical shear stress τcri with higher accuracy, the inventors found that it is significantly effective to formulate the critical shear stress τcri as the sum of the reciprocal of the precipitated oxygen concentration ΔOi, i.e., l/ΔOi and the residual oxygen concentration Co in a silicon wafer after heat treatment performed in the device fabrication process. They also found that a comparison of the critical shear stress τcri estimated by the thus obtained formula and the thermal stress τ applied to a silicon wafer in heat treatment of the device fabrication process makes it possible to determine whether or not slip dislocations are formed in the device fabrication process and to evaluate the quality (determine the pass/fail) of the silicon wafer. Thus, they accomplished the present invention.
Specifically, we propose the following features.
(1) A quality evaluation method for a silicon wafer, comprising the steps of:
(2) The quality evaluation method for a silicon wafer, according to (1) above, wherein the critical shear stress τcri is given by Formula (A) below, where ΔOi: the precipitated oxygen concentration, Co: the residual oxygen concentration, I′: the temperature of the heat treatment, and k: the Boltzmann constant.
τcri=24.6×(l/ΔOi)+7.0×10−5×Co×exp(0.91eV/kT) (A)
(3) The quality evaluation method for a silicon wafer, according to (1) above, wherein the step of determining the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co after heat treatment in the device fabrication process is performed by measuring the precipitated oxygen concentration and the residual oxygen concentration in the silicon wafer after the heat treatment performed on the silicon wafer in the device fabrication process.
(4) The quality evaluation method for a silicon wafer, according to (1) above, wherein the step of determining the precipitated oxygen concentration and the residual oxygen concentration Co after the heat treatment in the device fabrication process is performed by simulation calculation.
(5) The quality evaluation method for a silicon wafer, according to (1) above, wherein the thermal stress τ is estimated based on the temperature distribution in the radial direction of the silicon wafer having been heated by being loaded into a heat treatment unit.
(6) The quality evaluation method for a silicon wafer, according to (1) above, wherein the thermal stress τ is estimated by simulation calculations.
(7) A method of producing a silicon wafer, comprising the steps of:
(8) The method of producing a silicon wafer, according to (7) above, wherein the precipitated oxygen concentration after heat treatment in the device fabrication process is 0.06×1017 atoms/cm3 or more and 0.8×1017 atoms/cm3 or less.
(9) The method of producing a silicon wafer, according to (7) above, wherein the residual oxygen concentration after heat treatment in the device fabrication process is 10×107 atoms/cm3 or more and 18×1017 atoms/cm3 or less.
(10) A silicon wafer having a precipitated oxygen concentration and a residual oxygen concentration, at which the thermal stress τ obtained in a device fabrication process is lower than the critical shear stress τcri at which slip dislocations are formed in the device fabrication process.
(11) The silicon wafer according to (10) above, wherein the precipitated oxygen concentration after heat treatment in the device fabrication process is 0.06×1017 atoms/cm3 or more and 0.8×1017 atoms/cm3 or less.
(12) The silicon wafer according to (10) above, wherein the residual oxygen concentration after heat treatment in the device fabrication process is 10×1017 atoms/cm3 or more and 18×1017 atoms/cm3 or less.
Thus, the critical shear stress at which slip dislocations are formed in a device fabrication process is determined with high accuracy, thereby determining with high accuracy whether or not slip dislocations are formed in a silicon wafer due to heat treatment of the device fabrication process.
In the accompanying drawings:
Embodiments will now be described with reference to the drawings.
Next, the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co in the silicon wafer W after heat treatment performed in the device fabrication process are determined in Step S2. Here, the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co in the silicon wafer W “after heat treatment performed in the device fabrication process” are determined.
The precipitated oxygen concentration ΔOi and the residual oxygen concentration Co “after heat treatment in the device fabrication process” herein can be determined by actually performing a heat treatment performed in a device fabrication process on the silicon wafer W or a heat treatment designed to emulate the heat treatment performed in the device fabrication process and by measuring the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co after the heat treatment. Such a heat treatment can be performed using a rapid thermal annealing (RTA) system or the like.
In this disclosure, when a heat treatment performed in a device fabrication process includes a plurality of steps, the heat treatment temperature is the temperature at which the thermal stress τ is highest.
The residual oxygen concentration Co of oxygen left in the silicon wafer W and the precipitated oxygen concentration ΔOi after such a heat treatment is measured based on the infrared absorption spectroscopy in accordance with ASTM F121-1979 using a Fourier transform infrared spectrometer (FT-IR).
Alternatively, the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co after heat treatment can be obtained by simulation calculation without actually performing heat treatment on the silicon wafer W in the device fabrication process. Specifically, the above values can be obtained using a known numerical analysis technique (for example, see Sumio Kobayashi. Journal of Crystal Growth, 1997, Vol. 174, p. 163). Using such simulation calculation, as compared with the case of performing heat treatment on the silicon wafer W, the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co can be determined more simply and in a shorter time.
Note that when the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co after heat treatment performed in the device fabrication process are determined by simulation calculation, the silicon wafer W need not be actually prepared in Step S1. Namely, Step S1 can be omitted, and only the data of the initial oxygen concentration, the thermal history during the growth, and the dopant concentration of a single crystal silicon ingot grown under certain conditions are required.
Subsequently, in Step S3, the critical shear stress τcri at which slip dislocations are formed in the silicon wafer in the device fabrication process is determined based on the precipitated oxygen concentration ΔOi and the residual oxygen concentration Co determined in Step S2. As described above, in the previous application (JP 2011-238664 A, JP 5533210 B), the inventors found that the critical shear stress τcri at which slip dislocations are formed in a device fabrication process is closely related to the ratio of the residual oxygen concentration Co (concentration of oxygen left in a wafer having been subjected to heat treatment performed in the wafer production stage) with respect to the BMD size L, expressed as Co/L (that is, the product of the reciprocal of L, i.e., 1/L and Co).
As a result of further studies to determine τcri with higher accuracy, the inventors found that it is significantly effective to measure the precipitated oxygen concentration ΔOi in place of the BMD size L and formulate the critical shear stress τcri, at which slip dislocations are formed in the device fabrication process, as the sum of the reciprocal of the precipitated oxygen concentration ΔOi, i.e., 1/ΔOi and the residual oxygen concentration
Co in a silicon wafer after heat treatment performed in the device fabrication process. Experiments that made it possible to obtain the above finding will now be described.
First, a number of samples of silicon wafers shown in
Specifically, each sample wafer was cut out in a 10 mm×40 mm piece and the obtained sample piece 1 was placed on support rods 2 with their support points at intervals of 30 mm as shown in
Accordingly, τcri can be determined from the formula (1) below.
τcri=τmax×(L/L−X) (1),
where τmax is the shear stress applied to the sample piece 1 in the test, L is the distance between the support points, and X is the width of the band of the dislocation pits. In this test, the applied load is read using a load cell and the read value was converted to the shear stress. Slip dislocations in silicon are formed on the (111) plane in the <110> direction. Considering this, the maximum shear stress τmax was determined by the following formula.
τmax(3×P×L)/(2×b×d2)×0.40825 (2),
where P is the maximum load read by the load cell, b is the width of the sample piece 1, and d is the thickness of the sample piece 1. Using the method, the maximum shear stress τmax was calculated, and the distance between the support points and the width of the dislocation pits were measured, thereby calculating the critical shear stress τcri.
From the relationship between the precipitated oxygen concentration ΔOi and the critical shear stress τcri shown in
τΔO=A(l/ΔOi) (3),
where A is a constant and ΔOi is the precipitated oxygen concentration.
Meanwhile, the effect of change in the residual oxygen concentration Co on the critical shear stress τcri can be regarded as the behavior of the stress (locking force) by which oxygen in the BMDs locks (closely holds) punched-out dislocations serving as Frank-Read sources. The locking force can be expressed by the formula (4) below.
τSL=B×Co×exp(0.91 eV/kT) (4),
where B is a constant, k is the Boltzmann constant, and T is the temperature.
The combination of those two formulae is considered to make it possible to express the critical shear stress τcri. For example, τcri can be expressed as the product of τΔOi and τSL. However, in that case, the critical shear stress τcri is 0 if the residual oxygen concentration Co is 0, and this is physically unnatural because slip dislocations are formed without a load of stress. Accordingly, the inventors conceived of formulating τcri as the sum of τΔOi and τSL. Specifically, the critical shear stress τcri is formulated as the formula (5) below.
τcri=τΔO
In the above formula (5), the critical shear stress τcri at which slip dislocations are formed in the device fabrication process is expressed as the sum of the stress component τΔOi required for the formation of slip dislocations from punched-out dislocations caused by BMDs and the stress component τSL for releasing the formed punched-out dislocations from the locking by oxygen in the BMDs. Further, as shown in Examples below, the critical shear stress τcri at which slip dislocations are formed in the device fabrication process can be estimated with exceedingly high accuracy by the above formula (5).
This formula (5) will be described in more detail with reference to
As a result of determining the constants A and B in the above formula (5) by the regression analysis, the critical shear stress τcri at which slip dislocations are formed in the device heat treatment process is expressed as in the formula (6) below.
τcri=24.6×(1/ΔOi)+7.0×10−5×Co×exp(0.91 eV/kT) (6)
Subsequently, the obtained critical shear stress τcri and the thermal stress τ applied to the silicon wafer W in the device fabrication process are compared. The thermal stress τ. applied to the silicon wafer in the device fabrication process can be determined as follows. Specifically, first, the silicon wafer is loaded into a heat treatment unit such as an RTA apparatus to heat the silicon wafer to apply thermal stress thereto. Under the heating conditions in normal RTA, the heating distribution is adjusted so that the temperature does not vary in the wafer plane; however, here, thermal stress is designed to be generated with an uneven heating profile. Next, the temperature distribution T(r′) in the radial direction of the silicon wafer is measured using a thermocouple. The stresses in the radial direction and the circumferential direction are given by the following respective formulae (7) and (8).
where r is the position in the radial direction of the silicon wafer, and R is the radius of the silicon wafer, a is the coefficient of thermal expansion, and E is the Young's modulus.
In a single crystal body like a silicon wafer, the planes and the direction in which slip dislocations are formed are limited, so that an analysis considering the slip planes is required. Slip dislocations in silicon are formed on the {111} planes in the <110> direction. Excluding the equivalents, there are three slip slopes in the <110> direction each for four {111} planes. Accordingly, 12 types of shear stresses are required to be determined.
The stress estimated using the above cylindrical coordinate system is converted to the Cartesian coordinate system, thereby determining the shear stresses on the respective slip planes in the respective slip directions as in the formula (9) below. Note that a slip plane is denoted by (ijk) and the slip direction is denoted by [1 mm].
In this disclosure, of the 12 types of shear stresses obtained as described above, the highest shear stress was adopted as the thermal stress τ applied to the silicon wafer in heat treatment of the device fabrication process.
The thermal stress τ applied to the silicon wafer in heat treatment of the device fabrication process can be determined by simulation calculation instead of being determined using a heat treatment unit as described above. Thus, the thermal stress τ can be estimated simply in a short time. Specifically, the radiant heat applied to the wafer from a heater and the heat conduction are analyzed by the finite element method, and the temperature distribution in the wafer plane in the heat treatment process is obtained. From the obtained temperature distribution, the thermal stress τ can be determined using the formulae (7), (8), and (9).
After that, in Step S4, whether or not slip dislocations are formed in the silicon wafer W in the device fabrication process is determined. In this disclosure, when the thus obtained thermal stress τ applied to the silicon wafer W in the device fabrication process is equal to or higher than the critical shear stress τcri determined by the formula (6), slip dislocations are formed in the silicon wafer in the device fabrication process, and silicon wafers determined to have slip dislocations formed therein are determined to be defective products. In other words, when the thermal stress τ is lower than the critical shear stress τcri, slip dislocations are determined not to be formed even after heat treatment of the device fabrication process is performed, and silicon wafers determined to have no slip dislocations formed therein are determined to be good products.
In such a way, whether or not slip dislocations are formed after performing heat treatment of the device fabrication process is determined with high accuracy, so that the quality (pass/fail) of a silicon wafer can be determined.
In the above embodiment of the quality evaluation method for a silicon wafer, the critical shear stress τcri is expressed by the sum of the effect τΔOi of the precipitated oxygen concentration ΔOi on the critical shear stress τcri expressed by the above formula (3) and the effect τSL of change in the residual oxygen concentration Co on the critical shear stress τcri expressed by the formula (4) (formula (5)).
The inventors diligently studied to determine the critical shear stress τcri with higher accuracy and subsequently found room for improvement in the calculation of the effect τSL of change in the residual oxygen concentration Co on the critical shear stress τcri. Further, they found that the effect of change in the residual oxygen concentration Co on the critical shear stress τcri can be calculated with higher accuracy using τSL′ expressed by the formula (10) below instead of using the above formula (4).
τSL′=B×ε0.22×Co×exp(0.91 eV/kT) (10),
where B is a constant, ε is the distortion velocity, k is the Boltzmann constant, and T is the temperature.
Expressing the critical shear stress τcri as the sum of the effect τΔOi of the precipitated oxygen concentration ΔOi on the critical shear stress τcri expressed by the above formula (3) and the effect ξSL of change in the residual oxygen concentration Co on the critical shear stress τcri expressed by the above formula (10) allows the critical shear stress τcri to be determined with higher accuracy.
τcri=τΔO
A method of producing a silicon wafer will now be described. in the disclosed method of producing a silicon wafer, a single crystal silicon ingot is grown under the growing conditions allowing a silicon wafer to be obtained, which wafer is determined to have no slip dislocations formed in a device fabrication process by the above quality evaluation method for a silicon wafer, and the grown single crystal silicon ingot is subjected to a wafer processing process.
The grown single crystal silicon ingot I is subjected to a known processing process including peripheral grinding, slicing, lapping, etching, and mirror polishing, thereby obtaining a silicon wafer W having a predetermined thickness.
The subsequent steps from Step S12 to Step S14 correspond to Steps S2 to S4 in
In this disclosure, in Step S14, when whether or not slip dislocations are formed in the silicon wafer W in the device fabrication process can be determined with high accuracy, and the thermal stress τ applied to the silicon wafer W in the device fabrication process is equal to or higher than the critical shear stress τcri determined by the formula (6), slip dislocations are determined to be formed in the silicon wafer in the device fabrication process. In other words, when the thermal stress τ is lower than the critical shear stress τcri, slip dislocations are determined not to be formed even after heat treatment of the device fabrication process is performed.
Further, a single crystal silicon ingot is grown under the growing conditions allowing a silicon wafer to be obtained, which wafer is determined to have no slip dislocations formed in a device fabrication process in Step S14, and the grown single crystal silicon ingot is subjected to a wafer processing process, thereby obtaining a silicon wafer in which slip dislocations are not formed in the device fabrication process.
When the thermal stress τ is equal to or higher than the critical shear stress τcri in Step S14, the growth conditions for the single crystal silicon ingot are changed, and the steps from Step S11 in which a single crystal silicon ingot is grown to Step S14 in which whether or not slip dislocations are formed in the device fabrication process is determined are repeated until the thermal stress τ becomes lower than the critical shear stress τcri in Step S15.
The growth conditions for the single crystal silicon ingot I are changed specifically so that the critical shear stress τcri will increase, the precipitated oxygen concentration ΔOi will decrease, and/or the residual oxygen concentration Co will decrease. When the single crystal silicon ingot I is grown, for example, by the CZ process, the above change can be performed, for example, by changing the oxygen concentration, the nitrogen concentration, or the carbon concentration or by changing the rotational speed of a crucible, the pulling rate, or the like.
Note that when the precipitated oxygen concentration Δoi and the residual oxygen concentration Co after heat treatment performed in the device fabrication process are determined by simulation calculation, the process of Steps S12 to S14 is performed without growing the single crystal silicon ingot I in Step S11; a single crystal silicon ingot is grown under the growth conditions under which a silicon wafer determined to have no slip dislocations formed can be obtained in the end; and the grown single crystal silicon ingot is subjected to a wafer processing process. Thus, a silicon wafer in which slip dislocations are not formed in the device fabrication process can be obtained.
The precipitated oxygen concentration ΔOi after the heat treatment in the device fabrication process is preferably controlled to 0.06×1017 atoms/cm3 or more and 0.8×1017 atoms/cm3 or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature. Further, the residual oxygen concentration Co after the heat treatment in the device fabrication process is preferably controlled to 10×1017 atoms/cm3 or more and 18×1017 atoms/cm3 or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature.
Thus, a silicon wafer in which slip dislocations are not formed after heat treatment in the device fabrication process can be produced.
Next, a silicon wafer of this disclosure will be described. The disclosed silicon wafer is a silicon wafer having a precipitated oxygen concentration ΔOi and a residual oxygen concentration Co at which the thermal stress τ applied in a device fabrication process is lower than the critical shear stress τcri at which slip dislocations are formed in the device fabrication process, in which wafer, no slip dislocations are formed even after a heat treatment of the device fabrication process is performed.
For a silicon wafer according to this disclosure, the precipitated oxygen concentration ΔOi after heat treatment in the device fabrication process is preferably 0.06×1017 atoms/cm3 or more and 0.8×1.017 atoms/cm3 or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature. Further, the residual oxygen concentration Co after heat treatment of the device fabrication process is preferably 10×1017 atoms/cm3 or more and 18×1017 atoms/cm3 or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature.
Examples of this Disclosure will now be Described.
At a set temperature, a high-temperature four-point bending test capable of applying a given stress was performed. The high-temperature four-point bending test is a test method in which the point of action in the above-described high-temperature three-point bending test is doubled, and a stress is applied with the distance between the two points of action being 15 mm. A characteristic of the high-temperature four-point bending test is that a constant stress can be applied to a sample piece as shown in the stress profile diagram of
Then, it was determined whether or not slip dislocations had been formed from BMDs after each sample wafer was loaded with a stress by subjecting each sample wafer to selective etching and then confirming the presence or absence of dislocation pits using an optical microscope. Whether or not slip dislocations were formed is shown in
As can be seen from the formula (6), in each sample wafer under the above broken line, the critical shear stress τcri is lower than the thermal stress τ applied to the silicon wafer in the device fabrication process. In this disclosure, such a wafer is determined as a silicon wafer in which slip dislocations are formed. As is apparent from
Sample wafers were subjected to heat treatment designed to emulate a standard device fabrication process, and whether or not slip dislocations were formed from BMDs was determined. Here, the heat treatment in the emulated device fabrication process was constituted by two processes A and B. Here, the process A was constituted by four heat treatment steps, in which different baking temperatures and heat treatment times were used. Meanwhile, the process B was constituted by six heat treatment steps, in which different baking temperatures and heat treatment times were used as in the process A, and the last step was an RTA step.
In the process A, the loading temperature and the unloading temperature of a sample wafer were both 600° C. and the heating rate and the cooling rate were both 8° C./min in the first to third steps. The loading temperature and the unloading temperature of the sample wafer were 800° C., and the heating rate and the cooling rate were 15° C./min in the fourth step. In the process B, the loading temperature and the unloading temperature of the sample wafer were both 600° C., and the heating rate and the cooling rate were both 8° C./min in the first to fifth steps; and the loading temperature and the unloading temperature of the sample wafer were both 650° C., the heating rate was 150° C./s, and the cooling rate was 75° C./s in the sixth step. The heat treatment conditions in the processes A and B are shown in Tables 3 and 4, respectively. The initial oxygen concentration InOi, the residual oxygen concentration Co, and the precipitated oxygen concentration ΔOi of the sample wafers having been subjected to the processes A and B are shown in Tables 5 and 6, respectively.
For the thermal stress τ in the device fabrication process, the in-place temperature of each sample wafer loaded into a heat treatment furnace was measured with a thermocouple using the formulae (7) to (9). A stress of 5.5 MPa was applied at a baking temperature of 1100° C. in the fourth step in the process A. Meanwhile, a thermal stress of 16,1 MPa was found to be applied at a baking temperature of 1000° C. in the sixth step in the process B.
With respect to the sample wafers having been subjected to the processes A and B, Table 5 shows the results of determining whether or not the thermal stress τ applied to each silicon wafer in heat treatment of the device fabrication process was lower than τcri calculated using the formula (6) and Table 6 shows the results of whether or not slip dislocations were actually formed.
As described above, in this disclosure, when the thermal stress applied to a sample wafer in heat treatment of a device fabrication process is lower than the critical shear stress τcri, i.e., when τ<τcri is satisfied; slip dislocations are determined not to be formed in the silicon wafer on which heat treatment is performed in the device fabrication process. As is apparent from Tables 5 and 6, the evaluation results according to this disclosure are completely consistent with the results of whether or not slip dislocations were actually formed. This shows that whether or not slip dislocations originated from BMDs are formed can be determined using the formula (6) with high accuracy,
Further, a single crystal silicon ingot was grown at a lower oxygen concentration than the case of growing sample wafers 1 and 3 in which slip dislocations were formed in Tables 5 and 6. The critical shear stress τcri of a silicon wafer W having a lower initial oxygen concentration taken out of the grown ingot was determined based on the precipitated oxygen concentration ΔOi and the residual oxygen concentration after heat treatment in the device fabrication process. Consequently, the critical shear stress τcri was higher than that obtained under the unchanged growth conditions, i.e., where τ<τcri was satisfied. Thus, the silicon wafer W was obtained, in which no slip dislocations were formed even after heat treatment in the device fabrication process was performed thereon.
The critical shear stress at which slip dislocations are formed in a device fabrication process is determined with high accuracy, thereby determining with high accuracy whether or not slip dislocations are formed in a silicon wafer due to heat treatment of the device fabrication process. Accordingly, this technique is useful in the semiconductor industry.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-128970 | Jun 2015 | JP | national |
