Patent Application
20090230378
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2008-0022448, filed on Mar. 11, 2008, the entire contents of which are hereby incorporated by reference.
Embodiments of the present invention relate to resistive memory devices and methods of forming the same, and more particularly, to phase-change memory devices that can be integrated with a high integration density and methods of forming the same.
Phase-change memory devices are memory devices to store and read information using a difference in electrical conductivity (or resistivity) of phase-change material, for example, chalcogenide. These phase-change memory devices are highlighted as a next generation memory owing to their characteristics, such as random access and nonvolatility.
However, like other memory devices, since the phase-change memory devices require a higher level of integration density, a new phase-change memory device capable of satisfying such a requirement and a method of forming the same are needed.
Embodiments of the present invention provide resistive memory devices with a high integration density and method of forming the same.
Embodiments of the present invention also provide phase-change memory devices with a high integration density and method of forming the same.
In some embodiments of the present invention, resistive memory devices include a resistive memory element formed on a substrate. A first insulating layer covers a side surface of the resistive memory element. A conductive line is provided on the resistive memory element. A second insulating layer covers a side surface of the conductive line. The first insulating layer and the second insulating layer have a difference in at least one selected from the group consisting of hardness, stress, dielectric constant, heat conductivity and porosity degree.
In other embodiments of the present invention, methods of forming a resistive memory device comprise forming a first insulating layer having a first opening on a substrate. A resistive memory element is formed in the first opening. A second insulating layer having an opening exposing the resistive memory element is formed on the resistive memory element and the first insulating layer. A conductive line connected with the resistive memory element is formed by filling the opening with a conducive material. The first insulating layer and the second insulating layer are formed such that the first insulating layer and the second insulating layer have at least one difference in characters, characters such as hardness, stress, dielectric constant, heat conductivity and porosity degree.
In still other embodiments of the present invention, methods of forming a resistive memory device comprise forming a resistive memory element on a substrate. A first insulating layer covering a sidewall of the resistive memory element is formed on the substrate. A second insulating layer having an opening exposing the resistive memory element is formed on the resistive memory element and the first insulating layer. A conductive line connected with the resistive memory element is formed by filling the opening with a conductive material. The first insulating layer and the second insulating layer are formed such that the first insulating layer and the second insulating layer have at least one difference in characters, characters such as hardness, stress, dielectric constant, heat conductivity and porosity degree.
The accompanying figures are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the figures:
Embodiments of the present invention relate to resistive memory devices and methods of forming the same. A resistive memory device is a type of memory device using a resistive memory element that can represent at least two resistive states discernible according to a signal applied, e.g., high resistive state and low resistive state. The resistive memory element may include, for example, a perovskite memory element, a phase-change memory element, a magneto-resistive memory element, a conductive metal oxide (CMO) memory element, a solid electrolyte memory element, a polymer memory element and the like.
The perovskite memory element may include, for example, a colossal magnetoresistive (CMR) material, a high temperature superconducting (HTSC) material, or the like. The solid electrolyte memory element has metal ions movable in a solid electrolyte, and thus the solid electrolyte memory element may include a material that can form a conductive bridging.
Example embodiments of the present invention will now be described using a resistive memory device employing a phase-change memory element. Accordingly, it will be understood that descriptions to be mentioned below may be applied to resistive memory devices employing various types of memory elements described above.
An embodiment of the present invention provides a phase-change memory device and a method of forming the same. The phase-change memory device according to an embodiment of the present invention includes a phase-change memory element. The phase-change memory element may include a phase-change material. For example, it will be understood that the phase-change memory element may indicate a phase-change material layer and two electrodes connected with both surfaces of the phase-change material layer. Also, it will be understood that the phase-change memory element indicates a phase-change material. The phase-change material may be a material of which crystalline state may be reversely changed between a plurality of crystalline states showing different resistive states depending on heat. Electrical signals, such as current, voltage, optical signals, radiation or the like may be used to change the crystalline state of the phase-change material. For example, when a current flows between electrodes connected with both ends of a phase-change material, heat is provided to the phase-change material by a resistive heating. At this time, the crystalline state of the phase-change material may be changed depending on intensity of heat provided and time provided. For example, the phase-change material may have an amorphous state (or reset state) with a high resistance and a crystalline state (or set state) with a low resistance.
The phase-change material may include, for example, chalcogenide. When a phase-change material according to embodiments of the present invention is expressed by ‘XY’, ‘X’ may include at least one selected from the group consisting of telulium (Te), Selenium (Se), Sulphur (S), and polonium (Po), and ‘Y’ may include at least one selected from the group consisting of Antimony (Sb), Arsenic (As), Germanium (Ge), Tin (Sn), Phosphorous (P), Oxygen (O), Indium (In), Bismuth (Bi), Silver (Ag), Gold (Au), Palladium (Pd), Titanium (Ti), Boron (B), Nitrogen (N) and Silicon (Si). Examples of the phase-change material according to an embodiment of the present invention may include chalcogenides such as Ge—Sb—Te (GST), Ge—Bi—Te (GBT), As—Sb—Te, As—Ge—Sb—Te, Sn—Sb—Te, In—Sn—Sb—Te, Ag—In—Sb—Te, an element in Group 5A of the periodic table-Sb—Te, an element in Group 6A of the periodic table-Sb—Te, an element in Group 5A of the periodic table-Sb—Se, an element in Group 6A of the periodic table-Sb—Se, and chalcogenides in which impurities are doped in the aforementioned chalcogenides. The impurities doped in the chalcogenides may include, for example, nitrogen, oxygen, silicon, or combinations thereof.
Embodiments of the present invention provide methods of forming an insulating layer for insulation between phase-change memory elements, and an insulating layer for insulation between conductive structures, for example, conductive lines. Also, an embodiment of the present invention provides a method of forming a variety of conductive lines such as a bit line and a word line in a cell array region, and a local conductive line in a peripheral circuit region, as well as an interconnecting method between conductive structures in a phase-change memory device.
As the degree of integration increases, a distance between elements in a horizontal direction, a distance between a variety of conductive lines such as a bit line and a local conductive line, and a line width of such conductive lines decreases, but a height of insulating layers and conductive layers stacked on a substrate in a vertical direction increases. For example, in the case of a phase-change memory element, its height and width decrease. The distance between adjacent phase-change memory elements decreases too.
When a phase-change memory element is formed under this circumstance, the inventors of the present invention have found that the phase-change memory element is distorted due to a thermal process, etc. Also, the inventors have found that if the phase-change memory element, in particular, the phase-change material is distorted, an interfacial characteristic between the phase-change material and electrodes is deteriorated and thus a set resistance increases.
According to embodiments of the present invention, in order to prevent a phase-change memory element and a phase-change material layer from being distorted, a phase-change material layer and an insulating layer enclosing a phase-change material layer have the same stress property. For example, an insulating layer enclosing a phase-change memory element shows ‘tensile stress’. The insulating layer enclosing the phase-change memory element may be formed of a material having a stress property that can compensate for a stress that a phase-change memory element has in a memory operation. The insulating layer enclosing the phase-change memory element may have, for example, a tensile stress of about 5×109 dyne/cm2.
According to other embodiments of the present invention, an insulating layer enclosing a phase-change memory element may be formed of a material with a high hardness to minimize the movement of the phase-change memory element.
Also, according to still other embodiments of the present invention, an insulating layer enclosing a phase-change memory element may be formed of a material with low heat conductivity. Thus, it is possible to reduce a thermal interference between adjacent phase-change memory elements.
The height increase in the vertical direction may cause an increase in the aspect ratio in various openings, such as a contact hole, a via-hole, etc., for an electrical connection between lower and upper conductive structures and conductive lines, between conductive structures, or between conductive lines. As the distance between adjacent conductive lines decreases, it becomes difficult to form a conductive line using an etching, and the resistance of a conductive line increases due to a decrease in the line width. Also, as the aspect ratio of opening increases, it becomes difficult to fill an opening with a conductive material, and the resistance of a conductive material filled in an opening also increases.
Accordingly, in an embodiment of the present invention, at least one conductive line, for example, a bit line is formed of copper using a damascene technique. To decrease the parasitic capacitance between adjacent conductive lines, an insulating layer enclosing a conductive line may be formed of, for example, a low-k material with low dielectric constant. For example, an insulating layer covering side surfaces of a conductive line, such as a bit line may be formed of a material having a dielectric constant lower than the insulating layer formed on side surfaces of the phase-change memory element.
In other embodiments of the present invention, an insulating layer enclosing a conductive line may be formed of a porous material in order to obtain a low dielectric constant. For example, an insulating layer enclosing a conductive line may be formed of a material having a higher porosity degree than an insulating layer enclosing a phase-change memory element. In still other embodiments of the present invention, an insulating layer enclosing a conductive line may be formed of a material having a lower hardness than an insulating layer enclosing a phase-change memory element.
In even other embodiments of the present invention, an insulating layer enclosing a conductive line may be formed of a material having a lower tensile stress than an insulating layer enclosing a phase-change memory element.
According to another embodiment of the present invention, when a copper bit line is formed using a damascene technique, a part of a contact structure for an electrical connection between conductive regions, between a conductive region and a conductive line, or between conductive lines is formed of copper at a position adjacent to the copper bit line. For example, when a stripe type opening for a bit line is formed, a hole type opening for a part of a contact structure is formed, the stripe type opening for a bit line is filled with copper to form a copper bit line, and the opening for a part of a contact structure is filled with copper to form a copper stud.
The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, like reference numerals in the drawings denote like elements, and thus their description will be omitted.
Terms such as “lower surface” and “upper surface” used in relation to elements of the present specification are relative terms which indicate a “relatively close surface to” and a “relatively distant surface from” a main surface of a substrate, respectively. Also, it will be understood that in the present specification, the heights of elements' surfaces may be compared with respect to a main surface of a substrate. For example, it will be understood that when a lower surface of one element is referred to as being “lower” than a lower surface of another element, the description may indicate that the lower surface of the one element is positioned closer to a main surface of a substrate than the lower surface of the other element.
A term ‘conductive material’ used in the present specification includes, but is not limited to, metal, conductive metal nitride, conductive metal oxide, conductive oxide nitride, silicide, metal alloy or combinations thereof. Examples of the metal include copper (Cu), aluminum (Al), tungsten titanium (TiW), tantalum (Ta), Molybdenum (Mo), tungsten (W) and the like. Conductive metal nitride includes, but is not limited to, for example, titanium nitride (TiN), tantalum nitride (TaN), Molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN) and the like. Examples of the conductive oxide nitride include, but are not limited to, titanium oxide nitride (TiON), titanium aluminum oxide nitride (TiAlON), tungsten oxide nitride (WON), tantalum oxide nitride (TaON) and the like. Examples of the conductive metal oxide include, but are not limited to, conductive novel metal oxides, such as iridium oxide (IrO), ruthenium oxide (RuO) and the like.
In the present specification, ‘substrate’ or ‘semiconductor substrate’ or ‘semiconductor layer’ may indicate a semiconductor-based structure with a silicon surface. Also, ‘substrate’ or ‘semiconductor substrate’ or ‘semiconductor layer’ may indicate a conductive region, an insulating region, and/or a semiconductor-based structure on which a device is formed. Such a semiconductor based structure may indicate, for example, a silicon layer, a silicon on insulator (SOI) layer, a silicon-germanium (SiGe) layer, a germanium (Ge) layer, a gallium-arsenide (GaAs) layer, a doped or undoped silicon layer, a silicon epitaxial layer supported by a semiconductor structure, or any semiconductor structures.
It will be understood that when an element or layer is referred to as being “on”, or “formed on” another element or layer, it may be directly on or formed on the other element or layer, or intervening elements or layers may be present or formed. Also, it will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such as studs, conductive lines, contact plugs, insulating layers, conductive materials, contact holes, via holes, opening and the like throughout the present specification, these elements should not be limited by these terms. These terms may be only used to distinguish one element from another region.
Bit lines BL of a stripe pattern extending in a column direction are arranged to cross the word lines WL. Memory cells may be positioned at crossing portions of the bit lines BL and the word lines WL. In an embodiment of the present invention, a memory cell may include, for example, a resistive memory element Mp, such as a phase-change memory element. One end of the resistive memory element Mp is connected with the bit line BL and the other end is connected with the word line WL. A selection element for selecting the resistive memory element Mp may be positioned between the word line WL and the other end of the resistive memory element Mp. According to an embodiment of the present invention, the resistive memory element Mp may include a phase-change material.
To decrease the resistance of the word line WL, the word line WL may be electrically connected with a conductive line having a low resistance through the word line contact structure WLC. For example, a conductive line with a low resistance used for decreasing the resistance of the word line WL may be referred to as the upper word line UWL in consideration that the conductive line is more distant from the substrate 100 than the word line WL. The word line WL may be referred to as a lower word line in consideration of this upper word line. Also, it will be understood that the word line WL may indicate the upper word line UWL as well as the lower word line LWL. The word line contact structure WLC may be positioned between the resistive memory elements Mp adjacent to each other in the first direction. The word line contact structure WLC may be formed per a predetermined number of memory cell(s), for example, per eight adjacent memory cells. That is, eight memory cells may be arranged between the contact structures WLC adjacent to each other in the first direction. Also, the contact structure WLC may be formed per an unspecified number of memory cells. That is, various numbers of memory cells, for example, sixteen, thirty two memory cells may be arranged between the contact structures WLC adjacent to each other in the first direction.
With reference to
Referring to
The second insulating layer 160 encloses the bit line 180. For example, the second insulating layer 160 is provided on a side surface of the bit line 180. The bit line 180 may be defined within the opening 165 of the second insulating layer 160. For example, the bit line 180 may be formed by patterning the second insulating layer 160 to form the opening 165 and then filling a conductive material such as copper in the opening 165. That is, the bit line 180 may be formed by using a damascene technique. The conductive barrier layer 170 may be provided between the copper bit line 180 and the second electrode 140. This conductive barrier layer 170 may be provided on a bottom and sidewalls of the opening 165.
According to the present embodiment, the first insulating layer 150 and the second insulating layer 160 are formed of materials having different properties. The first insulating layer 150 and the second insulating layer 160 show differences in hardness, porosity degree, dielectric constant, stress, and/or heat conductivity. For example, the first insulating layer 150 may be formed of a material with a high hardness, low porosity degree, tensile stress, and/or low heat conductivity. The second insulating layer 160 may be formed of a material with a low hardness, low dielectric constant, and/or a high porosity degree. For example, the first insulating layer 150 may be formed of a material having a relatively higher hardness, higher dielectric constant, lower porosity degree, higher tensile stress, and/or lower heat conductivity than the second insulating layer 160.
For example, the first insulating layer 150 may show a tensile stress of about 5×109 dyne/cm2. The second insulating layer 160 may show a lower tensile stress or may not show a tensile stress.
Although not shown in the drawing, a capping layer may be further provided. For example, this capping layer may be formed of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxide nitride (SiON), aluminum oxide (AlOx), titanium oxide (TiO2), or the like. This capping layer may be, for example, provided on the second electrode 140.
Referring to
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A method of forming a phase-change memory device according to the embodiments of the present invention will now be described with reference to the accompanying drawings.
After the word line, the selection element and the like are formed, the interlayer insulating layer 110 is formed on the substrate 100. The interlayer insulating layer 110 is patterned to form the electrode contact hole 115 defining a first electrode and exposing a corresponding selection element. A conductive material is filled in the electrode contact hole 115 to form the first electrode 120.
The phase-change material layer 130 correspondingly connected with the first electrode, and the second electrode 140 is formed. According to the present embodiment, the phase-change material layer 130 and the second electrode 140 may be formed by forming a phase-change material layer such as a chalcogenide, and a conductive material for the second electrode on the first electrode 120 and the interlayer insulating layer 110, and then patterning the phase-change material layer and the conductive material for the second electrode. Here, a capping layer may be further formed on the conductive material for the second electrode. Accordingly, a capping layer will be provided on the second electrode 140. This capping layer may be formed after the phase-change material layer and the conductive layer for the second electrode are patterned. In this case, the capping layer will be provided on side surfaces of the phase-change material layer 130 and the second electrode 140 as well as on an upper surface of the second electrode 140. This capping layer may be formed on the conductive material for the second electrode in embodiments to be described later.
Referring to
To prevent the phase-change material layer 130 from being distorted, the first insulating layer 150 is formed to have the same stress property as that of the phase-change material layer 130. For example, in the case where the phase-change material layer 130 has a tensile stress, the first insulating layer 150 is formed to have a tensile stress. For example, the first insulating layer 150 may have a tensile stress of about 5×109 dyne/cm2. The first insulating layer 150 is formed of a material with a high hardness such that the first insulating layer 150 may rigidly support the phase-change material layer 130. Alternatively, the first insulating layer is formed of a material having a tensile stress and a high hardness.
The first insulating layer may be formed of an oxide layer formed by a vapor deposition method using a high density plasma, a silicon oxide nitride (SiON) formed by a vapor deposition method, an oxide layer formed by a vapor deposition method using a reinforced plasma, and/or a silicon nitride layer formed by a vapor deposition method at a high temperature.
The first insulating layer 150 may be also formed of a material with a low heat conductivity in order to minimize a thermal interference between the first insulating layer 150 and the phase-change material layer 130 adjacent thereto.
Next, a process of forming a bit line using a damascene technique will be described with reference to
For example, the second insulating layer 160 may be formed of a material having a higher porosity degree, a lower hardness, a lower tensile stress, a higher heat conductivity and/or a lower dielectric constant than the first insulating layer 150. Alternatively, the second insulating layer 160 may be formed of a material not having a tensile stress.
For a low dielectric constant, the second insulating layer 160 may be formed of, for example, boron-doped silicon oxide (BSG), phosphorous-doped oxide (PSG), boron and phosphorous-doped oxide (BPSG), carbon-doped silicon oxide, hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), SiLK, polyimide, polynorbornene, polymer dielectric material or the like. Also, the second insulating layer 160 may be formed of an oxide layer using an atomic layer deposition method, PETEOS oxide, flowable oxide (FOX) or the like.
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In the embodiment described with reference to
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In the present embodiment, the contact hole 155 of the first insulating layer 150 may be formed in a different pattern, for example, in a stripe pattern extending in the column direction. Thus, at least two adjacent phase-change memory cells share the phase-change material with each other.
According to the present embodiment, a part of the phase-change material adjacent to the first electrode 120, the phase-change material formed on a bottom of the contact hole 155 is not subject to an etch process. According to an embodiment of the present invention, since a phase-change of the phase-change material layer 130 takes place at a portion adjacent to the first electrode 120, it is possible to form a more reliable phase-change material layer.
With reference to
Referring to
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In the present embodiment, an etch for the phase-change material layer in which a phase-change takes place is not basically generated.
In the present embodiment, the contact hole 155 of the first insulating layer 150 may be formed in a different pattern, for example, in a stripe pattern extending in the column direction. Thus, at least two adjacent phase-change memory cells share the phase-change material with each other.
Referring to
Referring to
Referring to
In the present embodiment, an etch for the phase-change material layer in which a phase-change takes place is not basically generated.
In the present embodiment, the contact hole 155 of the first insulating layer 150 may be formed in a different pattern, for example, in a stripe pattern extending in the column direction. Thus, at least two adjacent phase-change memory cells share the phase-change material with each other.
With reference to
Referring to
Referring to
In the present embodiment, an etch for the phase-change material layer in which a phase-change takes place is not basically generated.
In the present embodiment, the contact hole 155 of the first insulating layer 150 may be formed in a different pattern, for example, in a stripe pattern extending in the column direction. Thus, at least two adjacent phase-change memory cells share the phase-change material with each other.
Referring to
A plurality of the bit lines BL is provided on the substrate 200 of the memory cell array region to cross the lower word lines LWL. In the peripheral circuit region, the first conductive line M1 corresponding to the bit line BL is provided. The first conductive line M1 may be electrically connected with the gate G, the source/drain region S/D of the driver transistor 230. The bit line BL and the first conductive line may include copper. According to an embodiment of the present invention, since the bit line BL and the first conductive line M1 may be formed of copper using a damascene technique, it is possible to decrease the resistances of the bit line BL and the first conductive line M1.
The phase-change material layer 300 is positioned between the lower word line LWL and the bit line BL. The first electrode 280 and the selection element 250 are provided between the phase-change material layer 300 and the lower word line LWL, and the second electrode 310 is provided between the phase-change material layer 300 and the bit line BL. In other words, the first electrode 280 and the second electrode 310 are electrically connected with the phase-change material layer 300. The first electrode 280 may be used, for example, as a heater for heating the phase-change material layer 300. The first electrode 280 is electrically connected with the lower word line LWL, for example, through the selection element 250 such as a diode. The second electrode 310 is electrically connected with the bit line BL.
The diode 250 functioning as a selection element may include an n-type semiconductor layer and a p-type semiconductor layer stacked on the substrate 200. The p-type semiconductor layer may be adjacent to the first electrode 280 and the n-type semiconductor layer may be adjacent to the lower word line LWL.
In the cell array region, the cell contact plug 290c, which is adjacent to the bit line BL and is electrically connected with the lower word line LWL, may be provided. The cell contact plug 290c may be made in a multi-layer structure. For example, the cell contact plug 290c may include a titanium nitride layer, a tungsten layer and a copper layer sequentially stacked in a sequence close to the substrate 200. The cell contact plug 290c may be provided, for example, in a cell contact hole penetrating the third insulating layer 380, the second insulating layer 360, the first insulating layer 320, the second interlayer insulating layer 260 and the first interlayer insulating layer 240.
Meanwhile, in the peripheral circuit region, the peripheral contact plugs 290p1-290p3 corresponding to the cell contact plug 209c may be provided. The peripheral contact structures 290p1-290p3 are electrically connected with the gate G, the source/drain region S/D of the driver transistor 230, or the impurity diffusion region 225. Similarly with the cell contact plug, the peripheral contact plug 290p1 connected with the source/drain region S/D may include a titanium nitride layer, a tungsten layer and a copper layer sequentially stacked in a sequence close to the substrate 200. The peripheral contact plugs 290p2 and 290p3 connected with the gate G may include, for example, a titanium nitride layer and a tungsten layer stacked in a sequence close to the substrate 200.
Similarly with the cell contact plug 290c1, the peripheral contact plug 290p1 may be provided in a peripheral contact hole penetrating the third interlayer insulating layer 380, the second insulating layer 360, the first insulating layer 320, the second interlayer insulating layer 260, and the first interlayer insulating layer 240. The peripheral contact plugs 290p2 and 290p3 may be provided in a peripheral contact hole penetrating the first insulating layer 320, the second interlayer insulating layer 260 and the first interlayer insulating layer 240.
According to embodiments of the present invention, the etch stop layer 330 may be provided between the second insulating layer 360 and the first insulating layer 320. This etch stop layer 330 is formed of a material having an etch selectivity with respect to the second insulating layer 360.
The upper word line UWL for decreasing the resistance of the lower word line LWL may be, for example, connected with the cell contact plug 290c2. In the meanwhile, in the peripheral circuit region, the second conductive line M2 corresponding to the upper word line UWL may be provided. The second conductive line M2 may be, for example, connected with the peripheral contact plug 290p1. Alternatively, the second conductive line M2 may be connected with the first conductive line M1. According to an embodiment of the present invention, since the upper word line UWL and the second conductive line M2 may be formed of copper using a damascene technique, the resistances of the upper word line UWL and the second conductive line M2 can be decreased.
In the cell array region, the global bit line GBL is provided on the upper word line UWL, and in the peripheral circuit region, the third conductive line M3 corresponding to the global bit line GBL is provided on the second conductive line M2. The global bit line GBL and the third conductive line M3 may include copper. Since the global bit line GBL and the third conductive line M3 may be formed of copper using a damascene technique, the resistances of the global bit line GBL and the third conductive line M3 can be decreased. The third conductive line M3 may be electrically connected with the second conductive line M2. The fourth interlayer insulating layer 400 may be provided between the global bit line GBL and the upper word line UWL.
The passivation layer 420 may be provided on the global bit line GBL and the third conductive line M3.
The first insulating layer 320 encloses side surfaces of the phase-change material layer 300, and the second insulating layer 360 encloses side surfaces of the bit line BL and the first conductive line M1.
The interlayer insulating layer 380 is provided between the bit line BL and the upper word line UWL and between the first conductive line M1 and the second conductive line M2. The interlayer insulating layer 400 is provided between the upper word line UWL and the global bit line GBL, and between the second conductive line M2 and the third conductive line M3.
According to another embodiment of the present invention, in order to obtain a higher integration density, the phase-change memory device may be formed in a multi-level on a substrate.
The aforementioned resistive memory device may be embodied in various forms or may be used as one element for various apparatuses. For example, the aforementioned resistive memory device may be applied for realizing various types of memory cards, USB memories, solid-state drivers, etc.
EDC 610 may encoder data to be stored in the memory 510. For example, EDC 610 may encode an audio data into an MP3 file and store the encoded MP3 file in the memory 510. Alternatively, EDC 610 may encode an MPEG video data (e.g., MPEG3, MPEG4, etc.) and store the encoded video data in the memory 510. Also, EDC 610 may include a plurality of encoders that encode a different type of data according to a different data format. For example, EDC 610 may include an MP3 encoder for audio data and an MPEG encoder for video data. EDC 610 may decode output data from the memory 510. For example, EDC 610 may decode audio data outputted from the memory 510 into an MP3 file. Alternatively, EDC 610 may decode video data outputted from the memory 510 into an MPEG file. Also, EDC 610 may include a plurality of decoders that decode a different type of data according to a different data format. For example, EDC 610 may include an MP3 decoder for audio data and an MPEG decoder for video data. Also, EDC 610 may include only a decoder. For example, previously encoded data may be delivered to EDC 610, decoded and then delivered to the memory controller 520 and/or the memory 510.
EDC 610 receives data for encoding or previously encoded data via the interface 630. The interface 630 may comply with a well-known standard (e.g., USB, firewire, etc.). The interface 630 may include one or more interfaces. For example, the interface 630 may include a firewire interface, a USB interface, etc. The data provided from the memory 510 may be outputted via the interface 630.
The representation component 620 represents data decoded by the memory 510 and/or EDC 610 such that a user can perceive the decoded data. For example, the representation component 620 may include a display screen displaying a video data, etc., and a speaker jack for outputting an audio data.
The controller 910 may include at least one microprocessor, digital processor, microcontroller, or processor. The memory 930 may store a command executed by data and/or the controller 910. The interface 940 may be used to transmit data from a different system, for example, a communication network, or to a communication network. The apparatus 9000 may be a mobile system such as a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card or a different system that can transmit and/or receive information.
According to embodiments of the present invention, it is possible to form a reliable phase-change memory device with a high integration density.
According to embodiments of the present invention, an interface characteristic between a phase-change material and an electrode can be enhanced to decrease the set resistance.
According to embodiments of the present invention, it is possible to form a resistive memory device and a phase-change memory device that can operate at a high speed.
According to embodiments of the present invention, heat transfer between adjacent memory cells can be minimized.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2008-0022448 | Mar 2008 | KR | national |
