Patent Application
20090140232
Memory devices are used in essentially all computing applications and in many electronic devices. For some applications, non-volatile memory, which retains its stored data even when power is not present, may be used. For example, non-volatile memory is typically used in digital cameras, portable audio players, wireless communication devices, personal digital assistants, and peripheral devices, as well as for storing firmware in computers and other devices.
A wide variety of memory technologies have been developed. Non-volatile memory technologies include flash memory, magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), and conductive bridging random access memory (CBRAM). Due to the great demand for memory devices, researchers are continually improving memory technology, and developing new types of memory, including new types of non-volatile memory.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
The scale of electronic devices is constantly being reduced. For memory devices, conventional technologies, such as flash memory and DRAM, which store information based on the storage of electric charges, may reach their scaling limits in the foreseeable future. Additional characteristics of these technologies, such as the high switching voltages and limited number of read and write cycles of flash memory, or the limited duration of the storage of the charge state in DRAM, pose additional challenges. To address some of these issues, researchers are investigating memory technologies that do not use storage of an electrical charge to store information. One such technology is conductive bridging random access memory (CBRAM).
When a voltage is applied across the solid electrolyte block 106, a redox reaction is initiated that drives Ag+ ions out of the first electrode 102 into the solid electrolyte block 106 where they are reduced to Ag, thereby forming Ag rich clusters within the solid electrolyte block 106. The size and the number of Ag rich clusters within the solid electrolyte block 106 may be increased to such an extent that a conductive bridge 114 between the first electrode 102 and the second electrode 104 is formed.
As shown in
To determine the current memory state of the CBJ 100, a sensing current is routed through the CBJ 100. The sensing current encounters a high resistance if no conductive bridge 114 exists within the CBJ 100, and a low resistance when a conductive bridge 114 is present. A high resistance may, for example, represent “0”, while a low resistance represents “1”, or vice versa.
The solid electrolyte block 106 can include many materials, but the materials of greatest interest for use in CBRAM are the chalcogens, including oxygen (O), sulphur (S), and selenium (Se). Combining these with copper (Cu) or silver (Ag) yields binary electrolytes, such as Ag2Se or Cu2S. Alternatively, a transition metal, such as tungsten (W) can be reacted with oxygen to form a suitable base glass for an electrolyte. If, for example, the resulting tungsten oxide is sufficiently porous and in its trioxide form (WO3), silver or copper ions will be mobile within the material, and can form electrodeposits. Another approach is to combine chalcogens with other elements, such as germanium, to create a base glass into which Cu or Ag may be dissolved. An example of such an electrolyte is Ag dissolved in Ge30Se70 (e.g., Ag33Ge20Se47). This takes the form of a continuous glassy Ge2Se3 backbone and a dispersed Ag2Se phase, which is superionic and allows the electrolyte to exhibit superionic qualities. The nanostructure of this material, and of its sulphide counterpart, provide good characteristics for use in switching devices, such as CBRAM. The metal-rich phase is both an ion and an electron conductor, but the backbone material that separates each of these conducting regions is a good dielectric, so the overall resistance of the material prior to electrodeposition is high. Generally, a germanium selenide (GeSe) compound or germanium sulfide (GeS) compound is used in conventional CBRAM devices, but silicon selenide and silicon sulfide may also be used. Although the example embodiments of the invention below are generally described in terms of a GeSe or GeS device, it will be understood that the principles of the invention may be employed in CBRAM devices that use silicon selenide or sulfide, or other suitable chalcogenide glasses.
A solid electrolyte, such as those used in CBRAM, can be made to contain ions throughout its thickness. The ions nearest the electron-supplying cathode will move to its surface and be reduced first. Non-uniformities in the ion distribution and in the nano-topography of the electrode will promote localized deposition or nucleation. Even if multiple nuclei are formed, the one with the highest field and best ion supply will be favored for subsequent growth, extending out from the cathode as a single metallic nanowire. The electrodeposition of metal on the cathode physically extends the electrode into the electrolyte, which is possible in solid electrolytes, particularly if they are amorphous or partially amorphous, and are able to accommodate the growing electrodeposit in a void-rich, semi-flexible structure.
Because the electrodeposit is connected to the cathode, it can supply electrons for subsequent ion reduction. This permits the advancing electrodeposit to harvest ions from the electrolyte, plating them onto its surface to extend itself forward. Thus, in an electrolyte containing a sufficient percentage of metal ions, the growing electrodeposit is always adjacent to a significant source of ions, so the average distance each ion travels in order to be reduced is, at most, a few nm.
The resistivity of the electrodeposit is orders of magnitude lower than that of the surrounding electrolyte, so once the electrodeposit has grown from the cathode to the anode, forming a complete conductive bridge, the resistance of the structure drops considerably. The decreasing resistance of the structure due to the electrodeposition effect increases the current flowing through the device until the current limit of the source is reached. At this point, the voltage drop falls to the threshold for electrodeposition, and the process stops, yielding the final “on” resistance of the structure.
As noted above, the electrodeposition process is reversible by changing the polarity of the applied bias. If the electrodeposit is made positive with respect to the original oxidizable electrode, it becomes the new anode, and will dissolve via oxidation. During the dissolution of the conductive bridge, balance is maintained by electrodeposition of metal back into the place where the excess metal for the electrodeposition originated. The original growth process of the conductive bridge will have left a low ion density region in the electrolyte surrounding the electrode, and this “free volume” will favor redeposition without extended growth back into the electrolyte. Once the electrodeposit has been completely dissolved, the process will self-terminate, yielding the final “off” resistance of the structure. The asymmetry of the structure facilitates the cycling of the device between a high-resistance “off” state, and a low-resistance “on” state, permitting the device to operate as a switch or memory element.
To write to the memory cell, the word line 214 is used to select the cell 200, and a current on the bit line 208 is forced through the memory element 204, to form or remove a conductive bridge in the memory element 204, changing the resistance of the memory element 204. Similarly, when reading the cell 200, the word line 214 is used to select the cell 200, and the bit line 208 is used to apply a voltage across the memory element 204 to measure the resistance of the memory element 204.
The memory cell 200 may be referred to as a 1T1J cell, because it uses one transistor, and one memory junction (the memory element 204). Typically, a memory device will include an array of many such cells. It will be understood that other configurations for a 1T1J memory cell, or configurations other than a 1T1J configuration may be used with a CBRAM or memory element such as is shown in
In the alternative configuration shown in
Use of amorphous or partially amorphous solids such as GeSe and GeS glasses in CBRAM devices presents numerous challenges. First, the resistance of these materials is very high when the device is in its “off” state, approximately 1011 to 1012 ohms at room temperature. This high off resistance (Roff) can lead to problems of interference. A node in a CBRAM cell located between the CBJ and the transistor (which has an Roff of approximately 1010 ohms when switched off) is essentially floating when both the CBJ and transistor are off, and is extremely sensitive to interference from sources such as capacitive coupling. Additionally, even very low leakage currents, for example, in the select transistors, may cause the buildup of interference voltages. Many other sources, such as static charges that may build up on plastic packages, may also cause interference effects. These interference effects can lead to inadvertent programming (switching) of the CBJ.
Another challenge in the use of amorphous or partially amorphous materials such as germanium selenide and germanium sulfide in CBRAM devices is the poor temperature stability of such materials. In particular, these materials may start to change from an amorphous or partially amorphous phase to a crystal phase at temperatures as low as 250° C. to 280° C. In a crystal phase, the migration of ions in the material becomes more difficult, which can lead to failure of the memory device. The temperatures reached during the back-end-of-line (BEOL) CMOS process may be as high as 400° C. or 450° C. These temperatures are too high for the chalcogenide glasses that are used in conventional CBRAM devices, and may lead, for example, to the material changing to the crystal phase. Attempts to improve the temperature stability of CBRAM devices by doping with oxygen have resulted in devices in which the Ag ions have insufficient ability to diffuse through the matrix, leading to devices that may be unable to retain an on-state.
In accordance with an embodiment of the invention, a multi-layer matrix may be used in an integrated circuit CBRAM device to provide a reduced Roff, resulting in decreased susceptibility to interference in a dense memory array. Additionally, depending on the materials used in the layers, a multi-layer matrix CBRAM device in accordance with an embodiment of the invention may provide improved temperature stability, without substantially hindering Ag-ion diffusion.
As shown in
The upper layer 304 and lower layer 308 include GeSe (or GeS) or another suitable solid electrolyte material, such as a chalcogenide glass or other amorphous or partially amorphous material. The layers 304, 306 and 308 of the resistive memory element 300 are also doped with Ag (or another suitable metal). The resistive memory element 300 also includes an inert electrode 310, including tungsten (W) or another suitable conductive material, and a reactive electrode 312, including Ag, or another metal, depending on the metal with which the CBJ 300 is doped.
To permit the penetration of Ag ions through the middle layer 306, the middle layer 306 should have a thickness between approximately 3 and 20 nm, and preferably between approximately 10 and 20 nm. The middle layer 306 may have a thickness greater than about 20 nm, but a higher threshold voltage will generally be needed to permit penetration of Ag ions through a layer that is substantially thicker than about 20 nm. Additionally, although the example embodiment shown in
The carbide composition middle layer 306 serves to reduce the Roff for the resistive memory element 300, reducing the susceptibility of a memory cell constructed in accordance with an embodiment of the invention to interference, and improving the suitability of such a memory cell for use in a dense array. Additionally, carbide compositions such as those used in the middle layer 306 may have a high recrystallization temperature. For example, GeC has a recrystalizytion temperature higher than 700° C. This may permit the middle layer 306 to serve as a barrier layer for crystallization, preventing crystallization in the upper layer 304 and the lower layer 308, neither of which has sufficient thickness to permit crystallization when separated from the other by the middle layer 306. This increases the temperature stability of the resistive memory element 300.
Due to the chemical nature of carbon, the diffusion of Ag through the middle layer 306 will be hindered only slightly, if at all. For example, this may be because the four valence electrons of the carbon fit well to a Ge central atom. Additionally, carbon does not generally bond with Ag. As a result of these properties, there is little (if any) disturbance to the retention of the on-state due to the introduction of the middle layer 306. It will be understood that although these properties may be useful, the invention is not limited to a particular theory of operation, and other materials may be used in accordance with the principles of the invention.
The resistance, including Roff, of the middle layer 306 may be adjusted by varying the composition of the middle layer 306. For example, a middle layer 306 that includes GeSe (or GeS), as well as GeC, may form GeSe:C (or GeS:C) impurities, which may reduce the resistance. Generally, a higher carbon content will cause a greater number of such impurities or defects in the material, which may cause leakage currents, leading to a reduced Roff. It should be noted that materials other than carbon can be used to provide this reduced Roff effect due to impurities and/or defects in the material. For example, nitrogen (N) may be used, to form a multi-layer system having GeSe:N impurities in the middle layer, between layers of GeSe. The resistance of such a nitrogen-containing triple layer system is shown in
Because the layers are effectively connected in series electrically, reducing the resistivity of one of the layers will reduce the resistivity of the entire multi-layer system. Thus, by using carbon or nitrogen impurities to reduce the Roff of the middle layer, the Roff for the entire memory element is reduced.
Referring now to
As described, the method starts with wafers onto which select transistors, vias, an isolation layer, and bottom electrode (typically containing tungsten) have already been deposited. Thus, the method described with reference to
In step 502, a GeSe target, a GeC target, and an Ag target are installed in sputter equipment that is capable of using at least three sputter targets without disrupting the vacuum. Many commonly used sputter deposition devices, such as some of the models manufactured by Canon ANELVA Corporation, of Tokyo, Japan, have this capability.
In step 504, a first GeSe layer is deposited. This layer may be deposited by means of RF-magnetron sputtering, or other suitable sputtering techniques. In the case of RF-magnetron sputtering, typically Ar is used as a sputter gas, at a pressure of approximately 4.5×10−3 mbar and an HF-sputter power in the range of approximately 1 to 2 kW. In some embodiments, this layer is deposited into pre-manufactured vias or on a W-plug of the memory element, and may have a thickness of approximately 20 nm, though a different thickness may be used (though if the thickness is great enough to permit crystallization, some of the temperature stability benefits may be lost).
In step 506, the GeC middle layer is deposited by RF sputtering the GeC target. This sputtering can be done under similar conditions to those in step 504, but with the power reduced to approximately 500 W to 1 kW (though other powers may be used). As discussed above, the thickness of the middle layer produced in this step should be between approximately 3 and 20 nm, and preferably between approximately 10 and 20 nm, though greater thickness is possible. Optionally, the GeC target may be co-sputtered together with the GeSe target, to provide GeSe:C impurities in the middle layer. Optionally, in some embodiments, a dense electron-cyclotron-wave resonance (ECWR) plasma may be generated by exciting and ionizing carbon atoms, to enhance the reactivity of the carbon atoms.
In step 508, a second layer of GeSe is deposited, using a process similar or identical to that used in step 504. The thickness of this layer may be approximately 20 nm, though a different thickness may be used. This would give the triple-layer matrix an approximate thickness of 50 to 60 nm, though this will vary with the thickness of the layers.
In step 510, the doping material Ag is deposited, and in step 512, the Ag doping material is diffused into the matrix by, for example, photodiffusion.
In step 514, the memory element is completed by depositing the Ag top electrode. This may be done, for example, by DC magnetron sputtering from an Ag target in a noble gas.
Referring to
Referring now to
In step 804, information is stored in the resistive memory element by reversibly forming a conductive bridge through the first solid electrolyte layer, the middle layer, and the second solid electrolyte layer, as described hereinabove.
Referring to
In
Next, as shown in
Memory cells including memory elements such as those described above may be used in memory devices that contain large numbers of such cells. These cells may, for example, be organized into an array of memory cells having numerous rows and columns of cells, each of which stores one or more bits of information. Memory devices of this sort may be used in a variety of applications or systems. As shown in
As shown in
While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
