The present invention relates to the field of rewritable non-volatile memories, and more specifically to that of resistive random access memories. A resistive random access memory comprises first and second electrodes separated by a layer made of electrically insulating material, and passes from an insulating state to a conducting state by formation of a conductive filament between the first and second electrodes.
Resistive Random Access Memories (RRAM) are today the subject of great interest, particularly on account of their low electrical consumption and their high operating speed.
A resistive type memory cell has at least two states: a “High Resistance State” (HRS), also called “OFF” state, and a “Low Resistance State” (LRS) or “ON” state. It may thus be used to store binary information.
Three types of resistive memories may be distinguished: memories based on thermochemical mechanism, memories based on valence change, and memories based on electrochemical metallisation.
The field of the present invention more particularly relates to this latter category based on ion conduction materials (CBRAM or “Conductive Bridging RAM” memories). The operation resides in the reversible formation and rupture of a conductive filament in a solid electrolyte, through dissolution of a soluble electrode. These memories are promising due to their low programming voltages (of the order of a Volt), their short programming times (<1 μs), their low consumption and their low integration cost. Furthermore, these memories can be integrated into the metallisation levels of the logic of a circuit (“above IC”), which makes it possible to increase the integration density of the circuit. From the architectural viewpoint, they only require a selection device, a transistor or a diode for example.
The operation of CBRAM memories is based on the formation, within a solid electrolyte, of one or more metal filaments (also called “dendrites”) between two electrodes, when the electrodes are taken to suitable potentials. The formation of the filament makes it possible to obtain a given electrical conduction between the two electrodes. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus to modify the electrical conduction between the two electrodes. For example, by reversing the potential between the electrodes, it is possible to make disappear or reduce the metal filament, so as to eliminate or reduce considerably the electrical conduction due to the presence of the filament.
This device 1 is formed by a Metal/Ion conductor/Metal type stack. It comprises a solid electrolyte 2, for example based on doped chalcogenide (e.g. GeS) or oxide (e.g. Al2O3). The electrolyte 2 is arranged between a lower electrode 3, for example made of Pt, forming an inert cathode, and an upper electrode 4 comprising a portion of ionisable metal, for example copper, and forming an anode. A portion of ionisable metal is a portion of metal able to form metal ions (here Cu2+ ions) when it is subjected to a suitable electrical potential. The device 1 represented in
As indicated previously, the memory state of a CBRAM memory device results from the difference in electrical resistivity between two states: “ON” and “OFF”.
In the “OFF” state, the metal ions (here Cu2+ ions for a soluble electrode comprising Cu) coming from the portion of ionisable metal are dispersed throughout the solid electrolyte 2. Thus, no electrical contact is established between the cathode 3 and the anode 4, that is to say between the upper electrode and the lower electrode. The solid electrolyte comprises an electrically insulating zone of high resistivity between the anode and the cathode.
When a positive potential V is applied to the upper soluble electrode 4 (the anode), an oxidation-reduction reaction takes place at the electrode, creating mobile ions 5. In the case of a copper electrode 4, the following reaction takes place:
Cu→Cu2++2e−.
The ions 5 then move in the electrolyte 2 under the effect of the electrical field applied to the electrodes. The speed of movement depends on the mobility of the ion in the electrolyte in question, which guides the choice of the soluble electrode/electrolyte pairing (examples: Ag/GeS; Cu/Al2O3, etc.). The speeds of movement of the ions are of the order of nm/ns.
On arrival at the inert electrode 3 (the cathode), the ions 5 are reduced due to the presence of electrons supplied by the electrode 3, leading to the growth of a metal filament 6 according to the following reaction:
Cu2+++2e−→Cu
The filament 6 grows preferentially in the direction of the soluble electrode 4.
The memory 1 then passes to the “ON” state when the filament 6 enables contact between the electrodes 3 and 4, making the stack conductive. This phase is called “SET” of the memory.
To pass to the “OFF” state (“RESET” phase of the memory), a negative voltage V is applied to the upper electrode 4, leading to the dissolution of the conductive filament. To justify this dissolution, thermal (heating) and oxidation-reduction mechanisms are generally put forward.
Often, the electrolyte 2 contains in the “OFF” state a residual filament 6 in contact with the cathode 3. This stems from the preceding SET phase and has not been dissolved completely during the RESET of the memory. The filament is designated residual when it does not establish a sufficient electrical conduction between the electrodes to obtain the “ON” state.
An area of development for CBRAM memories relates to the retention of information, that is to say the retention of the “OFF” state and the “ON” state. It is sought to improve the stability of the insulating and conducting states, particularly for high operating temperatures. Numerous studies relate to these CBRAM memories in order to improve their electrical performances. One of the difficulties of CBRAM memories in fact relates to the difficulty of forming the filament in the electrolyte.
An aspect of the invention is thus to propose a metal oxide based CBRAM memory cell having improved retention of information. Another aspect of the invention is to propose a metal oxide based CBRAM memory cell having improved electrical performances.
An aspect of the invention thus relates to a resistive random access memory device comprising:
“Chalcogen element” is taken to mean an element of group 16 of the periodic table. The interface layer beneficially makes it possible to contribute to the creation of a plurality of oxygen vacancies at the interface with the solid electrolyte made of metal oxide. This plurality of oxygen vacancies makes it possible to facilitate the movement of mobile ions, and thus the formation of the conductive filament. This thus contributes to reducing the forming voltage, that is to say the voltage to apply between the soluble electrode and the inert electrode to enable the formation of the conductive filament during the forming step. The interface layer also beneficially makes it possible to contribute to improving the retention of information, that is to say to the increase of the persistence of the conductive filament within the metal oxide based solid electrolyte, when no voltage is applied. The interface layer is in fact able to behave like a barrier for the mobile ions forming the conductive filament, thereby avoiding any dissolution of the filament.
Apart from the characteristics that have been evoked in the previous paragraph, the resistive random access memory device according to an aspect of the invention may have one or more additional characteristics among the following, considered individually or according to any technically possible combinations thereof:
Another aspect of the invention relates to a first method of manufacturing a resistive random access memory device according to an aspect of the invention, comprising the following steps:
Apart from the steps cited in the preceding paragraph, the method of manufacturing a resistive random access memory device according to the first embodiment of the invention may have one or more additional steps among the following, considered individually or according to all technically possible combinations thereof:
Embodiments of the invention and its different applications will be better understood on reading the description that follows and by examining the figures that accompany it.
The figures are presented for indicative purposes and in no way limit the invention.
Unless stated otherwise, a same element appearing in the different figures has a single reference.
In the present description, the expressions “CBRAM memory cell”, “CBRAM type memory device” and “resistive random access memory device” will be employed indiscriminately.
The second electrode E2 includes:
The first electrode E1 is made of an inert conductive material, that is to say not participating in the formation of a conductive filament within the solid electrolyte ML made of metal oxide. This inert conductive material may typically be:
In the particular example represented in
Alternatively, the following configurations, considered individually or according to all technically possible combinations thereof, could be adopted:
The ion source layer ISL of the second electrode E2 is made of soluble conductive material, that is to say participating in the formation of a conductive filament within the solid electrolyte ML made of metal oxide. The soluble conductive material may be for example:
The diffusion barrier DB of the second electrode E2 is made of a conductive material, such as for example:
The diffusion barrier DB is typically a thin layer, of thickness less than or equal to 5 nm. The thickness of the diffusion barrier DB is measured along a direction substantially perpendicular to the reference plane.
It will be appreciated that the diffusion barrier DB makes it possible to contribute to an efficient control of the concentration of the transition metal in the interface layer INT.
The electrical contact layer CT of the second electrode E2 is made from a conductive material, such as for example Ti—TiN, that is to say a layer of Ti and a layer of TiN, or Ta—TaN, that is to say a layer of Ta and a layer of TaN.
According to the first embodiment of the invention, the interface layer INT1 of the first type comprises:
In an embodiment, the transition metal is titanium Ti, or alternatively hafnium Hf or zirconium Zr. In an embodiment, the chalcogen element is tellurium Te, or alternatively sulphur S or selenium Se.
The interface layer INT1 of the first type according to the first embodiment of the invention is also designated by the acronym ICL (Ion Crossing Layer).
According to a second embodiment of the invention, the CBRAM memory cell (reference 20 of
The interface layer INT2 of the second type is particularly represented in
In the same way as previously:
The soluble conductive element of the interface layer INT2 of the second type is beneficially the same as the soluble conductive element of the ion source layer ISL. Thus, for example, when the ion source layer ISL is made from copper Cu, the soluble conductive element of the interface layer INT2 of the second type is copper Cu. The interface layer INT2 of the second type is also designated by the acronym IBL (Ion Buffer Layer). The choice of the soluble conductive material of the ion source layer ISL thus determines the soluble conductive element present in the interface layer INT2 of the second type.
The method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment firstly comprises the following steps:
The first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment then comprises a thermal annealing step, illustrated in
The thermal annealing step enables the at least partial diffusion of the transition metal of the C2 layer, deposited previously, into the C1 layer comprising the chalcogen element. At the end of the thermal annealing step, the diffusion of the transition metal into the C1 layer makes it possible to obtain the interface layer of the first type INT1, comprising the transition metal and the chalcogen element.
According to a first alternative, the first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment may comprise, in addition to the thermal annealing step that has just been described, a UV irradiation step. This UV irradiation step is then carried out typically with an average power comprised between 20 mW/cm2 and 150 mW/cm2, for a duration comprised between 1 minute and 20 minutes, and for wavelengths comprised between 100 nm and 400 nm.
It will be appreciated that the UV irradiation step makes it possible to break bonds in the solid electrolyte made of metal oxide, and thus to generate defects capable of promoting oxygen vacancies in the solid electrolyte made of metal oxide.
According to this first alternative, the steps of thermal annealing and UV irradiation may then take place simultaneously or not. Thus, generally speaking:
The first method 100 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment finally comprises the following steps:
The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.
The second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment firstly comprises, in the same way as the first method 100, the following steps:
The second method 200 then comprises a step of depositing, on the solid electrolyte made of metal oxide ML, a C3 layer comprising the transition metal, the chalcogen element and a soluble conductive element. The soluble conductive element of the C3 layer is able to participate in the formation of a conductive filament within the solid electrolyte made of metal oxide ML and may thus for example be:
The second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment then comprises, in the same way as the first method 100, a thermal annealing step, illustrated in
The thermal annealing step enables the at least partial separation of the species of the C3 layer and to obtain:
According to a first alternative, the second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment may comprise, in addition to the thermal annealing step that has just been described, a UV irradiation step. This first alternative has been described previously in the case of the first method 100. The UV irradiation step makes it possible to break the bonds in the solid electrolyte made of metal oxide, and thus to generate defects capable of promoting oxygen vacancies in the solid electrolyte made of metal oxide.
The second method 200 of manufacturing a metal oxide based CBRAM memory cell 10 according to the first embodiment finally comprises the following steps:
The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.
The choice of the soluble conductive element of the C4 layer is determined by the type of soluble conductive material that it is wished to use later to form the ion source layer ISL. For example, in the case where it is wished to form later an ion source layer ISL made of copper Cu, the soluble conductive element of the C4 layer is copper Cu.
The first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment then comprises a thermal annealing step, illustrated in
The thermal annealing step enables the at least partial diffusion of the transition metal of the C2 layer, deposited previously, into the C4 layer comprising the chalcogen element and the soluble conductive element. At the end of the thermal annealing step, the diffusion of the transition metal into the C4 layer makes it possible to obtain the interface layer of the second type INT2, comprising the transition metal, the chalcogen element and the soluble conductive element.
According to a first alternative, the first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment may comprise, in addition to the thermal annealing step that has just been described, a UV irradiation step. This first alternative has been described previously in the case of the first method 100 of manufacturing the metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention. The UV irradiation step makes it possible to break bonds in the solid electrolyte made of metal oxide, and thus to generate defects capable of promoting oxygen vacancies in the solid electrolyte made of metal oxide.
The first method 300 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment finally comprises the following steps:
The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.
As evoked above,
The second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment firstly comprises the following steps:
The soluble conductive element of the C5 layer is typically determined by the type of soluble conductive material that it is wished to use later to form the ion source layer ISL. In the case where it is wished to form later an ion source layer ISL made of copper Cu, the soluble conductive element of the C3 layer is copper Cu.
The second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment then comprises a thermal annealing step, illustrated in
According to a first alternative, the second method 400 of manufacturing the metal oxide based CBRAM memory cell 20 according to the second embodiment may comprise, instead of the thermal annealing step that has just been described, a UV irradiation step. According to a second alternative, the second method 400 may comprise the thermal annealing step and the UV irradiation step. These first and second alternatives have been described previously in the case of the first method 100 of manufacturing the metal oxide based CBRAM memory cell 10 according to the first embodiment of the invention.
The thermal annealing step and/or the UV irradiation step enable the at least partial diffusion of the soluble conductive element of the C5 layer, deposited previously, into the interface layer of the first type INT1. At the end of the thermal annealing step and/or the UV irradiation step, the diffusion of the soluble conductive element into the interface layer of the first type INT1 makes it possible to obtain the interface layer of the second type INT2, comprising the transition metal, the chalcogen element and the soluble conductive element.
The second method 400 of manufacturing the CBRAM memory cell 20 according to the second embodiment finally comprises the following steps:
The ion source layer ISL, the diffusion barrier DB and the electrical contact layer CT form the second electrode E2.
Number | Date | Country | Kind |
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1455332 | Jun 2014 | FR | national |
This application is a divisional of U.S. patent application Ser. No. 14/737,593, filed Jun. 12, 2015, which claims priority to French Patent Application No. 1455332, filed Jun. 12, 2014, the entire contents of which are incorporated herein by reference in their entirety.
Number | Date | Country | |
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Parent | 14737593 | Jun 2015 | US |
Child | 15784689 | US |