The invention relates generally sputter deposition in the formation of semiconductor integrated circuits. In particular, the invention relates to a combination of sputter deposition and sputter etching in forming liner layers.
Magnetron sputtering has long been used in the deposition of horizontally extending layers of metallization such as aluminum and copper. More recently, magnetron sputtering has been adapted to the more challenging task of depositing liner layers in high aspect-ratio holes such as inter-level electrical contacts, also called vias. A via 10 for a copper metallization, illustrated in the cross-sectional view of
A conventional dielectric material for both dielectric layers 14, 16 has been silicon dioxide (silica) but more recently low-k dielectric materials have been developed, some of which are composed of silicon oxycarbide having a significant carbon content. Further, the dielectric material may be made porous to obtain very low values of dielectric constant. To prevent copper from migrating into the dielectric material, a thin barrier layer 20 is deposited on a via sidewall 22 and usually also on a field region 24 on top of the upper dielectric layer 16. The barrier layer 20 preferably is not formed on a via bottom 26 so as to reduce contact resistance to the underlying conductive feature 12. A conventional barrier material for copper metallization is tantalum, either a single Ta layer or a Ta/TaN barrier layer. Ruthenium tantalum is also being developed as a barrier material. Techniques have been developed to selectively coat the barrier layer 20 into the narrow via hole 18 by magnetron sputtering of a tantalum, ruthenium, or ruthenium tantalum target. The nitride layer is similarly deposited by reactive sputtering in which nitrogen is additionally admitted into the sputter chamber.
Electrochemical plating (ECP) is typically used to fill the via hole 18 with copper although electroless plating is possible. ECP copper usually requires a copper seed layer both to serve as a plating electrode and to nucleate the ECP copper. Accordingly, a copper seed layer 30 is deposited on the via sidewall 22 and the field region 24 as well as the via bottom 26 in somewhat conformal layers. Again, magnetron sputtering techniques have been developed for depositing copper fulling these demanding requirements. These techniques rely upon a high ionization fraction of the sputtered copper atoms and electrical biasing of the wafer to draw the copper ions deep within the via hole 18 to deposit a substantial bottom portion 32 and an acceptably thick sidewall portion 34. The sidewall coverage is accomplished in part by energetic copper ions which are accelerated by the wafer bias and resputter, that is, sputter etch, copper from the bottom portion 32 onto the sidewall portion 34. The copper sputtering may also produce a relatively thick field portion 36 on top of the field region 24. Significant overhangs 38 develop on the corners of the field portion 36 at the top of the via hole 18 producing a narrow throat 40 We have observed that the overhangs 38 mostly develop above the barrier layer in the field region 20. That is, the narrowest portion of the throat 40 is above the bottom of the copper field portion 36.
To complete the metallization, copper is plated, for example, by electroplating, into the via hole 18. The ECP copper overfills the via hole 18 and deposits over the field region 24. Chemical mechanical polishing (CMP) is used to remove the copper over the barrier layer 20 outside the via hole 18, thereby leaving only copper in the via hole 18.
Metallization structures are often more complex than the via structure 18 of
Returning to the simpler via structure of
Some believe that increasing both the copper ionization fraction and the wafer bias causes the copper ions to mill the developing overhangs. We believe, however, that energetic copper ions do not limit the growth of the overhangs. Instead, the energetic copper ions tend to resputter the copper from the overhangs to portions of the sidewall underlying the overhangs. As a result, the resputtering effectively pushes the overhangs down into the via hole. While the extent of the overhangs may be somewhat reduced, if the overhangs are pushed below the level of the field barrier, the overhang etching may expose a facet of the barrier layer at the corner of the via hole and etch through it, thereby locally destroying the barrier.
Another solution is needed for reducing the size of the overhangs and improving the ability to fill high aspect-ratio vias.
Further but related problems arise when the dielectric material is a carbon-containing low-k dielectric material such as Black Diamond II available from Applied Materials, Inc. of Santa Clara, Calif. Such materials do not afford the highly anisotropic etch available in silica. The problems worsen when the dielectric material is made porous to further decrease the dielectric constant. As illustrated with exaggeration in the cross-sectional view of
Yet further, the vertical structure to be etched through during the dielectric etch process may be more complicated than previously illustrated. As illustrated in the cross-sectional view of
The sputter deposition of copper seed layer may not completely coat sides of the concave sidewall 54 or recesses 64, 64 resulting in the same problems discussed before for overhangs.
A copper seed layer is formed in a via or other hole in a semiconductor integrated circuit by a multiple-step process. First, copper is deposited in a plasma sputtering process under conditions creating a high fraction of copper ions and the wafer is biased to accelerate the copper ions and attract some of them deep into the hole. The copper deposits at least at the bottom of the hole and in the field region and overhangs may form over the hole. Secondly, an argon plasma is formed and the wafer is biased to accelerate the argon ions and to attract at least some of them deep in the hole. The energetic argon ions resputter copper at the bottom of the via onto the via sidewalls and also sputter etch the field region to reduce the size of the overhangs. The overhangs should not be etched below the top of the hole.
A final copper sputter deposition may be performed prior to electroplating copper into the remaining portion of the hole.
The sputter deposition and etch process may be repeated to fill more of the hole before copper electroplating. If the sputter and etch process are repeated sufficiently, the hole may be filled with copper by the last deposition step to fill the hole so that chemical mechanical polishing may immediately follow the sputter deposition.
The sputter deposition and etch processes may be performed in a single plasma sputter chamber. For example, the chamber may be equipped with an RF coil. Sputter deposition is favored at low argon pressure, high target power, and low coil power. Sputter etching is favored at higher argon pressure, lower target power, and higher coil power. The substrate should be strongly biased for at least the initial copper deposition steps and for the argon sputter etching steps.
Filling copper into high aspect-ratio holes such as vias and dual-damascene interconnects is facilitated by a combination of copper sputter deposition and argon sputter etching preferably performed in a single copper sputter chamber. The energetic sputter etching reduces the size of overhangs and also tends to redistribute copper into concave portions of the sidewalls in a process often referred to as resputtering.
Although some aspects of the invention are not so limited, the sputter deposition and sputter etching are preferably performed in a chamber with an RF coil which can excite an argon plasma for the argon sputter etch with limited if any sputtering of the copper target during the etch phase. Ding et al. have described a sputter deposition/etch sequence of a tantalum barrier in an inductively coupled sputter chamber in U.S. patent application Ser. No. 10/915,139, filed Aug. 9, 2004, now published as U.S. patent application publication 2006/0030151. A similar sputter chamber 70 is illustrated in the cross-sectional view of
A copper target 106 is supported on the upper adapter 80 through an isolator 108 electrically isolating the electrically biased target 106 from the grounded vacuum chamber and grounded shields 90, 92. At least the face of the target 106 is composed of at least 90 at % copper and possible intentional alloying and unintentional impurities totaling less than 10 at %. A pedestal 110 supports a wafer 112 to be sputter processed in opposition to the target 106. The RF coil 110 is placed in the lower half or even third of the chamber between the target 106 and pedestal 110 to generate a plasma near the wafer 112. A shadow ring 114 interlocking with the ascending lip of the cup-shaped lower shield 90 overhangs the peripheries of the wafer 112 and the pedestal 110 to protect them from sputter processing. A sidewall magnet system 116 is placed outside the lower adapter 78 on a level with and partially below the RF coil 100 to create a magnetic barrier against diffusion of the plasma to the chamber walls. The magnet system 116 may be an annular array of vertically polarized magnets or a DC coil arranged about the central axis 74.
A functional cross-sectional view of the chamber is illustrated in
A magnetron 126 positioned in back of the target 106 includes an outer pole 128 of one vertical magnetic polarity surrounding an inner pole 130 of the other polarity. The magnetron 126 is preferably strong, small, and unbalanced in the sense that the total magnetic intensity of the outer pole 128 is substantially larger than that of the inner pole 130 it surrounds. It projects a magnetic field in front of the target 106 to trap electrons and thereby increases the density of the plasma and hence the sputtering rate. A copper target is capable of self-sustained sputtering so that once the plasma has been excited, the argon pressure can be reduced even substantially to zero because the high-density plasma ionizes the sputtered copper atoms and the copper ions are partially attracted back to the target 106 to continue the sputtering. To produce more uniform target sputtering, the magnetron 126 although located away from the central axis 74 is rotated about it by a motor 132 rotating a rotary shaft 134 extending along the central axis 74 to more uniformly sputter the target 106. An arm 136 fixed to the rotary shaft 134 supports the magnetron 126 in its rotational movement.
A coil RF power supply 136 supplies RF power to the RF coil 100 to generate an argon plasma in a region removed from the target 106. Generally, the target 106 is DC powered for sputter deposition and the RF coil 100 is RF coil for sputter etching of the wafer 112. However, an RF supply may power the target sputtering.
A bias RF power supply 138 electrically biases the pedestal 110 through a capacitive coupling circuit 140. In the presence of a plasma, the capacitively coupled RF bias causes the pedestal 110 to develop a negative DC self-bias to attract and accelerate ions from the plasma to the wafer 112. The ions so attracted may be copper ionized atoms sputtered from the target 106 or argon ions primarily generated by the RF coil 100.
Such a sputter chamber can be used for a sequence of copper sputter deposition and sputter etch steps.
A highly biased sputter deposition of copper ions into a via hole 18 produces, as schematically illustrated in the cross-sectional view of
Scanning electron micrographs (SEMs) were taken to experimentally confirm the two-step process of deposition and etch. As illustrated in the cross-sectional view of
SEMS were taken in a more methodical set of experiments. Sputter deposition of 100 nm or 140 nm of copper into narrow trenches to form a copper film 156 produces severe overhangs 158, as illustrated in the cross-sectional view of
The sputter etch step depends upon an energetic heavy ion, such as argon, being accelerated toward the wafer and sputtering material from the wafer. The energy EION of the singly charged ion depends on both the wafer floating voltage VFLOATING and the plasma potential VPLASMA depending upon wafer biasing according to
E
ION
=eV
FLOAT
+eV
PLASMA.
The floating potential VFLOAT is typically less than 20 volts so the plasma potential VPLASMA needs to be increased to obtain larger ion energy EION by increasing the RF power applied to the pedestal electrode. The ion energy can be effectively increased by increasing the plasma potential, for example, in a capacitively coupled plasma. Both plasma argon ions and copper ions sputtered from the target effectively sputter deposited copper and they have their respective advantages. A higher ionization density is typically available from an argon plasma but argon ions remove material at the bottom of the via and seem to degrade gap fill. On the other hand, energetic copper ions may simultaneously mill copper overhangs at the top of the gap and redistribute copper at the bottom of the gap. The RF coil 100 allows the copper ion energy to be decoupled from the copper ion flux. The RF coil 100 also allows very low pressure copper sputter etching with less than 0.4 milliTorr of argon.
The energy of the ion producing sputter etching affects the gap fill performance. Ions of higher energy more effectively remove the overhangs and open the throat to produce a better seed layer inside the via and to facilitate the ECP fill, thus promoting gap fill. An ion energy of 320 eV in a 70% etch back produces significantly better gap fill than an ion energy of 70 eV.
Temperature of the pedestal and hence the wafer during etching has also been found to play an important role in reducing the overhangs, presumably because of the reflow of copper at higher temperatures. As the wafer temperature increases from 28° C. to 150° C. with 1 kW of RF coil power and 1 kW of wafer bias power, the overhangs are significantly reduced. However, a further temperature increase to 250° C. produces significant copper overhangs but also significant bottom coverage. In general terms, a deposition temperature above 50 or 70° C. reduces the size of the overhangs to promote sputtering into the via holes. An even higher deposition temperature of above 150° C. promotes reflow of the already deposited copper into and within the via hole, thus improving sidewall coverage. However, a deposition temperature of above 250° C. causes thin layers of copper to agglomerate into localized islands and thus in some applications should be avoided in order to assure a continuous thin seed layer.
The ability to use the same chamber for both sputter deposition and sputter etch enables a variety of copper gap fill processes. As illustrated in the flow diagram of
The etch step 162, as illustrated in
In one method, a relatively low level of DC power is applied to the target and the RF coil is strongly powered so that most of the wafer etching is effected by argon ions. Argon sputtering is effective at removing the copper bottom portion 32 but it seems to produce difficulties in copper filling of the hole.
In a second method, a high fraction of copper ionization is achieved and high bias power is applied to the wafer with little argon. As a result, the wafer etching is effected mainly by copper ions. For sputtering of copper, which allows self-sustained sputtering, the argon pressure may be reduced or its direct supply into the main chamber may be stopped. Copper sputter etching benefits from resputtering near the bottom and promotes copper hole filling.
Copper ion etching requires a magnetron producing a high copper ionization fraction and generally needs extra measures to achieve good etch uniformity. Such measures may include sidewall magnets or electromagnets adjacent the wafer. Copper ion sputtering may be accomplished in two different types of chambers. A capacitively coupled plasma may be produced of sufficient plasma density by high DC power applied to the target without the use of an RF coil to produce many copper ions. The sputtering process are at least close to those required for sustained self-sputtering. Capacitively coupled sputter etching, however, lacks the additional process control afforded by the RF coil. On the other hand, an inductively coupled plasma relies on the RF inductive coil to support a plasma near the wafer to increase the copper ionization. Inductively coupled generation of the plasma eases the requirements of high target power and strong magnetrons so auxiliary means for improving the etch uniformity are less important.
The generation of a high plasma density, particularly for argon ion etching, is promoted. dual-frequency (HF/VHF) biasing of the wafer, e.g., 13.56 MHz and 60 MHz, RF inductive coils intermediate the target and pedestal, or additional VHF biasing of the target, e.g. 60 MHz using an auxiliary electrode near the pedestal.
An example of an inductively coupled argon etch includes applying between 0 and 1 kW of DC power to the target, applying between 450 W and 3 kW of RF power at 2 MHz to the inductive coil, and applying between 400 to 1250 W of RF power at 13.56 MHz to the pedestal. The magnetron is relatively unimportant in the argon etch. The argon chamber pressure is maintained between 0.4 to 5 milliTorr and counter-rotating DC currents of −17 A and 17 A are applied to the bottom inner and outer electromagnets of the quadruple electromagnet array described by Gung et al. in U.S. patent application publication 2005/0263390, incorporated herein by reference.
An example of a recipe for a capacitively coupled argon ion etch includes applying between 1 and 10 kW of DC power to the target scanned by a strong magnetron, applying between 800 and 1250 W of RF bias power at 13.56 MHz to the pedestal while maintaining the argon chamber pressure between 0.4 and 1.5 milliTorr.
An example of a recipe for a capacitively coupled copper ion etch includes applying between 15 and 30 kW of DC power to the target scanned by the strong magnetron, applying between 1.5 and 2.5 kW of RF bias power at 13.56 MHz the pedestal while maintaining the argon chamber pressure between 0.4 and 1.5 milliTorr. The high bias power produces a net etch rate.
An example of a recipe for a dual-frequency pedestal includes applying to the pedestal between 500 to 200 W of VHF power at 60 MHz and between 400 and 1200 W of HF power at 13.56 MHz while maintaining an argon chamber pressure of between 2 and 30 milliTorr.
An example of a recipe for an auxiliary annular electrode located in the lower portion of the chamber includes applying 1 kW of VHF power at 60 MHz to the auxiliary electrode and 1 kW of HF power at 13.56 MHz to the pedestal with an argon pressure of 0.5 to 4 milliTorr.
An example of a recipe for a sputter etch chamber includes 1 to 2 kW of VHF power to a pedestal electrode, 1 to 2 kW of VHF power at 60 MHz on the target, and 0 to 1.2 kW of HF at 13.56 MHz on the wafer pedestal at 1 to 4 milliTorr of discharge pressure.
The structure of
The process described above was used to fill a large number of vias in a test wafer in which the vias had critical dimensions of 35 to 50 nm with aspect ratios of above 5:1. The ECP filled structure was sectioned and SEMs were imaged. In a comparative experiment, 50 nm of seed copper was deposited and the via holes were then filled with ECP copper without intermediate etching. A significant fraction of the vias were formed with voids extending through their bottom third or half. When the copper seed was subjected to a 40% etch back with the argon sputter etching of the invention, the number of voided vias was reduced but not eliminated. When the etch back was extended to 70% and 80%, substantially all the vias were completely filled.
In a further embodiment of the process of the invention, the deposition and etch steps 160, 162 may be repeated to produce respectively the structures illustrated in the cross-sectional view of
In a yet further embodiment, the deposition and etch steps 160, 162 may be repeated yet further times, for example, for a total of three or four sequences, to almost fill the via hole 18, as shown in the flow diagram of
It is possible to adapt the invention to reduce the amount of wafer biasing between subsequent sputter deposition steps.
It is possible to practice the invention in separate sputter deposition and sputter etching chambers.
It is possible to adapt the invention to reduce the amount of wafer biasing between subsequent sputter deposition steps.
It is possible to practice the invention in separate sputter deposition and sputter etching chambers.
The invention provides several fabrication methods, which may be used on available commercial equipment, of sputtering a copper seed layer into via holes of increased aspect ratio.
This application claims benefit of provisional application 60/888,893, filed Feb. 8, 2007.
Number | Date | Country | |
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60888893 | Feb 2007 | US |