The present invention relates generally to bulk semiconducting materials that are structurally designed and chemically engineered at nanometer dimensional scales to exhibit properties of a three-dimensional electron gas, and in particular to the incorporation of these unique semiconductor materials into a semiconductor carrier that is used to electrically interconnect additional semiconductor die comprising a larger microelectronic system with other active electrical or opto-electronic devices monolithically integrated into the carrier surface.
The present invention relates specifically to a bulk semiconducting material that consists of a uniform distribution of nanoscale polycrystalline grains wherein the diameter of the polycrystalline grains is limited to nanometer physical dimensions such that the nanoscale texture of the semiconducting material induces quantum-size effects within the polycrystalline grains that endow the bulk semiconductor with electrical or optical properties (herein referred to as “general dielectric properties”) of a three-dimensional (3D) electron gas. An additional specific embodiment of the invention relates to methods and processes that diffuse electrically conducting or electrical insulating materials into the grain boundaries of the nanoscale polycrystalline grains.
The present invention relates generally to the monolithic assembly of an active electronic, photonic, or opto-electronic device that comprises a layer of semiconductor material having thickness greater than 50 nm which exhibits the general dielectric properties of a 3D electron gas onto a semiconductor chip carrier that is used to electrically interconnect various additional semiconductor die into a more sophisticated microelectronic system. Such various active electronic or opto-electronic devices may include, but are not limited to, high power density/high-speed power management circuits, stable clock generators, electrical signal modulators, optical sensors, optical power generators, optical signal generators and/or modulators or thermoelectric systems,
1. Description of the Prior Art
T. J. Phillips et al. (U.S. Pat. No. 7,173,292), (hereinafter referred to as Phillips '292), teaches that runaway currents (avalanche breakdown) caused by impact ionization in modulation-doped field effect (MODFET) or high electron mobility (HEMT) transistors applied to narrow band gap semiconductor materials is mitigated or substantially eliminated by forming a quantum well field effect transistor (QWFET). The quantum well FET consists of thin multi-layered structures comprising one or more wide band gap semiconductors. (See
The field effect device is created by inserting the quantum well region 2 between two conductive doped source 8 and drain 9 regions. An electrical bias applied to the gate electrode 10 is then used to modulate current supplied to the source electrode 11 when it is collected by the drain electrode 12. The high charged carrier mobilities available in QWFET devices enable high switching speeds reported in the range between 250 GHz to 1 THz, and thus have value in high switching speed systems or millimeter-wave communications systems.
In a QWFET device, the central layer 6 must be sufficiently thin (20-50 nm) to form a 2-D electron gas through quantization effects in the quantum well contained in the primary conduction channel. The quantization effects are generated by the nanometer scale thickness of the central layer 6 and the height of the band edges 26,27 created by contacting to the semiconductor layers 5,7 that form the quantum well 28. These quantization effects create the discrete energy levels 29,30 of the high electron mobility 2-electron gas. The semiconductor layers 5,7 provide higher ionization thresholds that prevent currents flowing in the primary conduction channel in the central layer 6 from undergoing avalanche breakdown through impact ionization processes. Examples of low band gap semiconductor materials used in the primary channels are indium antimonide (InSb), indium arsenide (InAs), indium arsenic antimonide (InAs(1-y)Sby), indium gallium antimonide (In(1-x)GaxSb), and/or indium gallium arsenide (In(1-x)GaxAs).
2. Definition of Terms
The term “active component” is herein understood to refer to its conventional definition as an element of an electrical circuit that that does require electrical power to operate and is capable of producing power gain.
The term “alkali metal” is herein understood to refer to its conventional definition meaning the group of metallic elements in column IA of the periodic table, consisting of lithium, sodium, potassium, rubidium, cesium, and francium.
The term “alkaline earth metal” is herein understood to refer to its conventional definition meaning the group of metallic elements found in column IIA of the periodic table, consisting of magnesium, calcium, strontium, barium, and radium.
The term “amorphous material” is herein understood to mean a material that does not comprise a periodic lattice of atomic elements, or lacks mid-range (over distances of 10's of nanometers) to long-range crystalline order (over distances of 100's of nanometers).
The terms “chemical complexity”, “compositional complexity”, “chemically complex”, or “compositionally complex” are herein understood to refer to a material, such as a metal or superalloy, compound semiconductor, or ceramic that consists of three (3) or more elements from the periodic table.
The term “chip carrier” is herein understood to refer to an interconnect structure built into a semiconductor substrate that contains wiring elements and embedded active components that route electrical signals between one or more integrated circuits mounted on chip carrier's surface and a larger electrical system that they may be connected to.
The term “electron gas” is herein understood to refer to its generally accepted definition as a collection of electrons (or holes) that are free to move within a modified solid via tunneling processes and have higher mobilities than they would normally have in a similar unmodified solid, wherein quantization effects generated by the solid's modification (typically nanoscale layering) induce a quantum energy well that govern and define the transport properties of the electrons (holes) and minimize interactions between the electron (holes) located within the quantum energy well.
The term “FET” is herein understood to refer to its generally accepted definition of a field effect transistor wherein a voltage applied to an insulated gate electrode induces an electrical field through insulator that is used to modulate a current between a source electrode and a drain electrode.
The term “halogen” is herein understood to refer to its conventional definition meaning the nonmetallic elements contained in column VIIA of the periodic table consisting of fluorine, chlorine, bromine, iodine, and astatine.
The term “halogenated” is herein understood to refer to its conventional definition meaning a molecule or substance that has been treated or combined with a halogen.
The term “integrated circuit” is herein understood to mean a semiconductor chip into which a large, very large, or ultra-large number of transistor elements have been embedded.
The term “LCD” is herein understood to mean a method that uses liquid precursor solutions to fabricate materials of arbitrary compositional or chemical complexity as an amorphous laminate or free-standing body or as a crystalline laminate or free-standing body that has atomic-scale chemical uniformity and a microstructure that is controllable down to nanoscale dimensions.
The term “liquid precursor solution” is herein understood to mean a solution of hydrocarbon molecules that also contains soluble metalorganic compounds that may or may not be organic acid salts of the hydrocarbon molecules into which they are dissolved.
The term “microstructure” is herein understood to define the elemental composition and physical size of crystalline grains forming a material substance.
The term “mismatched materials” is herein understood to define two materials that have dissimilar crystalline lattice structure, or lattice constants that differ by 5% or more, and/or thermal coefficients of expansion that differ by 10% or more.
The term “nanoscale” is herein understood to define physical dimensions measured in lengths ranging from 1 nanometer (nm) to 100's of nanometers (nm).
The term “opto-electronic device” is herein understood to refer to any device that uses an electrical signal to modulate an optical signal having energetic characteristics defined by the optical, infrared (near, mid or far), millimeter wave, sub-millimeter wave, or ultraviolet (near or far) regions of the electromagnetic spectrum, or visa-versa.
The term “passive component” is herein understood to refer to its conventional definition as an element of an electrical circuit that that does not require electrical power to operate and is capable of altering an electrical signal's amplitude and/or phase or being used as an energy storage device.
The term “photonic device” is herein understood to refer to a device that uses a signal having energetic characteristics defined by the optical, infrared (near, mid, or far), millimeter wave, sub-millimeter wave, or ultraviolet (near or far) electromagnetic spectrum to modulate one or more additional signal having energetic characteristics defined by the optical, infrared (near, mid, or far), millimeter wave, sub-millimeter wave or ultraviolet (near or far) regions of the electromagnetic spectrum.
The term “power FET” is herein understood to refer to the generally accepted definition for a large signal vertically configured MOSFET and covers multi-channel (MUCHFET), V-groove MOSFET, truncated V-groove MOSFET, double-diffusion DMOSFET, modulation-doped transistors (MODFET), heterojunction transistors (HETFET), and insulated-gate bipolar transistors (IGBT).
The term “quantum dot” is herein understood to apply to its conventional meaning of a material domain that is small enough to induce quantum-size effects that exhibit the electronic, optical, or opto-electronic characteristics of an electron gas.
The term “standard operating temperatures” is herein understood to mean the range of temperatures between −40° C. and +125° C.
The terms “tight tolerance” or “critical tolerance” are herein understood to mean a performance value, such as a capacitance, inductance, or resistance that varies less than ±1% over standard operating temperatures.
The term “II-VI compound semiconductor” is herein understood to refer to its conventional meaning describing a compound semiconductor comprising at least one element from column IIB of the periodic table consisting of: zinc (Zn), cadmium (Cd), or mercury (Hg); and, at least one element from column VI of the periodic table consisting of: oxygen (O), sulfur (S), selenium (Se), or tellurium (Te).
The term “III-V compound semiconductor” is herein understood to refer to its conventional meaning describing a compound semiconductor comprising at least one semi-metallic element from column III of the periodic table consisting of: boron (B), aluminum (Al), gallium (Ga), and indium (In); and, at least one gaseous or semi-metallic element from the column V of the periodic table consisting of: nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), or bismuth (Bi).
The term “IV-IV compound semiconductor” is herein understood to refer to its conventional meaning describing a compound semiconductor comprising a plurality of elements from column IV of the periodic table consisting of: carbon (C), silicon (Si), germanium (Ge), tin (Sn), or lead (Pb).
The term “IV-VI compound semiconductor” is herein understood to refer to its conventional meaning describing a compound semiconductor comprising at least one element from column IV of the periodic table consisting of: carbon (C), silicon (Si), germanium (Ge), tin (Sn), or lead (Pb); and, at least one element from column VI of the periodic table consisting of: sulfur (S), selenium (Se), or tellurium (Te).
The present invention generally relates to fully integrated semiconductor chip carriers that contain systems that function at high switching speeds, and in particular to processes and methods that enable the monolithic integration of active devices comprising a bulk material layer exhibiting quantum-size effects or the characteristics of a quantum dot throughout the bulk material layer.
One embodiment of the present invention provides a three-dimensional polycrystalline semiconductor material, comprising a major ingredient forming individual crystalline grains having a nominal maximum grain diameter less than or equal to 50 nm, and a minor ingredient forming boundaries between the individual crystalline grains.
The minor ingredient may surround the crystalline grains of the major ingredient. Quantum size effects within the polycrystalline material may induce a free electron gas characteristic of a quantum well. The polycrystalline material may form a three-dimensional quantum well structure. The molar concentrations of the minor ingredient may be between 0.0001 mol % and 0.75 mol % of the polycrystalline material. The major ingredient may comprise the crystalline grains is silicon, germanium, tin, or any admixture thereof. The minor ingredient forming the grain boundaries may be an insulating, semi-insulating, or semiconducting material consisting of a metal halide comprising an alkali element from the first (I) column or an alkaline earth element from second (II) column of the periodic table, or a transition-metal having chemical properties similar to an alkali or alkaline earth metal, and a halogen element selected from the seventh (VII) column of the periodic table. The insulating or semi-insulating material has an energy band gap may be larger than the band gap of the semiconductor material comprising the polycrystalline grain. The minor ingredient forming the grain boundaries may be a conductive material consisting of an alkali element from the first (I) column or an alkaline earth element from second (II) column of the periodic table, or a transition-metal having chemical properties similar to an alkali or alkaline earth metal. The major ingredient may comprise crystalline grains is a III-V compound semiconducting material and the minor ingredient forming the boundaries may be an insulating, semi-insulating, or semiconducting material consisting of a metal halide comprising an alkali element from the first (I) column or a transition-metal having chemical properties similar to an alkali metal, and a halogen element selected from the seventh (VII) column of the periodic table. The major ingredient of the crystalline grains may be a II-VI compound semiconductor and the minor ingredient forming the boundaries is silicon, silicon carbide, germanium, tin or an admixture thereof. The polycrystalline material may have a three dimensional size that is greater than 50 nm in every direction. The polycrystalline material may be monolithically integrated into an active device. The active device may be a field effect transistor, an opto-electronic device or a photonic device. The major ingredient comprising crystalline grains may be a III-V compound semiconducting material and the minor ingredient forming the boundaries may be a conducting material consisting of an alkali element from the first (I) column or a transition-metal having chemical properties similar to an alkali metal.
Another embodiment of the present invention provides a semiconductor carrier, comprising an active device including a semiconductor layer that is monolithically integrated into the semiconductor carrier and is comprised of a nanoscale polycrystalline assembly including semiconducting crystalline grains having maximal physical dimensions in the range of 20 nm to 50 nm that are enveloped by a grain boundary material that is 2 nm to 10 nm thick, such that the quantum size effects within the polycrystalline grain induce a free electron gas characteristic of a quantum well.
The active device may be a field effect transistor, an opto-electronic device or a photonic device. The active device may comprise a power management module monolithically integrated on to its surface. The active device may comprise a semiconductor die. The semiconductor carrier may have active circuitry embedded within the carrier substrate.
Yet another embodiment of the present invention provides a method of fabricating a semiconductor layer comprised of a nanoscale polycrystalline assembly including semiconducting crystalline grains having maximal physical dimensions in the range of 20 nm to 50 nm that are enveloped by a grain boundary material that is 2 nm to 10 nm thick, such that the quantum size effects within the polycrystalline grain induce a free electron gas characteristic of a quantum well, comprising the steps of: forming a solution of low volatility liquid metalorganic precursors having stoichiometric ratios suitable for producing majority phase polycrystalline grains consisting of an elemental semiconductor or a desired compound semiconductor stoichiometry; adding to said solution dopants in concentrations in the range of 0.0001 mol % to 0.5 mol % having stoichiometric ratios suitable for producing an insulating, semi-insulating, or semiconducting secondary phase material in the grain boundary of the majority phase polycrystalline grains; adding to said solution precursors for the dopants to the majority phase polycrystalline grains in the concentrations desired within the polycrystalline grains, heating a substrate upon which the semiconductor layer will be formed a temperature in the range of 250° C. to 500° C.; simultaneously decomposing the non-volatile metalorganic precursors on the substrate in an inert or reducing gas atmosphere to form an amorphous deposit having stoichiometric precision that is chemically uniform at the atomic scale; baking said amorphous deposit to remove organic residue from the deposit; annealing said baked deposit for a minimum of 5 seconds in ionized argon plasma using an applied power of 50 W to 300 W at a substrate temperature between 40° C. and 400° C. and a pressure in the range of 1,500 mTorr to 5,000 mTorr; and optionally adding nitrogen, and/or reducing partial pressure ratios of carbon dioxide and carbon monoxide to the ionized argon plasma.
The semiconducting material of the crystalline grains may be silicon, germanium, tin, or any admixture thereof. The grain boundary material may be an insulating, semi-insulating, or semiconducting material consisting of a metal halide comprising an alkali element from the first (I) column or an alkaline earth element from second (II) column of the periodic table, or a transition-metal having chemical properties similar to an alkali or alkaline earth metal, and a halogen element selected from the seventh (VII) column of the periodic table. The insulating or semi-insulating material may have an energy band gap that is larger than the band gap of the semiconductor material comprising the polycrystalline grain. The semiconductor material of the crystalline grains may be a III-V compound semiconducting material and the grain boundary material is an insulating, semi-insulating, or semiconducting material consisting of a metal halide comprising an alkali element from the first (I) column or a transition-metal having chemical properties similar to an alkali metal, and a halogen element selected from the seventh (VII) column of the periodic table. The semiconducting crystalline grains may be a II-VI compound semiconductor and the grain boundary material may be silicon, silicon carbide, germanium, tin or an admixture thereof.
The present invention is illustratively shown and described in reference to the accompanying drawings, in which:
This application is copending with de Rochemont U.S. Ser. No. 13/168,922, entitled “SEMICONDUCTOR CARRIER WITH VERTICAL FET POWER MODULE”, filed Jun. 24, 2011 (de Rochemont '922), and de Rochemont U.S. Ser. No. 13/163,654, entitled “FREQUENCY-SELECTIVE DIPOLE ANTENNA”, filed Jun. 17, 2011 (de Rochemont '654), which are incorporated herein by reference. The current application instructs means to insert a bulk semiconductor layer into an active component integrated on a semiconductor carrier, where the bulk semiconductor layer has thickness greater than 50 nm and exhibits general dielectric properties of an electron gas. One counterpart application (de Rochemont '922) instructs means to fully integrate a high efficiency, power management system as a monolithic structure on a semiconductor carrier to modulate high current levels using a resonant three-dimensional gate structure enabled by serpentine windings. The other counterpart application, (de Rochemont '654), instructs methods to form a conducting element as a serpentine winding by folding the conducting element in ways that introduce localized regions of capacitive or inductive loading, such that the combination of localized reactive loads along the length of the folded conductor form a distributed network filter. It goes on to illustrate how two mirror image serpentine elements so formed function as a dipole antenna that is resonant over selective frequencies. The counterpart application de Rochemont '654 also instructs the insertion of tight-tolerance electroceramic material within the regions of localized reactive loading to increase or more precisely tune the coupling strength of localized reactive loads. The current application is also filed jointly with de Rochemont U.S. Ser. No. 13/216,692, entitled “POWER FET WITH RESONANT TRANSISTOR GATE”, filed Aug. 23, 2011 (de Rochemont '692), which is incorporated herein by reference. The co-pending application de Rochemont '692 instructs a power management module that modulates large currents at low current densities at pre-determined frequencies and methods to form the power management module on a semiconductor carrier.
The current application incorporates by reference all matter contained in de Rochemont, U.S. Ser. No. 11/479,159, filed Jun. 30, 2006, entitled “ELECTRICAL COMPONENT AND METHOD OF MANUFACTURE” (the '159 application), de Rochemont, U.S. Ser. No. 11/620,042 filed Jan. 6, 2007 entitled “POWER MANAGEMENT MODULES” (the '042 application), de Rochemont and Kovacs, U.S. Ser. No. 12/843,112 filed Jul. 26, 2010, “LIQUID CHEMICAL DEPOSITION PROCESS APPARATUS AND EMBODIMENTS”, (the '112 application), de Rochemont U.S. Ser. No. 13/152,222, entitled “MONOLITHIC DC/DC POWER MANAGEMENT MODULE WITH SURFACE FET”, filed Jun. 2, 2011 (the '222 application), and de Rochemont, U.S. Ser. No. 13/182,405, entitled “CUTTING TOOL AND METHODS OF MANUFACTURE”, filed Jul. 13, 2011 (the '405 application). The '159 application discloses how LCD methods fabricate a monolithic integrated circuit comprising tight tolerance passive networks. The '042 application discloses how liquid chemical deposition (“LCD”) methods fabricate a monolithic integrated power management module that includes a tunable inductor coil. The '112 application discloses preferred apparatus used in applying LCD methods. The '222 application instructs the monolithic integration of a low-loss power management circuit containing a surface FET. The '405 application discloses LCD methods to fabricate carbide, nitride and MAX-phase materials, such as silicon carbide, or complex chemistries that incorporate silicon and carbon elements.
Reference is now made to
It is anticipated that the integrated circuit semiconductor die 102 will have power demand requirements in excess of 750 W-inch2 as semiconductor manufacturing tolerances progress beyond the 22 nm line feature node. High-efficiency, high-speed fully integrated power management modules 108 are monolithically formed on the chip carrier 100, using methods and embodiments detailed in the '042, '122, '159, '222, '654, '692, '922 applications incorporated herein by reference. These methods and embodiments may be used to optimize data transfer between memory devices and processor die, or other semiconductor die co-located on the semiconductor carrier 100.
Reference is now made to
The prior art of
While the prior art teaches the use of multi-layer structures that induce 2D-electron gases within an ultra-thin plane of the ultra-high speed FET, the limitation restricting the primary conduction channel to thicknesses of 20-50 nm limits the overall currents that can be channeled through the high-electron mobility layers. Ultra-thin layers will cause high current densities that rapidly increase the probability of impact ionization and avalanche currents even at low power levels. Therefore, it is desirable to develop methods and embodiments that induce high electron mobility in semiconductor materials having thicknesses greater than 20-50 nm to reduce power densities in the high-speed layer. Higher currents can be achieved under the prior art, by creating multiple multi-layer structures comprising primary and secondary conduction channels. It is therefore desirable to produce a quantized conduction channel that has considerably greater thickness since the approach using multiple multi-layer structures has substantially higher cost and limited economic value when compared to a similar device that enables electron gas properties in a single semiconductor layer that is thicker than 20-50 nm. It is also desirable to develop methods and embodiments that enable electron gases in wider band gap semiconductor materials to better manage impact ionization thresholds.
Reference is now made to
Ordinarily, polycrystalline semiconductors have greatly reduced charge carrier mobilities due to the reduced mean free paths caused by the lattice dislocations encountered as the charge carrier attempts to navigate the grain boundary. However, maximum physical dimensions 123 in the range 20-50 nm are small enough to form quantum wells that induce quantization effects as each grain 122 of the polycrystalline semiconductor material 120 becomes a quantum dot within the bulk material when a chemically distinct material envelops the grain 122 at the grain boundaries 124,126. The quantum dot thereby produces a three-dimensional (3D) electron gas within each grain 122. Quantum tunneling mechanisms represent the fastest charge transfer mechanism across an energy barrier, occurring at femtosecond time periods, an additional preferred aspect of the present invention strengthens the energy barrier by optionally enveloping the semiconducting grains 122 with thin layers (2-10 nm thick, preferably 2-5 nm thick) of metallic grain boundary material 124 (
qϕB=q(ϕm−χ) (1)
where q is the electron charge, ϕm is the metal work function and χ is the semiconductor electron affinity. Conduction electrons injected into and contained within the quantized energy levels 138 will tunnel through the junction barriers (ϕB) 132A,132B,132C,132D at femtosecond transit speeds, which thereby makes very fast semiconductor switching speeds possible when these materials are configured in field effect transistor structures. The thin metallic grain boundary material 124 is a limitation in an FET-switched device as it will carry leakage currents that are undesirable in most applications. Therefore, it is preferable to form the polycrystalline semiconductor 121 that has electrically insulating or semi-insulating/semiconducting grain boundary material 126 enveloping the semiconductor grains 122 as depicted in
As discussed in greater detail below, thermodynamic and/or chemical incompatibility is required to phase separate the grain material from the grain boundary material while processing the polycrystalline grains. As shown in Tables I & II (
The principal advantage afforded by these polycrystalline semiconductors is that devices having arbitrarily thick conduction channels can be easily constructed in contrast to the prior art in which the primary conduction channels 6 are limited to 20-50 nm layer thicknesses as shown in
Since the modulated currents multilayer 2D-electron gas structures instructed by the prior art limit high-speed current transport to primary conduction channel(s) 6 that are 20-50 nm thick, forty (40) to one hundred (100) such layers would be required to transport equivalent currents in a single two (2) micron thick 3D-electron gas primary conduction channel 161 described by the present invention. The high-speed quantum dot field effect transistor may be integrated in any circuit using LCD methods, apparatus, and processes, including, but not limited to, power management devices or silicon carriers that are used in high-speed computing processes or radio applications.
Reference is now made to
A plasma annealing step is then used to render the amorphous layer 171 into a polycrystalline layer 173 that has uniform microstructure with grain sizes 174 ranging between 20-50 nm. Other thermal processing methods may be used to render the amorphous deposit into a polycrystalline state, but rapid thermal annealing process, and plasma annealing processes in particular, are preferred. The substrate 172 and deposit 171 may be pre-heated to temperatures in the range of 40° C. to 400° C. during the ionized plasma annealing step. Argon gas is the primary ballast used in the plasma annealing step, with additional gas additives consisting of nitrogen and/or carbon monoxide and carbon dioxide not exceeding 20% partial pressures. Total atmospheric pressures in the range of 1500 to 5000 mTorr, with power settings ranging from 50 W to 300 W for periods of 5 to 60 seconds are preferred for generating nanoscale polycrystalline semiconducting grains enveloped with a distinct phase grain boundary material.
It is desirable to select metallic species that will be driven towards the grain boundaries by thermodynamic processes during the annealing step to form metallic grain boundaries. In the early-stages of crystalline nucleation, cooperative forces will create crystalline fields that atomically organize the majority elements in the amorphous deposit 171 into its thermodynamically most favored crystalline phase. The cooperative forces will be driven by the majority chemical concentrations, causing chemically compatible elements to be drawn into the crystal nucleation process while expelling chemically incompatible elements to the grain boundaries. For example, if silicon is the majority chemical element, present in the deposit at levels exceeding 99.99 mol %, the crystalline fields that build during the nucleation process will favor the incorporation of elements that have similar charge and molecular orbital orientations, such as germanium. It is therefore desirable to select grain boundary materials from metallic elements that have incompatible charge and orbital characteristics to the semiconductor compound being formed within the grain, such as those shown in Tables I & II. Elements that are located in the columns of The Periodic Table furthest away from the column in which the semiconducting elements are drawn from satisfy this requirement. Therefore, metalorganic precursors to alkali metals or alkaline earth metals, in concentrations of 0.0001 to 0.5 mol %, are added to the liquid precursor solution used to form the amorphous deposit when it is desirable to form metallic grain boundaries 175 in the polycrystalline deposit 173. Alkali metals are preferred over alkaline earth metals. Halogenated metalorganic precursors to alkali metals, alkaline earth metals, or transition metals are added to the liquid precursor solution when it is desirable to form insulating grain boundaries 176 that comprise any of the I-VII grain boundary materials depicted in Tables I and II in the polycrystalline deposit 173. Precursor molecules 177 essentially “carry” a metallic element 178 attached to an organic molecule that decomposes on the surface where the metallic element 178 is eventually deposited. Halogenated precursors will substitute one or more of the hydrogen elements 179 in the organic molecule with a halide element 180 from the group: fluorine, chlorine, iodine, or bromine. Halogenated alkali or alkaline earth metal precursors allows the elemental constituents of insulating compounds, comprising either a singular alkali or alkaline earth halide or a plurality of alkali or alkaline earth halides, to be transported to the deposition surface and integrated into the amorphous deposit and driven into the grain boundary regions 176 in a subsequent plasma annealing step. As explained in greater detail within application '405, silicon carbide or aluminum nitride material phases can be introduced to the amorphous deposit 171 by forming a colloidal suspension of liquid metalorganic precursors and silicon carbide or aluminum nitride nanoparticles. These nanoparticle carbide and nitride phases will migrate to the grain boundaries during plasma annealing when their molar concentrations are held between 0.0001 mol % and 0.75 mol %.
A specific advantage to the present invention is its ability to use the 3D electron gases generated by the nanoscale polycrystalline semiconductors to increase the carrier mobility within a specific layer or in a plurality of layers, which is not possible under the prior art. In the prior art described by Phillips '292, a 2D electron gas is generated by forming quantum wells by sandwiching a layer of low band gap semiconductor, such as indium antimonide (InSb, Egap=0.17 eV), between epitaxial layers of higher band gap semiconductors. (See
As mentioned above, tunneling processes represent the fastest electron transport mechanism. Tunneling processes are possible between adjacent quantum wells (not shown), but not within a low band gap semiconductor layer since there are no energy barriers within layer forming the bottom of the well. (Adjacent quantum wells can be visualized by imagining a plurality of multilayer structures in the vertical direction of
As mentioned above, the 3D quantum wells of the present invention interject an energy barrier at the boundary of every grain. Therefore, the mean free path of any conduction electron is limited to the nanoscale dimension of the grain (20 nm to 50 nm). The drifting electron will then encounter a thin (2 nm to 10 nm) energy barrier through which it will tunnel. The combination of reduced mean free path (reduced impact ionization) and tunneling currents in the direction or primary drift currents allows all types of semiconductor materials to support fast transport processes in any direction, without the restriction of limiting the modulated current to a 20-50 nm layer.
This advantage is particularly important in power FET devices, opto-electronic or photonic devices as any of the layers 161,162,163,164 (see
A final embodiment is depicted in
It is readily understood that the quantum well technology and manufacturing methods described herein may be easily applied to any other form of quantum well devices, including but not limited to multiplexers, signal encoders, and sensors. It is further readily understood that the devices described above embody methods of manufacture and methods of operation which are also new and non-obvious with respect to the prior art.
The present invention is illustratively described above in reference to the disclosed embodiments. Various modifications and changes may be made to the disclosed embodiments by persons skilled in the art without departing from the scope of the present invention as defined in the appended claims.
This application claims priority from U.S. provisional application 61/409,846 entitled “QUANTUM DOT FIELD EFFECT TRANSISTOR IN A FULLY INTEGRATED SILICON CARRIER AND METHOD OF MANUFACTURE” filed Nov. 3, 2010.
Number | Name | Date | Kind |
---|---|---|---|
2283925 | Harvey | May 1942 | A |
2886529 | Louis | May 1959 | A |
3574114 | Monforte | Apr 1971 | A |
3614554 | Shield et al. | Oct 1971 | A |
3983077 | Fuller et al. | Sep 1976 | A |
4400683 | Eda et al. | Aug 1983 | A |
4455545 | Shelly | Jun 1984 | A |
4523170 | Huth, III | Jun 1985 | A |
4646038 | Wanat | Feb 1987 | A |
4759120 | Bernstein | Jul 1988 | A |
4859492 | Rogers, Jr. et al. | Aug 1989 | A |
4880770 | Mir et al. | Nov 1989 | A |
4967201 | Rich, III | Oct 1990 | A |
5084749 | Losee et al. | Jan 1992 | A |
5130675 | Sugawara | Jul 1992 | A |
5139999 | Gordon et al. | Aug 1992 | A |
5154973 | Imagawa et al. | Oct 1992 | A |
5198824 | Poradish | Mar 1993 | A |
5217754 | Santiago-Aviles et al. | Jun 1993 | A |
5219377 | Poradish | Jun 1993 | A |
5263198 | Geddes et al. | Nov 1993 | A |
5272485 | Mason et al. | Dec 1993 | A |
5403797 | Ohtani et al. | Apr 1995 | A |
5427988 | Sengupta et al. | Jun 1995 | A |
5456945 | McMillan et al. | Oct 1995 | A |
5478610 | Desu et al. | Dec 1995 | A |
5503912 | Setoyama et al. | Apr 1996 | A |
5513382 | Agahi-Kesheh et al. | Apr 1996 | A |
5535445 | Gunton | Jul 1996 | A |
5540772 | McMillan et al. | Jul 1996 | A |
5543773 | Evans et al. | Aug 1996 | A |
5584053 | Kommrusch et al. | Dec 1996 | A |
5590387 | Schmidt et al. | Dec 1996 | A |
5614252 | McMillan et al. | Mar 1997 | A |
5625365 | Tom et al. | Apr 1997 | A |
5635433 | Sengupta | Jun 1997 | A |
5656561 | Rogers et al. | Aug 1997 | A |
5707459 | Itoyama et al. | Jan 1998 | A |
5707715 | deRochemont et al. | Jan 1998 | A |
5747870 | Pedder | May 1998 | A |
5759923 | McMillan et al. | Jun 1998 | A |
5764189 | Lohninger | Jun 1998 | A |
5771567 | Pierce et al. | Jun 1998 | A |
5854608 | Leisten | Dec 1998 | A |
5859621 | Leisten | Jan 1999 | A |
5889459 | Hattori et al. | Mar 1999 | A |
5892489 | Kanba et al. | Apr 1999 | A |
5903421 | Furutani et al. | May 1999 | A |
5933121 | Rainhart et al. | Aug 1999 | A |
5945963 | Leisten | Aug 1999 | A |
6023251 | Koo et al. | Feb 2000 | A |
6027826 | deRochemont et al. | Feb 2000 | A |
6028568 | Asakura et al. | Feb 2000 | A |
6031445 | Marty et al. | Feb 2000 | A |
6040805 | Huynh et al. | Mar 2000 | A |
6046707 | Gaughan et al. | Apr 2000 | A |
6052040 | Hino | Apr 2000 | A |
6111544 | Dakeya et al. | Aug 2000 | A |
6130471 | Boles | Oct 2000 | A |
6143432 | deRochemont et al. | Nov 2000 | A |
6154176 | Fathy et al. | Nov 2000 | A |
6176004 | Rainhart et al. | Jan 2001 | B1 |
6181297 | Leisten | Jan 2001 | B1 |
6188368 | Koriyama et al. | Feb 2001 | B1 |
6195049 | Kim et al. | Feb 2001 | B1 |
6204203 | Narwankar et al. | Mar 2001 | B1 |
6208843 | Huang et al. | Mar 2001 | B1 |
6222489 | Tsuru et al. | Apr 2001 | B1 |
6227188 | Tankala et al. | May 2001 | B1 |
6266020 | Chang | Jul 2001 | B1 |
6271803 | Watanabe et al. | Aug 2001 | B1 |
6300894 | Lynch et al. | Oct 2001 | B1 |
6320547 | Fathy et al. | Nov 2001 | B1 |
6323549 | deRochemont et al. | Nov 2001 | B1 |
6492949 | Breglia et al. | Dec 2002 | B1 |
6496149 | Birnbaum et al. | Dec 2002 | B1 |
6501415 | Viana et al. | Dec 2002 | B1 |
6541820 | Bol | Apr 2003 | B1 |
6552693 | Leisten | Apr 2003 | B1 |
6559735 | Hoang et al. | May 2003 | B1 |
6583699 | Yokoyama | Jun 2003 | B2 |
6605151 | Wessels et al. | Aug 2003 | B1 |
6611419 | Chakravorty | Aug 2003 | B1 |
6620750 | Kim et al. | Sep 2003 | B2 |
6639556 | Baba | Oct 2003 | B2 |
6642908 | Pleva et al. | Nov 2003 | B2 |
6650303 | Kim et al. | Nov 2003 | B2 |
6670497 | Tashino et al. | Dec 2003 | B2 |
6680700 | Hilgers | Jan 2004 | B2 |
6683576 | Achim | Jan 2004 | B2 |
6686406 | Tomomatsu et al. | Feb 2004 | B2 |
6690336 | Leisten et al. | Feb 2004 | B1 |
6697605 | Atokawa et al. | Feb 2004 | B1 |
6742249 | deRochemont et al. | Jun 2004 | B2 |
6742611 | Illerhaus et al. | Jun 2004 | B1 |
6743744 | Kim et al. | Jun 2004 | B1 |
6762237 | Glatkowski et al. | Jul 2004 | B2 |
6791496 | Killen et al. | Sep 2004 | B1 |
6864848 | Sievenpiper | Mar 2005 | B2 |
6906674 | McKinzie, III et al. | Jun 2005 | B2 |
6919119 | Kalkan et al. | Jul 2005 | B2 |
6940087 | Komoda et al. | Sep 2005 | B2 |
7002436 | Ma et al. | Feb 2006 | B2 |
7047637 | deRochemont et al. | May 2006 | B2 |
7116949 | Irie et al. | Oct 2006 | B2 |
7230316 | Yamazaki et al. | Jun 2007 | B2 |
7405698 | deRochemont | Jul 2008 | B2 |
7456449 | Fujiwara et al. | Nov 2008 | B2 |
7522124 | Smith et al. | Apr 2009 | B2 |
7564887 | Wang et al. | Jul 2009 | B2 |
7572313 | Palanisamy et al. | Aug 2009 | B2 |
7595623 | Bennett | Sep 2009 | B2 |
7652901 | Kirchmeier et al. | Jan 2010 | B2 |
7679102 | Chik et al. | Mar 2010 | B2 |
7763917 | deRochemont | Jul 2010 | B2 |
7892659 | Oboodi et al. | Feb 2011 | B2 |
7917311 | Finkel et al. | Mar 2011 | B2 |
7968273 | Chen | Jun 2011 | B2 |
8066805 | Zurcher et al. | Nov 2011 | B2 |
8069690 | DeSantolo et al. | Dec 2011 | B2 |
8069935 | Miess et al. | Dec 2011 | B1 |
8134177 | Murooka | Mar 2012 | B2 |
8178457 | de Rochemont | May 2012 | B2 |
8334154 | Fuertes et al. | Dec 2012 | B2 |
8350657 | de Rochemont | Jan 2013 | B2 |
8354294 | de Rochemont et al. | Jan 2013 | B2 |
8715839 | de Rochemont | May 2014 | B2 |
8759670 | Furusawa | Jun 2014 | B2 |
20010023779 | Sugaya et al. | Sep 2001 | A1 |
20010027119 | Furutani et al. | Oct 2001 | A1 |
20010048969 | Constantino et al. | Dec 2001 | A1 |
20020039667 | Takaya et al. | Apr 2002 | A1 |
20020047768 | Duffy | Apr 2002 | A1 |
20020070983 | Kozub et al. | Jun 2002 | A1 |
20020092472 | Hayashi et al. | Jul 2002 | A1 |
20020110004 | Parks | Aug 2002 | A1 |
20020190818 | Endou et al. | Dec 2002 | A1 |
20030002045 | Nemat-Nasser et al. | Jan 2003 | A1 |
20030034124 | Sugaya et al. | Feb 2003 | A1 |
20030073565 | Ellis et al. | Apr 2003 | A1 |
20030080325 | Uchiyama et al. | May 2003 | A1 |
20030107455 | Imanaka et al. | Jun 2003 | A1 |
20030111714 | Bates et al. | Jun 2003 | A1 |
20030122647 | Ou | Jul 2003 | A1 |
20030148024 | Kodas et al. | Aug 2003 | A1 |
20030161959 | Kodas et al. | Aug 2003 | A1 |
20030170436 | Sumi et al. | Sep 2003 | A1 |
20030186636 | Akyuz et al. | Oct 2003 | A1 |
20030221621 | Pokharna et al. | Dec 2003 | A1 |
20040000964 | Killen et al. | Jan 2004 | A1 |
20040000966 | Killen et al. | Jan 2004 | A1 |
20040000970 | Killen et al. | Jan 2004 | A1 |
20040000972 | Killen et al. | Jan 2004 | A1 |
20040000975 | Killen et al. | Jan 2004 | A1 |
20040000976 | Killen et al. | Jan 2004 | A1 |
20040001024 | Killen et al. | Jan 2004 | A1 |
20040001026 | Killen et al. | Jan 2004 | A1 |
20040001027 | Killen et al. | Jan 2004 | A1 |
20040001028 | Killen et al. | Jan 2004 | A1 |
20040012081 | Kwon | Jan 2004 | A1 |
20040033654 | Yamagata | Feb 2004 | A1 |
20040070334 | Buckley | Apr 2004 | A1 |
20040070915 | Nagai et al. | Apr 2004 | A1 |
20040084080 | Sager et al. | May 2004 | A1 |
20040113738 | Ahn et al. | Jun 2004 | A1 |
20040118448 | Scher et al. | Jun 2004 | A1 |
20040145874 | Pinel | Jul 2004 | A1 |
20040189528 | Killen et al. | Sep 2004 | A1 |
20040195575 | Komoda | Oct 2004 | A1 |
20050127389 | Fujiwara | Jun 2005 | A1 |
20060086994 | Viefers et al. | Apr 2006 | A1 |
20060093860 | Schuisky et al. | May 2006 | A1 |
20060134491 | Hilchenko et al. | Jun 2006 | A1 |
20060189104 | Yan | Aug 2006 | A1 |
20070166453 | Van Duren et al. | Jul 2007 | A1 |
20070259768 | Kear et al. | Nov 2007 | A1 |
20100055492 | Barsoum et al. | Mar 2010 | A1 |
20100155786 | Heald | Jun 2010 | A1 |
20110049394 | De Rochemont | Mar 2011 | A1 |
20110065224 | Bollman et al. | Mar 2011 | A1 |
Number | Date | Country |
---|---|---|
1450580 | Oct 2003 | CN |
0026056 | Apr 1981 | EP |
0939451 | Jan 1999 | EP |
1376759 | Feb 2004 | EP |
1125897 | Sep 1968 | GB |
2007143197 | Dec 2007 | WO |
2010048580 | Apr 2010 | WO |
Entry |
---|
US 5,888,459 A, 03/1999, McMillan et al. (withdrawn) |
International Search Report and Written Opinion in corresponding PCT application No. PCT/US11/059236, dated Feb. 21, 2014. |
Extended European Search Report in corresponding European Application No. 11838840.4, dated May 16, 2017. |
Andrenko et al. “EM Analysis of PBG Substrate Microstrip Circuits for Integrated Transmitter Front End” MMET Proceedings 295-297 (2000). |
Bardi et al. “Plane Wave Scattering From Frequency-Selective Surfaces by the Finite-Element Method” IEEE Transactions on Magnetics 38(2):641-644 (2002). |
Chappell et al. “Composite Metamaterial Systems for Two-Dimensional Periodic Structures” IEEE 384-387 (2002). |
Cheng et al. “Preparation and Characterization of (Ba, Sr) TiO3 thin films using interdigital electrodes” Microelectronic Engineering 66:872-879 (2003). |
Clavijo et al. “Design Methodology for Sievenpiper High-Impedance Surfaces: An Artificial Magnetic Conductor for Positive Gain Electrically Small Antennas” IEEE Transactions on Antennas and Propagation 51(10):2678-2690 (2003). |
Diaz et al. “Magnetic Loading of Artificial Magnetic Conductors for Bandwidth Enhancement” IEEE 431-434 (2003). |
Hansen “Effects of a High-Impedance Screen on a Dipole Antenna” IEEE Antennas and Wireless Propagation Letters 1:46-49 (2002). |
Joshi et al. “Processing and Characterization of Pure and Doped Ba0.6Sr0.4TiO3 Thin Films for Tunable Microwave Applications” Mat. Res. Soc. Symp. Proc. 656E: DD4.9.1-DD4.9.6 (2001). |
Kern et al. “Active Negative Impedance Loaded EBG Structures for the Realization of Ultra-Wideband Artificial Magnetic Conductors” IEEE 427-430 (2003). |
Kern et al. “The Synthesis of Metamaterial Ferrites for RF Applications Using Electromagnetic Bandgap Structures” IEEE 497-500 (2003). |
Kern et al. “Ultra-thin Electromagnetic Bandgap Absorbers Synthesized via Genetic Algorithms” IEEE 1119-1122 (2003). |
Khun et al., “Characterization of Novel Mono- and Bifacially Active Semi-Transparent Crystalline Silicon Solar Cells” IEEE Transactions on Electron Devices, 46(10): 2013-2017 (1999). |
Kretly et al. “The Influence of the Height Variation on the Frequency Bandgap in an AMC Articial Magnetic Conductor for Wireless Applications: an EM Experimental Design Approach” Proceedings SBMO/IEEE MTT-S IMOC 219-223 (2003). |
Lee et al. “Investigation of Electromagnetic Bandgap (EBG) Structures for Antenna Pattern Control” IEEE 1115-1118 (2003). |
McKinzie III et al. “Mitigation of Multipath Through the Use of an Artificial Magnetic Conductor for Precision CPS Surveying Antennas” IEEE 640-643 (2002). |
McKinzie et al. “A Multi-Band Artificial Magnetic Conductor Comprised of Multiple FSS Layers” IEEE 423-426 (2003). |
Monorchio et al. “Synthesis of Artificial Magnetic Conductors by Using Multilayered Frequency Selective Surfaces” IEEE Antennas and Wireless Propagation Letters 1:196-199 (2002). |
Mosallaei et al. “Periodic Bandgap and Effective Dielectric Materials in Electromagnetics: Characterization and Applications in Nanocavities and Waveguides” IEEE Transactions on Antennas and Propagation 51(3):549-563 (2003). |
Pontes et al. “Study of the dielectric and ferroelectric properties of chemically processed BaxSr1-xTiO3 thin films”Thin Solid Films 386(1): 91-98 (2001). |
Rogers et al. “AMCs Comprised of Interdigital Capacitor FSS Layers Enable Lower Cost Applications” IEEE 411-414 (2003). |
Rogers et al. “An AMC-Based 802.111a/b Antenna for Laptop Computers” IEEE 10-13 (2003). |
Sievenpiper et al. “Two-Dimensional Beam Steering Using an Electrically Tunable Impedance Surface” IEEE Transactions on Antennas and Propagation 51(10):2713-2722 (2003). |
Sun et al. “Efficiency of Various Photonic Bandgap (PBG) Structures” 3RD Int'l Conf. on Microwave and Millimeter Wave Technology Proceedings 1055-1058 (2002). |
Tsunemine et al. “Pt/BaxSr(1-x)TiO3/Pt Capacitor Technology for 0.15μm Embedded Dynamic Random Access Memory” Jap. J. Appl. Phys. 43(5A):2457-2461 (2004). |
Vest “Metallo-organic decomposition (MOD) processing of ferroelectric and electro-optic films: A review” Ferroelectrics 102: 53-68 (1990). |
Viviani et al. “Positive Temperature Coefficient of Electrical Resistivity below 150k of Barium Strontium Titanate” J. Amer. Ceram. Soc. 87: 756-758 (2004). |
Weily et al. “Antennas Based on 2-D and 3-D Electromagnetic Bandgap Materials” IEEE 847-850 (2003). |
Yang et al. “Surface Waves of Printed Antennas on Planar Artificial Periodic Dielectric Structures” IEEE Transactions on Antennas and Propagation 49(3):444-450 (2001). |
Zhang et al. “Planar Artificial Magnetic Conductors and Patch Antennas.” IEEE Transactions on Antennas and Propagation 51(10):2704-2712 (2001). |
Ziroff et al. “A Novel Approach for LTCC Packaging Using a PBG Structure for Shielding and Package Mode Suppression” 33rd European Microwave Conference—Munich 419-422 (2003). |
Number | Date | Country | |
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20170229302 A1 | Aug 2017 | US |
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61409846 | Nov 2010 | US |
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Parent | 14839364 | Aug 2015 | US |
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Child | 14839364 | US |