This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2007-0110814 filed on Nov. 1, 2007, the entire contents of which are hereby incorporated by reference.
The present invention relates to a semiconductor chip package and a method of forming the same. More particularly the present invention relates to a semiconductor chip package having a molding layer disposed on a backside surface, side surfaces and an active surface of a semiconductor chip and a method of forming the same.
Some embodiments of the present invention provide a semiconductor chip package having a molding layer. The semiconductor chip package includes a semiconductor chip, a plurality of external connection terminals, and the molding layer. The semiconductor chip comprises a backside surface, side surfaces, and an active surface having a plurality of chip pads disposed thereon. The molding layer substantially covers the backside surface, the side surfaces, and the active surface of the semiconductor chip and defines at least one opening exposing a portion of the backside surface of the semiconductor chip.
The semiconductor chip package according to some embodiments of the present invention has improved resistance to cracking and chipping. Further, because the semiconductor chip package includes the molding layer on all six sides of the semiconductor chip, underfill and back-side protection processes are not needed. Therefore, the process for manufacturing the semiconductor chip package can be simpler and less costly than conventional methods.
The above and other features and advantages of the present invention will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings, in which:
The present invention is described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Example embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the shapes of the illustrations accordingly, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes of components illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the components illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a component of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
As shown in
As described below, the opening 156 may be located at a substantially center portion of the semiconductor chip 110. Alternatively, the opening 156 may be located at one or more center edge portions of the semiconductor chip 110 as discussed with respect to
A portion of the molding layer 154 that covers the active surface 112 exposes a portion of the external connection terminals 116 and forms a concave surface between the external connection terminals 116 and below a top of the external connection terminals 116 such that the external connection terminals can be firmly fixed to the semiconductor chip 110. In other words, the molding layer 154 can provide structural support to the joints between the external connection terminals 116 and the chip pads 114, thereby improving the reliability of the joints. Also, because all of the main surfaces, including side surfaces, of the semiconductor chip 110 are covered with the molding layer 154, a costly BSP layer is not required according to some embodiments of the present invention.
According to one embodiment, the opening 156 may be filled with a thermally conductive material (not illustrated), such as copper or silver, can be disposed within the opening 156 to improve the heat dissipation from the semiconductor package 100 when it is in actual use.
Additionally, an adhesive layer, i.e., an epoxy type adhesive, can be disposed between the thermally conductive material and the exposed chip 110 for electrical isolation therebetween.
Referring to
Referring to
Referring to
The back surfaces 111 of the semiconductor chips 110 face toward the main mold 130 for a compression molding process to be performed at a subsequent step.
Referring to
A release tape 150 is also provided over the carrier tape 120 between the subsidiary mold 140 and the main mold 130. The release tape 150 may be supplied from a tape roller (not illustrated) located on both sides of the molds 130, 140. The thickness of the release tape 150 is in the range of about 50 to about 400 μm. The release tape 150 may be PolyTetraFluoroEthylene (PTFE) or Ethylene TetraFluoroEthylene copolymer (ETFE). The release tape 150 may be formed of a material that does not easily transform during the compression molding process.
In addition, a molding material 152 is dispensed on the semiconductor chips 110 and the carrier tape 120 at room temperature. The molding material 152 is located between the release tape 150 and the semiconductor chip 110 having external connection terminals 116. In one embodiment, the molding material 152 may be dispensed between the release tape 150 and the semiconductor chip 110 after the release tape 150 is conformally attached to the molding part 142 of the subsidiary mold 140. The molding material 152 may be an epoxy molding compound (EMC). The EMC may be in the form of a powder or liquid. The EMC may include about 50 to about 90 wt % silica and have a coefficient of thermal expansion of about 50 ppm/° C. below the glass transition temperature. The molding may also be formed of a silicone material.
Then, the molds 130, 140 may be heated to a temperature range of about 100° C. to about 200° C., for example about 175° C., for more than 2 seconds such that the viscosity of the molding material 152 is properly reduced. For example, although not fixed, the viscosity of the molding material 152 may be about 20 to 70 poise or higher and the molding material 152 may have a spiral flow rate of about 40 to about 140 inches during the molding process.
The heating process is performed to transform the powder into a liquid form if the power is employed in the molding process.
Also, during this heating process, the molding part 142 is exhausted (evacuated) by vacuum at a pressure of about 50 Torr within the molding part 142 such that a molding layer 154 shown in
According to one aspect of the present invention, the molds 130, 140 may be formed of a material having a coefficient of thermal expansion different from that of the molding material 152 such that the molded semiconductor package shown in, for example,
Referring to
During the compression molding process, the main mold 130 and the subsidiary mold 140 are compressed against each other. As a result, the release tape 150 and the semiconductor chip 110 between the molds 130, 140 are also compressed against each other with the molding material 152 between them.
As shown in
During the compression molding process, the carrier tape 120 is conformally adhered to the bottom surface 132 of the main mold 130 due to the pressure exerted by the molding material 152 filling the molding space 136. Also, the release tape 150 may be adhered to the subsidiary mold 140 due to the compression molding process.
Further, the external connection terminals 116 can protrude above a top surface of the molding layer 154. In other words, an upper portion of the external connection terminals are exposed from the molding layer 154.
In one embodiment, the molding layer 154 forms a concave top surface between the external connection terminals 116 and below a top of the external connection terminals 116. The height of the concave top surface can be substantially the same or less than a height of the external connection terminals 116, but higher than half the height of the external connection terminals 116. As a result, without additional processing steps, e.g., a coating process to provide a support at the joints of the external connection terminals 116 and the chip pads 114, the external connection terminals 116 can be firmly secured to the semiconductor chips 110.
As a result, an underfill process may not be required unlike the prior art. Consequently, the board-level reliability can be improved without the costly underfill process and the overall assembly time can be significantly reduced, thereby reducing the overall manufacturing costs.
After forming the molding layer 154, an additional curing step at greater than 100° C. may be performed to improve the adhesion between the semiconductor chips 110 and the molding layer 154 and to increase the integrity of the molding layer 154.
The main mold 130 and the subsidiary mold 140 are then separated from the semiconductor chips 110. Because the carrier tape 120 and the release tape 150 are adhered to the main mold 130 and subsidiary mold 140, respectively, the carrier tape 120 and the release tape 150 are also removed from the semiconductor chips 110 when the main mold 130 and the subsidiary mold 140 are separated. The area of the backside surface 111 overlying the projecting portion 134 will later define an opening 156 when the molds 130, 140 are separated.
The manufacturing of the semiconductor package 100 shown in
The semiconductor chip packages 100 manufactured according to the method of this embodiment include a molding layer 154 on all six sides of the semiconductor chips 110. Thus, the semiconductor chip packages 100 are less susceptible to damage from the external environment and failure during testing.
Thus, the chipping or cracking problems in the prior art can be substantially reduced. Also, no BSP layer is required. Further, because the above processes are performed on selected semiconductor chips, the above processes need only be performed on semiconductor chips that are found to pass a testing step. Therefore, the manufacturing cost is reduced as compared to the conventional BSP process where both good and bad semiconductor chips are processed. Because EMC is typically less expensive than BSP materials, the cost of the process according to embodiments of the present invention can be reduced as compared to the conventional process.
A person of ordinary skill in the art will appreciate that the thickness of the molding layer 154 on the backside surface 111 of the semiconductor chips 110 can be adjusted by controlling the depth of the molding space 136 and/or the thickness of the carrier tape 120. Therefore, according to some embodiments of the present invention, the thickness of the semiconductor package 110 can be easily adjusted, which is not available in the conventional process because the BSP tape typically has a pre-determined thickness.
Referring to
Referring to
In one aspect, the exposed portion of the side surface 113 of the semiconductor chip 110 and the exposed portion of the backside surface 111 forms a step within the at least one opening 256.
In one aspect, substantial portions of the edges of the semiconductor chip 110 are covered by the molding layer 254 such that the edges are protected from chipping or external impacts, unlike in the prior art. The molding layer 254 exposes a portion of the external connection terminals 116 and also has a concave top surface between the external connection terminals 116 and below a top of the external connection terminals 116 such that the external connection terminals 116 can be firmly fixed to the semiconductor chip 110.
Referring to
In the following discussion of the embodiment of
Referring to
Referring to
The projecting portion 234 of the main mold 230 may be arranged on at least two edge portions of the semiconductor chips 110 and preferably, the projecting portion 234 of the main mold 230 is arranged on four edge portions of the semiconductor chips 110. In one embodiment, each of the projecting portions 234 of the main mold 230 is configured to support a pair of adjacent semiconductor chips 110.
The main mold 230 includes voids or molding spaces 236 disposed under the semiconductor chips 110.
Referring to
The molding material 252 may be an epoxy molding compound (EMC). The EMC may be in the form of a powder or liquid. The EMC may include about 50 to about 90 wt % silica and have a coefficient of thermal expansion of about 50 ppm/° C. below the glass transition temperature.
A release tape 150 is also provided between the subsidiary mold 240 and the main mold 230. The release tape 150 may be supplied from a tape roller (not illustrated) located on both sides of the molds 230, 240. The thickness of the release tape 150 is in the range of about 50 to about 400 μm. The release tape 150 may be PolyTetraFluoroEthylene (PTFE) or Ethylene TetraFluoroEthylene copolymer (ETFE). The release tape 150 may be formed of a material that does not easily transform during the compression molding process.
In addition, a molding material 252 is dispensed on the semiconductor chips 110 having external connection terminals 116 at room temperature. The molding material 252 is located between the release tape 150 and the main mold 230. In one embodiment, the molding material 252 may be dispensed between the release tape 150 and the semiconductor chip 110 after the release tape 150 is conformally attached to the molding part 242 of the subsidiary mold 240.
The molding material 252 may be an epoxy molding compound (EMC). The EMC may be in the form of a powder or liquid. The EMC may include about 50 to about 90 wt % silica and have a coefficient of thermal expansion of about 50 ppm/° C. below the glass transition temperature.
Then, the molds 230, 240 may be heated to a temperature range of about 100° C. to about 200° C., for example about 175° C., for more than 2 seconds such that the viscosity of the molding material 252 is properly reduced for the compression molding process. For example, although not fixed, the viscosity of the molding material 152 may be about 20 to 70 poise or higher and the molding material 152 may have a spiral flow rate of about 40 to about 140 inches during the molding process.
The heating process is performed to transform the powder into a liquid form if the power is employed in the molding process.
Also, during this heating process, the molding part 242 is exhausted (evacuated) by vacuum at a pressure of about 50 Torr within the molding part 242 such that a molding layer 254 shown in
According to one aspect of the present invention, the molds 230, 240 may be formed of a material having a coefficient of thermal expansion different from that of the molding material 252 such that the molded semiconductor package shown in, for example,
Referring to
The main mold 230 and the subsidiary mold 240 are then separated from the semiconductor chips 110. Because the release tape 250 is adhered to the subsidiary mold 240, the release tape 250 is removed from the semiconductor chips 110 when the main mold 230 and the subsidiary mold 240 are separated. The area of the backside surface 111 overlying the projecting portion 234 and the portion of the side surface 113 in contact with the projecting portion 234 will later define the opening 256 when the molds 230, 240 are separated.
Then, the semiconductor chips 110 are singulated into individual semiconductor chip packages 200 shown in
Thus, with embodiments of the invention discussed above, the chipping or cracking problems in the prior art can be substantially reduced. Also, no expensive BSP layer is required. Further, because the above processes are performed on selected semiconductor chips, the above processes need only be performed on semiconductor chips that are found to pass a testing step, e.g., a known-good die (KGD). Therefore, the manufacturing cost is reduced as compared to the conventional BSP process where both good and bad semiconductor chips are processed. Because EMC is typically less expensive than BSP materials, the cost of the process according to embodiments of the present invention can be reduced as compared to the conventional process.
Referring to
Referring to
According to some embodiments of the present invention, a semiconductor chip package includes a molding layer on all sides, e.g., six sides, of a semiconductor chip. Thus, the semiconductor chip package is less susceptible to cracking and chipping. Further, underfill and back-side protection (BSP) processes may not be needed. Therefore, the process for manufacturing the semiconductor chip package can be simplified and the expense of the process can be reduced. Also, because the molding layer surrounds joints between the chip pads and the external connection terminals, the joint reliability can be improved without the underfill process.
A person of ordinary skill in the art will appreciate that a semiconductor chip can have more or fewer than six sides and that the above-described processes can be applied to such semiconductor chips, within the spirit and scope of the present invention.
According to some embodiments of the present invention, a molding layer is formed on both the front and back sides of a semiconductor chip substantially simultaneously in a single process. Therefore, the processing time and expense is reduced as compared to conventional processes. Further, a minimum amount of the semiconductor chip is exposed outside of the molding layer, so that the occurrence of chipping of the semiconductor chip (at a subsequent testing step for example) can be reduced.
Lastly, embodiments and concepts of the present invention can be readily applied to semiconductor packages such as a wafer level package (WLP). However, concepts of the present invention can be also useful to other similar conventional semiconductor packages within the spirit and scope of the present invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Various operations will be described as multiple discrete steps performed in a manner that is most helpful in understanding the invention. However, the order in which the steps are described does not imply that the operations are order-dependent or that the order that steps are performed must be the order in which the steps are presented.
The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few example embodiments of the present invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. The present invention is defined by the following claims, with equivalents of the claims to be included therein.
Number | Date | Country | Kind |
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2007-0110814 | Nov 2007 | KR | national |