TREA

Semiconductor deposition method and device

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Information

  • Patent Grant
  • 4707216
  • Patent Number
    4,707,216
  • Date Filed
    Friday, January 24, 1986
    39 years ago
  • Date Issued
    Tuesday, November 17, 1987
    37 years ago
Information
Abstract
Description
Claims
  • 1. A method of forming a layer of semiconductor material of improved quality, comprising the steps of:
  • providing a single crystalline silicon or germanium substrate having a {100} crystallographic surface tilted in the <001> direction; and
  • expitaxially depositing a different single crystalline semiconductor material over said surface to obtain a layer of said semiconductor material.
  • 2. The method as defined by claim 1, wherein said different single crystalline semiconductor material is a III-V semiconductor.
  • 3. The method as defined by claim 1, wherein said epitaxial depositing step is performed by molecular beam epitaxy.
  • 4. The method as defined by claim 2, wherein said epitaxial depositing step is performed by molecular beam epitaxy.
  • 5. A method of forming a layer of gallium arsenide of improved quality, comprising the steps of:
  • providing a single crystalline silicon substrate having a {100} crystallographic surface tilted by at least 2.29 degrees in the <001> direction;
  • epitaxially depositing an arsenic prelayer on said surface; and
  • epitaxially depositing gallium arsenide over said arsenic prelayer to obtain a layer of gallium arsenide.
  • 6. The method as defined by claim 5, further comprising the steps of epitaxially depositing intervening strained layers of III-V semiconductor material between said arsenic prelayer and said layer of gallium arsenide.
  • 7. The method as defined by claim 5, wherein said epitaxial depositing steps are performed by molecular beam epitaxy.
  • 8. The method as defined by claim 6, wherein said epitaxial depositing steps are performed by molecular beam epitaxy.
  • 9. The method as defined by claim 1, wherein said substrate is silicon, and said different single cyrstalline semiconductor material is gallium arsenide.
Foreign Referenced Citations (2)
Number Date Country
0022320 Feb 1984 JPX
0022319 Feb 1984 JPX
Non-Patent Literature Citations (20)
Entry
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Fischer, R., T. Henderson, J. Klem, W. T. Masselink, W. Kopp, H. Morkoc, and C. W. Litton, "Characteristics of GaAs/AlGaAs MODFETs Grown Directly on (100) Silicon", Electronics Letters 20 (22), Oct. 25, 1984, 945-947.
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Mazur, J. H., J. Washburn, T. Henderson, J. Klem, W. T. Masselink, R. Fischer, and H. Morkoc, "TEM Investigation of Polar-on-Nonpolar Epitaxy: GaAs-AlGaAs on (100) Ge", Presented at the Materials Research Society Meeting, Boston, MA, Nov. 26-30, 1984.
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Mazur, J. H., J. Washburn, T. H
This invention was made with Government support under Contract F49620-83-K-0021 awarded by the United States Air Force. The Government has certain rights in this invention.