Patent Application
20120322272
The present invention relates to a semiconductor device having a stress film over field-effect transistors and a method for fabricating the semiconductor device.
In order to increase the performance of semiconductor devices, the structures of transistors have been miniaturized. However, it is becoming difficult: to improve the speeds of operation of transistors only by miniaturization of the structures of transistors because the minimum feature sizes (for example the minimum gate lengths) that are now required have reached the order of the wavelength of light and driving voltage decreases with decreasing feature size.
Under these circumstances, it has generally found that the mobility of electrons (or holes) in silicon crystals is changed by applying a strain to the silicon crystals. The property is being widely used to improve the speeds of operation of transistors. For example, the carrier mobility of field-effect transistors is improved by applying a strain to silicon crystals in channel regions by stress films formed on a silicon substrate (Patent Document 1).
Patent Document 1 discloses that two types of stress films covering field-effect transistors are formed, which apply tensile stress and compressive stress on the silicon substrate. The two types of stress films apply tensile stress to the channel region of an n-channel transistor and compressive stress to the channel region of a p-type transistor.
Patent Document 1: Japanese Patent Laid-Open No. 2005-57301
Today, stress films that apply tensile stress to channel regions are provided by depositing a material such as a silicon nitride and then exposing the silicon nitride to ultraviolet (UV) light, for example. When the film deposited by the process is shrunk, the following problem may occur.
A surface may be formed in the silicon nitride film 60a formed as described above in a region between adjacent gate electrodes 15a, 15b where the portions of silicon nitride film 60a grown from the sidewalls of the adjacent gate electrodes join together (the surface will be referred to as discontinuous surface hereinafter). When subsequently the silicon nitride film 60a is shrunk by UV exposure, the silicon nitride film 60 at the discontinuous surface may break as shown in
Usually p-channel transistors are also formed on the same semiconductor substrate. The hole mobility of a p-channel transistor decreases when a tensile stress is applied to its channel region. Therefore, an additional step of selectively removing the tensile stress film formed over the entire semiconductor substrate is required.
According to one aspect of the embodiments, a method for fabricating a semiconductor device includes: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film.
According to another aspect of the embodiments, a semiconductor device in which n-channel field-effect transistors are formed on a silicon substrate, including: a first stress film formed to cover the field-effect transistors and applying a strain to channel regions of the field-effect transistors; and a second stress film formed on the first stress film and applying a strain to the channel regions of the field-effect transistors.
The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description and are exemplary and explanatory and are not restrictive of the embodiments, as claimed.
Embodiments of the present invention will be described with reference to drawings. The present embodiments are only illustrative and the present invention is not limited to configurations shown in the embodiments.
The stress film 30 includes layers of thin stress films deposited as shown in
A process of actually fabricating a semiconductor device illustrated in
In this step, STIs 2 that isolate element formation regions 3 are formed in a silicon substrate 1 as shown in
In this step, the n-channel MOS transistors 10a, 10b and p-channel MOS transistors 20a, 20b are formed in the element formation regions 3 of the silicon substrate 1 in isolation from each other as shown in
First a silicon oxide film (not shown) is formed on the silicon substrate 1 in order to form gate insulating films 12a, 12b, 22a, 22b. Then, a polysilicon film (not shown) is formed by a method such as CVD in order to form gate electrodes 13a, 13b, 23a, 23b. The portions of the formed silicon oxide film and polysilicon film except the regions of the gate electrodes 13a, 13b, 23a, 23b are removed by photolithography or anisotropic etching. Then, sidewall films 14a 14b, 24a, and 24b are formed on the sidewalls of the gate electrodes 13a, 13b, 23a, and 23b, respectively.
The gate electrodes (13a, 13b, 23a, 23b) are 40 to 50 nm in width and approximately 100 nm in height, for example. Each of the sidewall films 14a, 14b, 24a, 24b is approximately 30 to 40 nm thick.
Concurrently with the formation of the gate electrodes 13a, 13b, 23a, 23b and the sidewall films 14a, 14b, 24a, 24b, extension regions 16, 26 and source-drain regions 17, 27 are formed.
In the region of the n-channel MOS transistors 10a, 10b, first the gate electrodes 13a, 13b are used as a mask to implant an n-type impurity to form extension regions 16. Then, the gate electrodes 15a, 15b having the sidewall films 14a, 14b formed are used as a mask to implant an n-type impurity to form source-drain regions 17. The n-type impurity may be arsenic (As), for example.
In the region of the p-channel MOS transistors 20a, 20b, first the gate electrodes 23a, 23b are used as a mask to implant a p-type impurity to form extension regions 26. Then, the gate electrodes 25a, 25b having the sidewall films 24a, 24b formed are used as a mask to implant a p-type impurity to form source-drain regions 27. The p-type impurity may be boron (B), for example.
In this step, silicide layers 18, 28 are formed on the surface of the gate electrodes 13a, 13b, 23a, 23b and on the surfaces of the source-drain regions 17, 27 as shown in
In this step, a silicon nitride film (first insulating film) 31a is formed and is then shrunk to form a first stress film 31 as shown in
A system used for depositing the silicon nitride on the silicon substrate 1 is a double parallel plate plasma enhanced CVD system (not shown). The gas for depositing the silicon nitride may be a mixed gas of silane (such as SiH4, SiH2Cl2, Si2H4, or Si2H6) and ammonium (NH3). The carrier gas used is a mixed gas of gases such as nitrogen (N2), argon (Ar), and helium (He). The conditions in the plasma CVD system are set as follows.
Here, it is desirable that the deposition of the silicon nitride films 31a is controlled to a thickness that does not form a discontinuous surface.
Then, the silicon substrate 1 is transferred from the plasma CVD system to a vacuum chamber (not shown), where the silicon substrate 1 on which the silicon nitride film 31a is formed is exposed to ultraviolet light (UV). The UV lamp used for UV exposure is a high-pressure mercury lamp which is commonly used. The atmosphere in the vacuum chamber may be a mixed gas of nitrogen, argon, and helium, for example. The conditions in the vacuum chamber are set as follows.
The silicon nitride film 31a is exposed to UV under the conditions listed above to shrink the silicon nitride film 31a to form a first stress film 31 having a tensile stress in the range from approximately 1500 to approximately 2000 Mpa. The first stress film 31 induces a tensile stress Ft1 in the silicon crystals in the channel regions 19, 29 of the MOS transistors formed on the silicon substrate 1. Here, the thickness of the silicon nitride film 31a is reduced by 5 to 20% by volume by the UV exposure compared with that before the UV exposure.
In this step, the same processing as that in the fourth step is performed. A silicon nitride film (second insulating film) 32a is formed on the first stress film 31 and is then shrunk to form a second stress film 32 as shown in
Like the first stress film 31, the second stress film 32 thus formed has a shrinkage force in the range from 1500 to 2000 Mpa and induces a tensile stress Ft2 in the channel regions 19, 29 of the MOS transistors formed on the silicon substrate 1.
In these steps, the same processing as that in the fifth step is performed twice to form third and fourth stress films 33 and 34 as illustrated in
In this way, the fourth step is repeated four times in total in the sequence of the fourth to seventh steps. As a result, a stress film 30 approximately 80 nm thick is formed on the silicon substrate 1 having the transistors (n-channel MOS transistors 10a, 10b and p-channel MOS transistors 20a, 20b) formed thereon.
In the present exemplary embodiment, a plurality of silicon nitride films having tensile stresses are formed in multiple steps as described above. Each silicon nitride film is deposited and then exposed to UV to shrink the film in each film forming step. Since the multilayered silicon nitride film is deposited in multiple steps, each silicon nitride film is deposited to a small thickness in each deposition step. Furthermore, since each silicon nitride film is shrunk by UV exposure to increase the gap before the next silicon nitride film is deposited, generation of a void as shown in
In order to transmit the force of the multilayered stress film 30 that strains silicon crystals to the silicon substrate 1, the first stress film 31 may be formed in contact with the silicon substrate 1.
It is also preferable that stress films formed nearer to the transistors are thinner than stress films formed farther from the transistors. Preferably, the stress film disposed closest to the transistors is thinner than the other stress films. The first stress film 31 may be the thinnest. If a stress film is formed so that these conditions are met, a silicon nitride film, immediately after the silicon nitride is deposited, that is, at the time the silicon nitride film has been formed, does not tend to form a discontinuous surface. Consequently, breaks in the stress film that would otherwise occur during shrinkage may be reliably inhibited.
In this step, the stress film 30 is removed from the regions in which the p-channel MOS transistors 20a, 20b are formed, as shown in
In this step, a stress film (fifth stress film) 40 and an insulating film 49 which acts as an etch stopper are formed on the insulating film 39 formed on the silicon substrate 1, as shown in
In this step, the stress film 40 and the insulating film 49 are removed from the regions where the n-channel MOS transistors 10a, 10b are formed and an interlayer insulating film 50 is formed, as shown in
In this way, n-channel MOS transistors 10a, 10b and p-channel MOS transistors 20a, 20b are formed on a silicon substrate 1 in the present exemplary embodiment and then a silicon nitride film (first insulating film) 31a covering these transistors is formed. Then, the silicon nitride film 31a is shrunk by UV exposure to form a first stress film 31. A silicon nitride film (second insulating film) 32a is formed on the first stress film 31 and is shrunk by UV exposure to form a second stress film 32. The process is repeated to form third and fourth stress films 33 and 34 on the second stress film 2. Then the stress films 31 to 34 are removed from the regions where the p-channel MOS transistors 20a, 20b are formed and then the fifth stress film 40 is formed in the region.
The structure has the following advantageous effects.
The present exemplary embodiment may inhibit breaks in the stress film 30 because a stress film (first stress film 31) thinner than the entire stress film (the first to fourth stress films 31 to 34) is formed first. Because the film (for example a silicon nitride film 31a) for forming the stress film is thin, a discontinuous surface 4 is less likely to be caused in the film formed in the region between adjacent gates, as shown in
A variation of the first exemplary embodiment will be described. The variation is an example in which, instead of UV exposure, plasma exposure is used in the step of shrinking a silicon nitride film or plasma exposure is performed in addition to UV exposure, if plasma exposure is performed in addition to UV exposure, any of the plasma exposure and UV exposure may be performed first. The effect of shrinking a silicon nitride film is provided irrespective of which of them is performed first. Plasma exposure is believed to have the effect of discharging hydrogen (H) from a nitride film. In the present exemplary embodiment, plasma exposure is used as assistance in shrinking films by UV exposure. In the second exemplary embodiment, plasma exposure is performed before UV exposure in the fourth to seventh steps of the first exemplary embodiment. The rest of the second exemplary embodiment is the same as the first exemplary embodiment.
For the plasma exposure, the plasma CVD system for CVD process in the first exemplary embodiment may be used. The plasma used may be nitrogen plasma, hydrogen plasma, or ammonium plasma. A deposited silicon nitride film is exposed to a nitrogen plasma, a hydrogen plasma, or an ammonium plasma to shrink the silicon nitride film. The types of plasmas are not limited to the examples enumerated above.
The conditions in the plasma CVD system for the plasma exposure are set as follows, for example.
The silicon nitride film exposed to the plasma is then exposed to UV.
The plasma exposure also acts on a silicon nitride film shrunk by UV exposure, thereby further shrinking the silicon nitride film. For example, plasma exposure of a deposited silicon nitride film 32a also acts on a stress film 31 already shrunk by UV exposure and further shrinks the thickness of the stress film 31.
The plasma exposure increases the amount of shrinkage of a silicon nitride film as compared with the first exemplary embodiment. The increase in the amount of shrinkage reduces the thickness of the stress film. As a result, a silicon nitride film subsequently deposited becomes less likely to form a break surface and the stress film becomes less prone to breaks. The plasma exposure may be performed in the same system used for depositing the silicon nitride films and therefore may be simply performed. The plasma exposure performed before UV exposure may improve the effect of inhibiting breaks in the stress film while at the same time providing a high tensile stress.
Results of examinations conducted on semiconductor devices fabricated by methods according to the first and second embodiments and a method of a comparative example to examine the crack generation rates will be given below. In the comparative example, the method illustrated in
First, the method according to the first exemplary embodiment was used to fabricate a semiconductor device including a stress film 30 (the structure illustrated in
Photolithography and etching were performed to remove the interlayer insulating film from the regions of the p-channel MOS transistors 20a, 20b. The resulting silicon wafer was observed under an SEM (Scanning Electron Microscope) and cross-sections of the silicon wafer were observed under TEM (Transmission Electron Microscope). The entire silicon wafer was observed in this way. The observations have not shown breaks in the stress film formed by the method of the first exemplary embodiment. The observations also have not shown any cracks in the STIs 2 of the silicon substrate 1.
Then, a stress film 30 was formed by the fabrication method of the second exemplary embodiment and the semiconductor device in which the stress film 30 was formed was observed by the same method described above. The observations have not shown any breaks or cracks.
Then, a stress film 60 was formed by the method of the comparative example and was observed by the same method described above. The observations have shown breaks in the stress film 60 and cracks in the STIs 2 of the silicon substrate 1. The observations have shown that breaks and cracks appear in regions of the pattern where successive gate electrode structures are formed at intervals of approximately 100 nm. More specifically, the breaks and cracks were observed in the regions between and around gates of the gate electrode structures near the surface of the silicon wafer.
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a depicting of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
This application is a divisional application of U.S. Ser. No. 12/567,972, filed Sep. 28, 2009, which is a continuation of international Application No. PCT/JP2007/056369 filed on Mar. 27, 2007, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12567972 | Sep 2009 | US |
| Child | 13598010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2007/056369 | Mar 2007 | US |
| Child | 12567972 | US |
