The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular relates to a semiconductor device employing a fin-type FET and a method for manufacturing the same.
A fin-type FET, which is one type of field-effect transistor, has a construction in which a thin fin-shaped silicon layer (hereinafter referred to as a ‘semiconductor beam’) erected on the surface of a semiconductor substrate is covered from three directions (the upper surface and the two side surfaces) by a gate electrode.
As illustrated in
However, the abovementioned fin-type FET has a problem in that there is a risk that the semiconductor beam or the semiconductor substrate may be damaged during the course of manufacture. This is because the semiconductor beam and the semiconductor substrate are exposed to excessive dry etching when the gate electrode is formed. This will now be described in detail.
In the process of forming the gate electrode, first a gate insulating film and a gate electrode material are formed in succession over the entire surface of the semiconductor beam, including the upper surface and the side surfaces. The film thickness in the perpendicular direction of the gate electrode material formed in this way differs greatly between sections formed on the side surfaces of the semiconductor beam and other sections. To elaborate, in the latter case the film thickness (X hereinafter) is determined in accordance with the amount of deposition, whereas in the former case the film thickness is increased by the height of the semiconductor beam (X+H hereinafter. H is the height of the semiconductor beam). After the gate electrode material has been formed, a masking film is used to cover the sections of the gate electrode material that are to remain as the gate electrode. Other sections of the gate electrode material are removed by anisotropic dry etching, with the masking film serving as a mask.
In the abovementioned dry etching, the gate electrode material formed on the side surfaces of the semiconductor beam is also subject to removal. Therefore, the duration of the dry etching must be set to a time that allows the gate electrode material having a film thickness of X+H to be removed adequately. However, if dry etching is performed with such a setting, dry etching continues to occur in the sections other than the side surfaces of the semiconductor beam even after the gate electrode material having a film thickness of X has been removed. As a result the gate insulating film, and the semiconductor beam and the semiconductor substrate thereunder are directly exposed to dry etching, and thus damage to the semiconductor beam and the semiconductor substrate is a concern.
The method of manufacturing a semiconductor device according to the present invention is characterized in that it comprises: a step of forming a first and a second dopant-diffused layer on the main surface of a semiconductor substrate; a step of forming a trench on a bottom surface of which is erected at least one semiconductor beam, each connected at one end to the abovementioned first dopant-diffused layer and connected at the other end to the abovementioned second dopant-diffused layer; a step of forming a gate insulating film on an inner surface of the abovementioned trench, including the side surfaces of each abovementioned at least one semiconductor beam, and on an upper surface of each abovementioned at least one semiconductor beam; a step of depositing a gate electrode material having a film thickness that exceeds the respective upper surfaces of each abovementioned at least one semiconductor beam, after the abovementioned gate insulating film has been formed; and a step of removing the abovementioned gate electrode material that is located outside the abovementioned trench as seen in a plan view, while leaving the abovementioned gate electrode material that is located inside the abovementioned trench as seen in a plan view.
The semiconductor device according to the present invention is characterized in that it comprises: a first and a second dopant-diffused layer formed on the main surface of a semiconductor substrate; a trench on a bottom surface of which is erected at least one semiconductor beam, each connected at one end to the abovementioned first dopant-diffused layer and connected at the other end to the abovementioned second dopant-diffused layer; a gate insulating film covering an inner surface of the abovementioned trench, including the side surfaces of each abovementioned at least one semiconductor beam, and an upper surface of each abovementioned at least one semiconductor beam; and a gate electrode covering, with the interposition of the abovementioned gate insulating film, the inner surface of the abovementioned trench, including the side surfaces of each abovementioned at least one semiconductor beam, and the upper surface of each abovementioned at least one semiconductor beam.
According to the present invention, it is possible to form the gate electrode by dry etching (in the first mode of embodiment discussed hereinafter) only sections of the gate electrode material that have been formed to a given film thickness, or by grinding the gate electrode material using a CMP method or the like (in the second mode of embodiment discussed hereinafter). Damage to the semiconductor beam or the semiconductor substrate resulting from the dry etching of the gate electrode material is therefore significantly suppressed compared with the background art discussed hereinabove.
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
[
Preferred modes of embodiment of the present invention will now be described in detail with reference to the accompanying drawings.
As illustrated in
A trench 11 is provided in the surface of the semiconductor substrate 1. As illustrated in
Three semiconductor beams 4 disposed at equal intervals in the X-direction are erected on the bottom surface of the trench 11, each extending in the Y-direction. The upper surface of each semiconductor beam 4 is located at the same height as the element isolation region 2 and the active region K. Further, each semiconductor beam 4 is connected respectively at one end of the trench 11 in the Y-direction to the first substrate region 1A and at the other end to the second substrate region 1B. Four trenches 11A to 11D are formed in the interior of the trench 11 by providing the semiconductor beams 4.
As illustrated in
As illustrated in
The region of the semiconductor substrate 1 from a location at the depth Z1 (>Z2) as far as the upper surface of the semiconductor substrate 1, excluding the regions comprising the dopant-diffused layers 5A, 5B, comprises a dopant-diffused layer 5C in which a dopant has been diffused. Therefore the surface of each semiconductor beam 4 and the bottom surfaces of the trenches 11A to 11D each comprise the dopant-diffused layer 5C, the dopant-diffused layer 5C within the active region K being integrated. Further, the dopant-diffused layer 5C is also formed below the element isolation region 2. A conduction-type dopant that differs from that in the dopant-diffused layers 5A, 5B is introduced into the dopant-diffused layer 5C.
A gate insulating film 6 covers the inner surface of the trench 11, including the side surfaces of each semiconductor beam 4, and the upper surfaces of each semiconductor beam 4. It should be noted that the sections of this gate insulating film 6 that are in contact with the element isolation region 2 and the dopant-diffused layers 5A, 5B do not function as gate insulating films, and therefore they are hereinafter referred to simply as ‘insulating films 8’, without the word ‘gate’.
The interior of the trench 11 is filled, on top of the gate insulating film 6 and the insulating film 8, with a gate electrode 7 comprising a laminated film (gate electrode material) of tungsten and titanium nitride. As illustrated for example in
By means of the construction described hereinabove, one MOS transistor (fin-type FET) is configured in the active region K, the gate electrode 7 serving as a gate, one of the dopant-diffused layers 5A, 5B serving as a source, and the other serving as a drain. The dopant-diffused layer 5C sandwiched between the dopant-diffused layer 5A and the dopant-diffused layer 5B constitutes the channel region of this MOS transistor.
It should be noted that in the semiconductor device 100, three semiconductor beams 4 are provided within the trench 11, but the scope of application of the present invention is not limited to this number. The present invention can be suitably applied in general to fin-type semiconductor devices in which one or more semiconductor beams 4 is provided within the trench 11.
A conductive film 12 is formed on the upper surface of the gate electrode 7. The conductive film 12 is formed by means of a polysilicon film in which a conduction-type dopant that is the same as the dopant diffused in the dopant-diffused layers 5A, 5B has been diffused. Further, an interlayer insulating film 9 comprising a silicon dioxide film is formed on the regions of the respective upper surfaces of the active region K and the element isolation region 2 that do not overlap the gate electrode 7 as seen in a plan view. The upper surface of the interlayer insulating film 9 is located at the same height as the upper surface of the conductive film 12.
A wiring line 13 extending in the X-direction is disposed on the upper surface of the conductive film 12 and the interlayer insulating film 9. Supply of power to the gate electrode 7 is effected via the wiring line 13. The length of the wiring line 13 in the Y-direction is set such that it is similar to the length of the semiconductor beams 4 in the Y-direction.
An interlayer insulating film 16 comprising a silicon dioxide film is provided on the upper surface of the interlayer insulating film 9 to a film thickness such that it covers the wiring line 13. Wiring lines 15A, 15B, each extending in the X-direction, are disposed on the upper surface of the interlayer insulating film 16. The wiring line 15A is formed above the first substrate region 1A, and is connected to the first substrate region 1A (the dopant-diffused layer 5A) by means of contact plugs 14A which penetrate through the interlayer insulating films 9, 16. Meanwhile, the wiring line 15B is formed above the second substrate region 1B, and is connected to the second substrate region 1B (the dopant-diffused layer 5B) by means of contact plugs 14B which penetrate through the interlayer insulating films 9, 16. As illustrated in
The operation of the semiconductor device 100 having the configuration described hereinabove will now be described. When the wiring line 13 is activated, the gate electrode 7 is activated via the conductive film 12, and a channel is formed in the dopant-diffused layer 5C. In other words, the MOS transistor configured within the active region K is turned on. This channel causes the dopant-diffused layer 5A and the dopant-diffused layer 5B to conduct, giving rise to a state in which the wiring lines 15A and 15B are electrically connected to each other. On the other hand, when the wiring line 13 is in an inactive state, the gate electrode 7 becomes inactive, via the conductive film 12, and the channel within the dopant-diffused layer 5C disappears. In other words, the MOS transistor configured within the active region K is turned off. In this case, the dopant-diffused layer 5A and the dopant-diffused layer 5B are electrically isolated from each other, and thus the wiring lines 15A and 15B are also electrically isolated from each other.
According to the semiconductor device 100 of the present mode of embodiment, as described in detail hereinafter it is possible to form the gate electrode 7 by dry etching only sections of the gate electrode material that have been formed to a given film thickness. Damage to the semiconductor beams 4 or the semiconductor substrate 1 caused by dry etching of the gate electrode material when the semiconductor device 100 is being manufactured can therefore be significantly suppressed compared with the background art discussed hereinabove.
Further, the side surfaces and the upper surface of each semiconductor beam 4, and the bottom surfaces of the trenches 11A to 11D (the sections other than the sections in which the element isolation region 2 is exposed) can be used as a channel region, and therefore the effective channel width can be increased compared with a case in which a planar MOS transistor occupying the same surface area is produced. The electrical driving force is thus increased and the channel-potential controllability improves, and it is therefore possible to avoid degradation of the element characteristics resulting from the short channel effect, which has been a problem with planar MOS transistors, without increasing the dopant concentration within the channel.
A method of manufacturing the semiconductor device 100 according to the present mode of embodiment will now be described with reference to the drawings.
In this method of manufacture, first the semiconductor substrate 1 is prepared, and as illustrated in
Next, using a CVD (Chemical Vapor Deposition) method, a masking film 21, being a silicon nitride (SiN) film having a film thickness of 50 nm, is formed on the upper surface of the silicon dioxide film which is not shown in the drawings discussed hereinabove. Then, after the masking film 21 in the region in which the element isolation region 2 is to be formed has been removed using a photolithographic method, dry etching is performed, using the remaining masking film 21 as a mask, to form a trench 10 demarcating the active region K. By forming the trench 10, an island-shaped dopant-diffused layer 5C having a length X1 in the X-direction and a length Y1 in the Y-direction is formed on the surface of the semiconductor substrate 1, as illustrated in
Next, a silicon dioxide film is deposited using a CVD method to a film thickness whereby the trench 10 is filled (300 nm), after which the silicon dioxide film that has been deposited on the upper surface of the masking film 21 is removed using a CMP (Chemical Mechanical Polishing) method. Then a 30 nm-thick portion (equivalent to the height of the masking film 21) of the upper portion of the silicon dioxide film that has been formed in the interior of the trench 10 is removed using an etch-back method, after which the remaining masking film 21 is removed using a wet etching method. By this means the trench 10 is filled, and an element isolation region 2 demarcating the active region K is formed, as illustrated in
Next, as illustrated in
Next, arsenic (As) is implanted into the first and second substrate regions 1A, 1B via the open portions 22A, 22B using an ion implantation method. By this means dopant-diffused layers 5A, 5B are formed respectively in the first and second substrate regions 1A, 1B. Preferably this arsenic implantation is performed under implantation conditions in which the implantation energy is 20 keV and the dosage is 5×1015 atoms/cm2, the arsenic being thermally diffused, after implantation, to a depth of 110 nm (=Z3) by heat-treating the semiconductor substrate 1 for 30 minutes at 900° C. to yield a concentration of 1×1020 atoms/cm3.
The photoresist 22 is removed when formation of the dopant-diffused layers 5A, 5B is complete, after which a protective film 23, being a silicon dioxide film having a thickness of 10 nm, and a masking film 24 (a first masking film), being a silicon nitride film having a thickness of 100 nm, are formed in succession on the upper surface of the semiconductor substrate 1 using a CVD method. A photolithographic method and a dry etching method are then used to process the masking film 24 into the pattern of the trenches 11A to 11D discussed hereinabove, and then dry etching is performed using the masking film 24 as a mask to form the trenches 11A to 11D illustrated in
Next the protective film 23 and the masking film 24 are removed using a wet etching method, to expose the respective upper surfaces of the semiconductor beams 4, the first and second substrate regions 1A, 1B and the element isolation region 2. A silicon dioxide film having a thickness of 1.5 nm is then formed over the entire surface using a CVD method, and further a silicon dioxide film having a thickness of 2 nm is formed using a thermal oxidation method. As illustrated in
A gate electrode material which will form the gate electrode 7 is next deposited to a film thickness whereby the trench 11 is filled. More specifically, titanium nitride (TiN) having a thickness of 5 nm is formed over the entire surface using a CVD method, and further, tungsten (W) having a thickness of 60 nm is deposited over the entire surface using a CVD method. As illustrated in
Next, a masking film (a second masking film; not shown in the drawings) which covers a region corresponding to the inside of the trench 11 as seen in a plan view is formed by photolithography, and this is used as a mask for dry etching performed to remove the gate electrode material located outside the trench 11 as seen in a plan view, as illustrated in
Here, the gate electrode material which is subjected to dry etching in this step is only the section located outside the trench 11 as seen in a plan view (only the section deposited above the first and second substrate regions 1A, 1B and the element isolation region 2). The film thickness of the gate electrode material in this section is constant, and therefore damage to the semiconductor beams 4 and the semiconductor substrate 1 resulting from the dry etching of the gate electrode material is significantly suppressed compared with the background art discussed hereinabove.
Next, an ion implantation method is used to implant arsenic into regions within the dopant-diffused layers 5A, 5B (the first and second substrate regions 1A, 1B) in particular in the vicinity of the semiconductor beams 4 and the trenches 11A to 11D, and further, the implanted arsenic is caused to diffuse into each semiconductor beam 4 by thermal diffusion. By this means, as illustrated in
Next, a silicon dioxide film having a thickness of 100 nm is deposited over the entire surface using a CVD method, and further, by effecting planarization using a CMP method, this silicon dioxide film is removed to the extent that the upper surface of the gate electrode 7 is exposed. By this means, as illustrated in
Next, the upper surface of the gate electrode 7 is excavated to a thickness of 10 nm by etch-back using dry etching. Because this dry etching only shaves a little from the upper surface of the gate electrode 7, it does not damage the underlying material. By this means a recessed portion 29 having a depth of 10 nm is formed, the side surfaces thereof comprising the interlayer insulating film 9 and the bottom surface comprising the gate electrode 7, as illustrated in
Next, after depositing tungsten having a thickness of 50 nm over the entire surface using a CVD method, the tungsten is processed into the shape of a wiring line 13 by means of a photolithographic method and a dry etching method. As discussed hereinabove, the wiring line 13 extends in the X-direction and is in contact at its lower surface with the conductive film 12.
Next, as illustrated in
After the contact plugs 14A, 14B have been formed, tungsten nitride (WN) and tungsten (W) are successively laminated onto the upper surface of the interlayer insulating film 16 using a sputtering method, and these are processed to form the wiring lines 15A, 15B by means of a photolithographic method and a dry etching method. It should be noted that the wiring line 15A is formed in such a way that it covers the contact plugs 14A, and the wiring line 15B is formed in such a way that it covers the contact plugs 14B. By this means the wiring lines 15A, 15B are respectively connected via the contact plugs 14A, 14B to the dopant-diffused layers 5A, 5B.
As explained hereinabove, according to this method of manufacture, only sections of the gate electrode material that have been formed to a given film thickness are subjected to dry etching. Damage to the semiconductor beams 4 or the semiconductor substrate 1 resulting from the dry etching of the gate electrode material is therefore significantly suppressed compared with the background art discussed hereinabove.
The semiconductor device 100 according to the present mode of embodiment differs in that the sections of the gate electrode 7 that were formed in sections overlapping the two end portions in the Y-direction of the trench 11 as seen in a plan view have been replaced with the interlayer insulating film 9, and in that the dopant-diffused layers 5A, 5B have also been provided in the interior of each semiconductor beam 4. There are also differences in the places in which the insulating film 8 remains, and in that the protective film 23 remains, but these result from changes to the manufacturing processes concomitant with the abovementioned two differences. An explanation focusing on the points of difference will now be provided.
First, with regard to the dopant-diffused layers 5A, 5B, in the present mode of embodiment the dopant-diffused layers 5A, 5B are also provided in the interior of each semiconductor beam 4, as illustrated in
Next, regarding the gate electrode 7 according to the present mode of embodiment, as illustrated in
As illustrated in
According to the semiconductor device 100 of the present mode of embodiment, as described in detail hereinafter it is possible to form the gate electrode 7 using a CMP method rather than by dry etching. There is therefore no damage to the semiconductor beams 4 or the semiconductor substrate 1 caused by dry etching of the gate electrode material when the semiconductor device 100 is being manufactured.
Further, the side surfaces and the upper surface of each semiconductor beam 4C, and the corresponding bottom surfaces of the trenches 11A to 11D (the sections other than the sections in which the element isolation region 2 is exposed) can be used as a channel region, and therefore the effective channel width can be increased compared with a case in which a planar MOS transistor occupying the same surface area is produced. The electrical driving force is thus increased and the channel-potential controllability improves, and it is therefore possible to avoid degradation of the element characteristics resulting from the short channel effect, which has been a problem with planar MOS transistors, without increasing the dopant concentration within the channel.
It should be noted that, as discussed hereinafter, the process for manufacturing the semiconductor device 100 according to the present mode of embodiment includes a step in which, after the interior of the trenches 11A to 11D has been filled with an insulating film 26, the insulating film 26 located in sections in which the gate electrode 7 is to be formed is removed using a photolithographic method and a dry etching method. The gate electrode 7 is formed by filling the sections in which the insulating film 26 has been removed with a gate electrode material, but there is a possibility that the etching location may deviate in the Y-direction when the insulating film 26 is being etched. However, according to the semiconductor device 100 of the present mode of embodiment, even if for sake of argument the etching location of the insulating film 26 were to deviate in the Y-direction, the interlayer insulating film 9 which subsequently replaces the insulating film 26 would serve as a buffer region, and it is therefore possible to prevent degradation of the element characteristics resulting from this positional deviation.
A method of manufacturing the semiconductor device 100 according to the present mode of embodiment will now be described with reference to the drawings.
In this method of manufacture also, first the dopant-diffused layer 5C, the element isolation region 2 and the active region K are formed on the surface of the semiconductor substrate 1. The steps up to this point are the same as were described for the first mode of embodiment with reference to
Next, as illustrated in
Next, as illustrated in
After the trenches 11A to 11D have been formed, a protective film 25, being a silicon dioxide film having a thickness of 10 nm, and the masking film 26 (fourth masking film), being a silicon nitride film having a thickness of 70 nm, are deposited successively using a CVD method. Then, the protective film 25 and the insulating film 26 remaining on the upper surface of the masking film 24 are removed using a CMP method, the protective film 25 and the insulating film 26 remaining only in the interior of the trenches 11A to 11D. It should be noted that the film thickness of the masking film 24 remaining after removal using the CMP method at this time is approximately 80 nm, which is approximately 20 nm less than when it was first deposited.
Next, a multilayer masking film 27 is applied over the entire surface, and as illustrated in
Here, the dry etching employed when the trenches 28 are formed is performed under conditions such that the silicon nitride film is selectively removed. By this means, while the dry etching is being performed, the protective film 25 remains on the inner surfaces of the trenches 11A to 11D. Further, the film thickness of the insulating film 26 subjected to removal by dry etching is constant. There is therefore almost no risk that the semiconductor substrate 1 exposed on the inner surfaces of the trenches 11A to 11D will be damaged by the dry etching. Further, a trench 31 is formed using wet etching, and thus the risk that this will damage the semiconductor substrate 1 is also small. It may therefore be assumed that there is almost no risk that the dry etching effected here will damage the semiconductor substrate 1.
When the trenches 28 have been formed, the multilayer masking film 27 is removed, after which a resist mask 30 is applied, and the pattern of the gate electrode 7 is transferred using a photolithographic method as illustrated in
A silicon dioxide film having a thickness of 1.5 nm is then formed over the entire surface using a CVD method, after which a silicon dioxide film having a thickness of 2 nm is formed using a thermal oxidation method on the inner surface of the trench 31, including the upper surfaces and the side surfaces of each semiconductor beam 4. As illustrated in
A gate electrode material which will form the gate electrode 7 is next deposited to a film thickness whereby the trench 31 is filled. More specifically, titanium nitride (TiN) having a thickness of 5 nm is formed over the entire surface using a CVD method, and further, tungsten (W) having a thickness of 60 nm is deposited over the entire surface using a CVD method. The tungsten and the titanium nitride are then removed using a CMP method until the masking film 24 is exposed. The gate electrode 7 is formed by this means in the interior of the trench 31, as illustrated in
In this way, in the present mode of embodiment the gate electrode 7 can be formed by grinding the gate electrode material using a CMP method. In the present mode of embodiment there is therefore no damage to the semiconductor beams 4 or the semiconductor substrate 1 resulting from dry etching of the gate electrode material.
Next, the upper surface of the gate electrode 7 is excavated to a thickness of 10 nm by etch-back using dry etching. Because this dry etching only shaves a little from the upper surface of the gate electrode 7, it does not damage the underlying material. By this means the gate electrode 7 is formed covering the interior of the trench 31, with the interposition of the gate insulating film 6 or the insulating film 8, and the recessed portion 29 surrounded by the insulating film 8 and the gate electrode 7 is formed in the upper portion of the trench 31. It should be noted that the depth of the recessed portion 29, namely 10 nm, is determined in such a way that the bottom surface of the recessed portion 29 is located above the upper surface of the gate insulating film 6 formed on the upper surface of the semiconductor beams 4C.
A polysilicon film (polycrystalline silicon film) is then deposited over the entire surface using a CVD method to a film thickness whereby the recessed portion 29 is filled, and the sections formed outside the recessed portion 29 as seen in a plan view are removed using a CMP method. By this means the interior of the recessed portion 29 is filled with the conductive film 12, which is a polysilicon film.
Next, the masking film 24 and the insulating film 26 that are exposed are removed by means of a wet etching method using heated phosphoric acid. By this means, as illustrated in
Next, an ion implantation method is used to implant arsenic via the trenches 32A, 32B into the exposed surfaces of the semiconductor beams 4, and further, the implanted arsenic is caused to diffuse by thermal diffusion in the vicinity of the boundaries between the semiconductor beams 4C and the semiconductor beams 4A, 4B. By this means, as illustrated in
Next, a silicon dioxide film having a thickness of 100 nm is deposited over the entire surface using a CVD method, after which this is removed using a CMP method to expose the upper surface of the conductive film 12. By this means, as illustrated in
As described hereinabove, according to this method of manufacture, the gate electrode 7 is formed using a CMP method rather than by dry etching. There is therefore no damage to the semiconductor beams 4 or the semiconductor substrate 1 resulting from dry etching of the gate electrode material.
Further, according to this method of manufacture, both end portions of the trench 11 in the Y-direction are filled using the interlayer insulating film 9 after the central portion of the trench 11 in the Y-direction has been filled using the gate electrode 7. According to such a method of manufacture, the interlayer insulating film 9 sandwiching the gate electrode 7 fulfills the role of an insulator between the gate electrode 7 and the first and second substrate regions 1A, 1B, and it is therefore possible to avoid degradation of the element characteristics resulting from positional deviation of the gate electrode 7 in the Y-direction.
Preferred modes of embodiment of the present invention have been described hereinabove, but various modifications to the present invention may be made without deviating from the gist of the present invention, without limitation to the abovementioned modes of embodiment, and it goes without saying that these are also included within the scope of the present invention.
For example, the method of manufacture according to the second mode of embodiment may be employed not only in the manufacture of the semiconductor device 100 according to the second mode of embodiment, but also in the manufacture of the semiconductor device 100 according to the first mode of embodiment. In this case it is preferable to omit the step of forming the protective film 25 and the insulating film 26, and the step of forming the trenches 28 using the multilayer masking film 27.
Further, in the abovementioned first mode of embodiment the dopant-diffused layers 5A, 5B are not formed within the semiconductor beams 4, but in the same way as in the second mode of embodiment, the dopant-diffused layers 5A, 5B may also be provided within the semiconductor beams 4 in the first mode of embodiment.
Number | Date | Country | Kind |
---|---|---|---|
2012-181130 | Aug 2012 | JP | national |
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/JP2013/072014 | 8/16/2013 | WO | 00 |