Patent Application
20250062209
The disclosure relates in general to a semiconductor device and a semiconductor package structure, and more particularly to a semiconductor device and a semiconductor package structure including Ultra Thick Metal (UTM).
In a Radio Frequency (RF) circuit device, Ultra Thick Metal (UTM) is used as the power path of the RF circuit device for well current distribution, power integrity and reducing IR-drop. However, when the circuit design/routing becomes more and more complicated, the availability of the UTM is reduced. Therefore, the RF circuit device suffers from the constraint on power/ground routing and the routing in the circuit such as interconnect and passive element.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
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In some instances, some RF circuit devices employ both general metal layers and UTM layers 121 in which the UTM layers 121 have a greater thickness than the general metal layers. For example, while some general metal layers range from about 1 μm to about 2 μm in thickness, the UTM layers 121 range from about 2 μm to about 4 μm in thickness. In some RF circuit devices, one or more UTM layers 121 are formed over the general metal layers separated by insulating layers except where portions of the metal and UTM layers 121 are connected by one or more vias.
In some embodiments, the general metal layer stacked on the RF circuit 111 forms a portion of an inductor. In other embodiments, the general metal layer stacked on the RF circuit 111 forms a portion of a capacitor. Still in other embodiments, the UTM layer 121 forms a portion of a power line.
In this embodiment, the semiconductor device 100 further includes at least one aluminum (AP) mesh layer 131 stacked on the UTM layer 121. The UTM layer 121 is connected to a power source Vdd or a ground GND through the aluminum mesh layer 131. The thickness of the aluminum mesh layer 131 is 1.4 to 2.8 um. The aluminum mesh layer 131 is extended to some area beyond the UTM layer 121. The aluminum mesh layer 131 connected to the UTM layer 121 could improve the electrical conductivity and reduce the parasitic resistance for power and grounding.
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For example, the aluminum mesh layer 131 is composed of a plurality of lines L131i, L131j crossed with each other, such that the aluminum mesh layer 131 forms the mesh structure. The lines L131i are substantially perpendicular to the lines L131j. The lines L131i may have substantially identical widths, the lines L131j may have substantially identical widths, and the widths of the lines L131i and the widths of the lines L131j may be substantially identical.
Or, for example, the aluminum mesh layer 131 has a plurality of holes H131 arranged in a matrix, such that the aluminum mesh layer 131 forms the mesh structure. The holes H131 may be rectangle shaped or circle shaped. The holes H131 may have substantially identical sizes.
The shapes of the holes H131 are not used to limit to the present invention. Please refer to
The widths of the lines L131i, L131j are not used to limit to the present invention. Please refer to
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For example, the cooper mesh RDL 231 is composed of a plurality of lines L231i, L231j crossed with each other, such that the cooper mesh RDL 231 forms a mesh structure. The lines L231i are substantially perpendicular to the lines L231j. The lines L231i may have substantially identical widths, the lines L231j may have substantially identical widths, and the widths of the lines L231i and the widths of the lines L231j may be substantially identical.
Or, for example, the cooper mesh RDL 231 has a plurality of holes H231 arranged in a matrix, such that the cooper mesh RDL 231 forms the mesh structure. The holes H231 may be rectangle shaped or circle shaped. The holes H231 may have substantially identical sizes.
The shapes of the holes H231 are not used to limit the present invention. Please refer to
The widths of the lines L231i, L231j are not used to limit the present invention. Please refer to
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Please referring to the following table I, the performances of the amplifiers in the semiconductor device with/without the aluminum mesh layer or the cooper mesh RDL are shown.
“OP1dB” is the output power level at which the gain decreases 1 dB from its constant value, which represents an index of linearity of a circuit. “PAE” is the power added efficiency defined as the ratio of the difference of the output and input signal power to the DC power consumed. As shown in the table I, the stability factor (k) could be greatly enhanced from 2.0 to 57.6 by using consolidated power mesh. Moreover, PA performance (gain, OP1dB, PAE@OP1 dB) can be enhanced as well by using consolidated power mesh.
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The semiconductor device 300 includes a FEOL part 310 and a BEOL part 320. The FEOL part 310 includes, for example, a RF circuit 311 including a plurality of matching network circuit 3111 and a plurality of amplifiers 3112. The BEOL part 320 is formed after the FEOL part 310. The BEOL part 320 includes, for example, at least one UTM layer 321, such as a plurality of top UTM layers and a plurality of sub-UTM layers and at least one passive component 322, such as a plurality of capacitors, stacked on the RF circuit 311. The thickness of the UTM layer 321 is, for example, 2 to 4 um.
The UTM layer 321 is connected to the power source Vdd or the ground GND through the routing mesh layer 331. The routing mesh layer 331 connected to the UTM layer 321 could improve the electrical conductivity and reduce the parasitic resistance for power and grounding.
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For example, the routing mesh layer 331 is composed of a plurality of lines L331i, L331j crossed with each other, such that the routing mesh layer 331 forms the mesh structure. The lines L331i are substantially perpendicular to the lines L331j. The lines L331i may have substantially identical widths, the lines L331j may have substantially identical widths, and the widths of the lines L331i and the widths of the lines L331j may be substantially identical.
Or, for example, the routing mesh layer 331 has a plurality of holes H331 arranged in a matrix, such that the routing mesh layer 331 forms the mesh structure. The holes H331 may be rectangle shaped or circle shaped. The holes H331 may have substantially identical sizes.
The shapes of the holes H331 are not used to limit the present invention. Please refer to
The widths of the lines L331i, L331j are not used to limit the present invention. Please refer to
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The semiconductor device 400 includes a FEOL part 410 and a BEOL part 420. The FEOL part 410 includes, for example, a RF circuit 411 including a plurality of matching network circuit 4111, a plurality of amplifiers 4112 and a plurality of through silicon via (TSV) 4113. The BEOL part 420 is formed after the FEOL part 410. The BEOL part 420 includes, for example, at least one UTM layer 421, such as a plurality of top UTM layers and a plurality of sub-UTM layers and at least one passive component 422, such as a plurality of capacitors, stacked on the RF circuit 411. The thickness of the UTM layer 421 is, for example, 2 to 4 um.
The UTM layer 421 is connected to the power source Vdd or the ground GND through the routing mesh layers 431, 441. The routing mesh layers 431, 441 connected to the UTM layer 421 could improve the electrical conductivity and reduce the parasitic resistance for power and grounding.
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For example, the routing mesh layer 431 is composed of a plurality of lines L431i, L431j crossed with each other, such that the routing mesh layer 431 forms the mesh structure. The lines L431i are substantially perpendicular to the lines L431j. The lines L431i may have substantially identical widths, the lines L431j may have substantially identical widths, and the widths of the lines L431i and the widths of the lines L431j may be substantially identical.
Or, for example, the routing mesh layer 431 has a plurality of holes H431 arranged in a matrix, such that the routing mesh layer 431 forms the mesh structure. The holes H431 may be rectangle shaped or circle shaped. The holes H431 may have substantially identical sizes.
The shapes of the holes H431 are not used to limit the present invention. In other embodiments, the holes (not shown) may have different sizes.
Further, the widths of the lines L431i, L431j are not used to limit the present invention. In other embodiments, the lines may have different widths.
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The semiconductor device 500A includes a FEOL part 510 and a BEOL part 520. The FEOL part 510 includes a plurality of TSVs 511. The BEOL part 520 is formed after the FEOL part 510. The BEOL part 520 includes, for example, at least one UTM mesh layer 521, such as a plurality of top UTM layers and a plurality of sub-UTM layers and at least one passive component 522, such as a plurality of capacitors. The thickness of the UTM mesh layer 521 is, for example, 2 to 4 um.
The semiconductor device 500B includes a FEOL part 530 and a BEOL part 540. The FEOL part 530 includes, for example, a RF circuit 531 including a plurality of matching network circuit 5311 and a plurality of amplifiers 5312. The BEOL part 540 is formed after the FEOL part 530. The BEOL part 540 includes, for example, at least one UTM layer 541, such as a plurality of top UTM layers and a plurality of sub-UTM layers and at least one passive component 542, such as a plurality of capacitors, stacked on the RF circuit 531. The thickness of the UTM layer 541 is, for example, 2 to 4 um.
The UTM mesh layer 521 and the UTM layer 541 are connected to the power source Vdd or the ground GND through the TSVs 511. The UTM mesh layers 521 connected to the UTM layer 541 could improve the electrical conductivity and reduce the parasitic resistance for power and grounding.
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For example, the UTM mesh layer 521 is composed of a plurality of lines L521i, L521j crossed with each other, such that the UTM mesh layer 521 forms the mesh structure. The lines L521i are substantially perpendicular to the lines L521j. The lines L521i may have substantially identical widths, the lines L521j may have substantially identical widths, and the widths of the lines L521i and the widths of the lines L521j may be substantially identical.
Or, for example, the UTM mesh layer 521 has a plurality of holes H521 arranged in a matrix, such that the UTM mesh layer 521 forms the mesh structure. The holes H521 may be rectangle shaped or circle shaped. The holes H521 may have substantially identical sizes.
The shapes of the holes H521 are not used to limit the present invention. In other embodiments, the holes (not shown) may have different sizes.
Further, the widths of the lines L521i, L521j are not used to limit the present invention. In other embodiments, the lines may have different widths.
According to the embodiments described above, the UTM layer 121, 221, 321, 421, 541 stacked with (or connected to) the aluminum mesh layer 131, the cooper mesh RDL 231, the routing mesh layer 331, the routing mesh layer 431 and the UTM mesh layer 521 can substantially reduce parasitic resistance for power & grounding.
Besides, the routing mesh layers 331, 431, 441 with multi layers structure could further reduce parasitic resistance because 3DIC has more routing resource (More layer, more metal scheme, and more flexibility of design rule check).
Furthermore, the matching network circuit 1111, 2111, 3111, 4111, 5311 could be implemented by UTM or InFO/CoWoS with high design flexibility to obtain a high quality passive element for circuit performance.
By the consolidated power mesh in 3DIC RF circuit, the current distribution, power integrity, and IR drop problem and be solved, and it has the potential to improve circuit performances such as stability, power efficiency, power performance, and reliability especially for high power circuit.
This disclosure covers the possibility of nowadays AP/Cu-RDL & packaging technology for integration circuit. It has the design flexibility for wide range of solutions.
Example embodiment 1: A semiconductor device is provided. The semiconductor device includes a Radio Frequency (RF) circuit, at least one Ultra Thick Metal (UTM) layer and at least one aluminum (AP) mesh layer. The UTM layer is stacked on the RF circuit. The aluminum mesh layer is stacked on the UTM layer, and the UTM layer is connected to a power source or a ground through the aluminum mesh layer.
Example embodiment 2 based on the Example embodiment 1: The aluminum mesh layer is composed of a plurality of lines crossed with each other to form a mesh structure.
Example embodiment 3 based on the Example embodiment 2: Some of the lines are substantially perpendicular to others of the lines.
Example embodiment 4 based on the Example embodiment 2: Some of the lines substantially have identical widths.
Example embodiment 5 based on the Example embodiment 1: The aluminum mesh layer has a plurality of holes arranged in a matrix to form a mesh structure.
Example embodiment 6 based on the Example embodiment 5: Some of the holes substantially have identical sizes.
Example embodiment 7 based on the Example embodiment 1: A thickness of the aluminum mesh layer is 1.4 to 2.8 um.
Example embodiment 8: A semiconductor device is provided. The semiconductor device includes a Radio Frequency (RF) circuit, at least one Ultra Thick Metal (UTM) layer and at least one copper mesh redistribution layer (RDL). The UTM layer is stacked on the RF circuit. The copper mesh RDL is stacked on the UTM layer, and the UTM layer is connected to a power source or a ground through the copper mesh RDL.
Example embodiment 9 based on the Example embodiment 8: The copper mesh RDL is composed of a plurality of lines crossed with each other to form a mesh structure.
Example embodiment 10 based on the Example embodiment 8: Some of the lines are substantially perpendicular to others of the lines.
Example embodiment 11 based on the Example embodiment 10: Some of the lines substantially have identical widths.
Example embodiment 12 based on the Example embodiment 8: The copper mesh RDL has a plurality of holes arranged in a matrix to form a mesh structure.
Example embodiment 13 based on the Example embodiment 12: Some of the holes substantially have identical sizes.
Example embodiment 14 based on the Example embodiment 8: A thickness of the copper mesh RDL is 2.8 to 5.5 um.
Example embodiment 15: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor device and an interposer. The semiconductor device includes a Radio Frequency (RF) circuit and at least one Ultra Thick Metal (UTM) layer. The UTM layer is stacked on the RF circuit. The interposer includes at least one routing mesh layer. The interposer is stacked on the semiconductor device, and the UTM layer is connected to a power source or a ground through the routing mesh layer.
Example embodiment 16 based on the Example embodiment 15: The routing mesh layer is composed of a plurality of lines crossed with each other to form a mesh structure.
Example embodiment 17 based on the Example embodiment 16: Some of the lines are substantially perpendicular to others of the lines.
Example embodiment 18 based on the Example embodiment 17: Some of the lines substantially have identical widths.
Example embodiment 19 based on the Example embodiment 15: The routing mesh layer has a plurality of holes arranged in a matrix to form a mesh structure.
Example embodiment 20 based on the Example embodiment 19: Some of the holes substantially have identical sizes.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
