Claims
- 1. A compound semiconductor device, comprising:a Si substrate; a first group III-V compound semiconductor layer provided on said Si substrate, said first group III-V compound semiconductor layer having a thickness set to enable a direct deposition of said first group III-V compound semiconductor layer on a surface of said Si substrate, said Si substrate containing oxidation-induced stacking faults with a density sufficient for suppressing a diffusion of a group V element in said first group III-V compound semiconductor layer into said Si substrate; a second group III-V compound semiconductor layer provided on said first group III-V compound semiconductor layer, said second group III-V compound semiconductor layer containing Al and having a thickness that minimizes a surface roughness thereof; a third group III-V compound semiconductor layer provided on said second group III-V compound semiconductor layer; a fourth group III-V compound semiconductor layer provided on said third group III-V compound semiconductor layer; and an active device formed on said fourth group III-V compound semiconductor layer.
- 2. A compound semiconductor device as claimed in claim 1, wherein said second group III-V compound semiconductor layer has a thickness of about 500 nm.
- 3. A compound semiconductor device as claimed in claim 1, wherein said third group III-V compound semiconductor layer has a root mean square of surface roughness of 4.0 nm or less.
- 4. A compound semiconductor device as claimed in claim 1, wherein said Si substrate has a resistivity of 1000 Ω.cm or more.
- 5. A compound semiconductor device as claimed in claim 1 further comprising an insulating support substrate such that said support substrate carries thereon said Si substrate.
- 6. A compound semiconductor device as claimed in claim 1, wherein each of said first and second group III-V compound semiconductor layers contains oxygen therein.
- 7. A compound semiconductor device as claimed in claim 1, wherein said Si substrate contains oxidation-induced stacking faults with a density equal to or smaller than 30 cm−2.
- 8. A compound semiconductor device as claimed in claim 1, wherein said Si substrate contains oxidation-induced stacking faults with a density equal to or smaller than 10 cm−2.
- 9. A compound semiconductor device as claimed in claim 1, wherein said Si substrate contains oxidation-induced stacking faults with a density equal to or smaller than 3 cm−3.
- 10. A compound semiconductor device as claimed in claim 1, wherein said Si substrate contains oxidation-induced stacking faults with a density equal to or smaller than 1 cm−2.
- 11. A compound semiconductor device as claimed in claim 1, wherein said first group III-V compound semiconductor layer contains Sb as a group V element and wherein said first group III-V compound semiconductor layer is substantially free from As and P.
- 12. A compound semiconductor device as claimed in claim 11, wherein said first group III-V compound semiconductor layer has a composition selected from a group consisting of InSb, GaSb, AlSb and a mixed crystal thereof.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Divisional of U.S. application Ser. No. 08/619,249 filed Mar. 21, 1996 now U.S. Pat. No. 5,834,362 which is a Continuation-in-Part of U.S. application Ser. No. 08/520,939 filed Aug. 31, 1995, now abandoned.
US Referenced Citations (12)
Foreign Referenced Citations (3)
Number |
Date |
Country |
63-053914 |
Mar 1988 |
JP |
63-184320 |
Jul 1988 |
JP |
06-045249 |
Feb 1994 |
JP |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
08/520939 |
Aug 1995 |
US |
Child |
08/619249 |
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US |