Patent Application
20240194745
Many types of power semiconductor devices utilize trench field plates for improving the breakdown and Rdson (on-state resistance) characteristics of the device. In some cases, the field plate trenches are ‘needle-shaped’ meaning the trench structure is narrow and long in a depth-wise direction of the semiconductor substrate in which the device is formed, as opposed to stripe-shaped trenches which have a longest linear dimension in a direction transverse to the depth-wise direction of the semiconductor substrate. In needle trench technologies, connecting the gate pad of the device to the gate electrodes in the active trenches is difficult due to termination structures having arrays of needle structures. The gate connection is typically implemented by a tungsten layer patterned with lithography and etch steps above the interlayer dielectric formed on the semiconductor substrate, and requires another layer of dielectric film above the tungsten layer with more lithography and etch steps.
Thus, there is a need for an improved design for connecting the gate pad of a semiconductor device with needle-shaped field plate trenches to the gate electrodes in the active trenches.
According to an embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate; a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric.
According to another embodiment of a semiconductor device, the semiconductor device comprises: a semiconductor substrate having an edge that extends between first and second main surfaces of the semiconductor substrate; a plurality of gate trenches extending from the first main surface into the semiconductor substrate in an active device region of the semiconductor substrate, each gate trench including a gate electrode insulated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches extending from the first main surface into the semiconductor substrate in both the active device region and a termination region of the semiconductor substrate that is devoid of fully functional transistor cells, the termination region having a recess formed in the first main surface; a shielding layer disposed in the recess in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric; polysilicon disposed in recesses formed in the shielding layer, the polysilicon being insulated from the semiconductor substrate by the shielding layer and electrically connected to the gate electrodes in the active device region.
According to an embodiment of a method of fabricating semiconductor devices from a semiconductor wafer, the method comprises: forming a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; forming a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; forming a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and forming a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
The embodiments described herein provide a gate interconnection design for semiconductor devices with needle-shaped field plate trenches. The gate interconnection design includes a polysilicon layer that forms the gate electrodes in an active device region of a semiconductor substrate and extends over at least part of a termination region of the semiconductor substrate. A shielding layer separates the polysilicon layer from the semiconductor substrate in the termination region. The shielding layer has a higher dielectric strength than just the gate dielectric that separates the gate electrodes in the active device region from the semiconductor substrate. The gate interconnection design avoids a costly tungsten gate interconnection layer and the overlying dielectric film. The termination structure described herein has a region of sub-surface dielectric material that shields the gate (e.g., polysilicon) material from exposure to the high voltage of the drain.
Described next with reference to the figures are embodiments of the gate interconnection design and methods of producing the gate interconnection design.
The semiconductor substrate 102 includes an active device region 104 and a termination region 106 that separates the active device region 104 from an edge 108 of the semiconductor substrate 102, the edge 108 extending between first and second main surfaces 111, 113 of the semiconductor substrate 102. The active device region 104 is where fully functional device cells are formed. The termination region 106 is devoid of fully functional device cells and reduces electrical field crowding at termination.
Transistor cells 110 are formed in the active device region 104. The transistor cells 110 are electrically coupled in parallel to form a vertical power transistor such as a vertical power MOSFET, an IGBT (insulated gate bipolar transistor), a JFET (junction FET), etc. Only a few transistor cells 110 are shown in the partial view of
In the case of a vertical power transistor, a drain or collector 112 of the vertical power transistor is disposed at the backside of the semiconductor substrate 102. Each transistor cell 110 includes a source/emitter region 114 of a first conductivity type and a body region 116 of a second conductivity type opposite the first conductivity type. The source/emitter region 114 of each transistor cell 110 of the first type is separated from a drift zone 118 of the first conductivity type by the corresponding body region 116.
The first conductivity is n-type and the second conductivity type is p-type for an n-channel device formed by the transistor cells 110, whereas the first conductivity is p-type and the second conductivity type is n-type for a p-channel device formed by the transistor cells 110. For either an n-channel device or a p-channel device, the source/emitter region 114 and the body region 116 form part of a transistor cell 110 and the transistor cells 110 are electrically connected in parallel between source (S)/emitter (E) and drain (D)/collector (C) terminals of the semiconductor device 100 to form a power transistor.
The body regions 116 of the transistor cells 110 may include a body contact region 117 of the second conductivity type and having a higher doping concentration than the body regions 116, to provide an ohmic connection with a source/emitter metallization 122 through a contact structure 124 that extends through an interlayer dielectric 126 that separates the source/emitter metallization 122 from the semiconductor substrate 102. The source/emitter regions 114 of the transistor cells 110 are also electrically connected to the source/emitter metallization 122 through the contact structure 124.
Each transistor cell 110 of the semiconductor device 100 also includes gate structures 128, with needle-shaped field plate trenches 130 between neighboring ones of the gate structures 128. The term ‘needle-shaped’ as used herein means a structure that is narrow and long in a depth-wise direction (z direction in
The needle-shaped field plate trenches 130 extend from the first main surface 111 of the semiconductor substrate 102 and into the semiconductor substrate 102 in both the active device region 104 and the termination region 106. Field plates 132 are disposed in the needle-shaped field plate trenches 130 and electrically connected to the source/emitter metallization 122 through the contact structure 124. A field dielectric insulating material 134 separates the field electrodes 132 from the semiconductor material of the semiconductor substrate 102.
In
The gate electrodes 136 in the active device region 104 of the semiconductor substrate 102 are electrically connected to a gate terminal (G) through, e.g., a gate metallization 140 and a (gate) polysilicon layer 142. The gate metallization 140 may be part of a structured power metallization 143 that also includes the source/emitter metallization 122 which is separated from the gate metallization 140. The structured power metallization 143 may include a thick power metal layer 145 that comprises Cu, Al, AlCu, AlSiCu, etc., a diffusion barrier and/or adhesion promoter 147 such as Ti and/or TiN below the thick power metal layer 145, and a tungsten layer 149 between the thick power metal layer 145 and the diffusion barrier and/or adhesion promoter 147.
The gate polysilicon layer 142 is disposed below the structured power metallization and forms the gate electrodes 136 in the active device region 104 and extends over at least part of the termination region 106. A shielding layer 146 separates the gate polysilicon layer 142 from the semiconductor substrate 102 in the termination region 106 and has a higher dielectric strength than just the gate dielectric 138.
In one embodiment, the first main surface 111 of the semiconductor substrate 102 has a recess 148 in the termination region 106 and the shielding layer 146 is an oxide disposed in the recess 148. For example, the shielding layer 146 may be an STI (shallow trench isolation) oxide. The first main surface 111 of the semiconductor substrate 102 and the upper surface 150 of the shielding layer oxide 146 may be coplanar and the gate polysilicon layer 142 may lie in the same plane above both the active device region 104 and the termination region 106, e.g., as shown in
Separately or in combination, the shielding layer 146 may comprise a first oxide 152 that contacts the semiconductor substrate 102 in the termination region 106 and a second oxide 154 formed on the first oxide 152. If the gate oxide 138 is deposited, the second oxide 154 of the shielding layer 146 may be identical to the gate oxide 138. If, however, the gate oxide 138 is thermally grown, then the gate oxide 138 is at interface of the substrate 102 and the shielding layer 146 and the second oxide 154 of the shielding layer 146 may be different than the gate oxide 138. The gate oxide 138 instead may be a mixture of thermal and deposited oxide, such that part of the second oxide 154 of the shielding layer 146 may be identical to the gate oxide 138 and another part of the second oxide 154 may be different than the gate oxide 138.
As shown in
A blanket power metal layer 145 that comprises Cu, Al, AlCu, AlSiCu, etc. is deposited on the blanket tungsten layer 149. The blanket power metal layer 145 is substantially thicker than the blanket tungsten layer 149 and the blanket diffusion barrier and/or adhesion promoter 147. For example, the blanket diffusion barrier and/or adhesion promoter 147 may comprise a Ti layer having a thickness of about 30 nm and a TiN layer having a thickness of about 40 nm. The blanket tungsten layer 149 may be about 300 nm thick. The blanket power metal layer 145 may be about 5 μm thick. These are just examples, though, and other thicknesses fall within the scope of the gate interconnection design embodiments described herein.
The blanket metal layers 145, 147, 149 of the power metallization 143 are then patterned by etching to define the gate metallization 140 and the source/emitter metallization 122 which are electrically isolated from one another. At least part of the gate metallization 140 forms a gate contact pad for external contacting by a gate conductor (not shown) such as one or more bond wires or a metal clip. The gate pad contact pad 140 is electrically connected to the polysilicon layer 142 in the termination region 106 and thus to the gate electrodes 136 in the active device region 104. At least part of the source/emitter metallization 122 forms a source/emitter contact pad for external contacting by a source/emitter conductor (not shown) such as a plurality of bond wires or a metal clip. The source/emitter pad contact pad 122 is electrically connected to the source and body regions 114, 116 in the active device region 104 and to the field electrodes 132 in both the termination region 106 and the active device region 104.
Similar to what is shown in
Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.
Example 1. A semiconductor device, comprising: a semiconductor substrate; a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric.
Example 2. The semiconductor device of example 1, wherein the plurality of needle-shaped field plate trenches extends from a first main surface of the semiconductor substrate into the semiconductor substrate, wherein the first main surface has a recess in the termination region, and wherein the shielding layer is an oxide disposed in the recess.
Example 3. The semiconductor device of example 2, wherein the first main surface of the semiconductor substrate and an upper surface of the oxide are coplanar, and wherein the polysilicon layer lies in a same plane above both the active device region and the termination region.
Example 4. The semiconductor device of any of examples 1 through 3, wherein the shielding layer is an oxide, and wherein the oxide is disposed partly below the first main surface and partly above the first main surface in the termination region.
Example 5. The semiconductor device of any of examples 1 through 4, wherein the plurality of needle-shaped field plate trenches extends from a first main surface of the semiconductor substrate into the semiconductor substrate, wherein the shielding layer is an oxide disposed on the first main surface in the termination region, wherein the polysilicon layer lies in a first plane above the active device region and in a second plane above the termination region, and wherein the second plane is spaced further from the first main surface than the first plane.
Example 6. The semiconductor device of any of examples 1 through 5, wherein the shielding layer comprises a first oxide that contacts the semiconductor substrate in the termination region and a second oxide formed on the first oxide.
Example 7. The semiconductor device of any of examples 1 through 6, wherein the plurality of needle-shaped field plate trenches extends from a first main surface of the semiconductor substrate into the semiconductor substrate, and wherein at least some of the needle-shaped field plate trenches in the termination region extend through the shielding layer.
Example 8. The semiconductor device of example 7, wherein a first subset of the needle-shaped field plate trenches in the termination region extend through the shielding layer, and wherein a second subset of the needle-shaped field plate trenches in the termination region extend only in semiconductor material.
Example 9. The semiconductor device of any of examples 1 through 8, wherein the polysilicon layer transitions from a first level in the active device region to a second level in the termination region, and wherein the first level is closer to the semiconductor substrate than the second level.
Example 10. The semiconductor device of any of examples 1 through 9, wherein: the semiconductor substrate has an edge that extends between first and second main surfaces of the semiconductor substrate; the termination region is interposed between the active device region and the edge; the plurality of needle-shaped field plate trenches extends from the first main surface into the semiconductor substrate; the gate electrodes are disposed above the first main surface; and the polysilicon layer lies in a same plane above both the active device region and the termination region.
Example 11. The semiconductor device of any of examples 1 through 10, wherein: the semiconductor substrate has an edge that extends between first and second main surfaces of the semiconductor substrate; the termination region is interposed between the active device region and the edge; the plurality of needle-shaped field plate trenches extend from the first main surface into the semiconductor substrate; the gate electrodes are disposed above the first main surface; the shielding layer is a dielectric material disposed on the first main surface in the termination region; and the polysilicon layer lies in a lower plane above the active device region and in a higher plane above the termination region.
Example 12. A semiconductor device, comprising: a semiconductor substrate having an edge that extends between first and second main surfaces of the semiconductor substrate; a plurality of gate trenches extending from the first main surface into the semiconductor substrate in an active device region of the semiconductor substrate, each gate trench including a gate electrode insulated from the semiconductor substrate by a gate dielectric; a plurality of needle-shaped field plate trenches extending from the first main surface into the semiconductor substrate in both the active device region and a termination region of the semiconductor substrate that is devoid of fully functional transistor cells, the termination region having a recess formed in the first main surface; a shielding layer disposed in the recess in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric; polysilicon disposed in recesses formed in the shielding layer, the polysilicon being insulated from the semiconductor substrate by the shielding layer and electrically connected to the gate electrodes in the active device region.
Example 13. A method of fabricating semiconductor devices from a semiconductor wafer, the method comprising: forming a plurality of transistors cells in an active device region of the semiconductor substrate, each transistor cell having a gate electrode separated from the semiconductor substrate by a gate dielectric; forming a plurality of needle-shaped field plate trenches in the active device region and in a termination region of the semiconductor substrate that is devoid of fully functional transistor cells; forming a polysilicon layer that forms the gate electrodes in the active device region and extends over at least part of the termination region; and forming a shielding layer that separates the polysilicon layer from the semiconductor substrate in the termination region, the shielding layer having a higher dielectric strength than just the gate dielectric.
Example 14. The method of example 13, wherein forming the shielding layer comprises: etching a recess into a first main surface of the semiconductor substrate in the termination but not in the active device region; and filling the recess with an oxide.
Example 15. The method of example 14, further comprising: planarizing the oxide such that the first main surface of the semiconductor substrate and an upper surface of the oxide are coplanar before forming the plurality of transistors cells, the plurality of needle-shaped field plate trenches, and the polysilicon layer.
Example 16. The method of example 14 or 15, wherein forming the polysilicon layer comprises: forming a gate oxide layer on the oxide in the recess and on the first main surface elsewhere; and depositing polysilicon on the gate oxide material in both the active device region and the termination region.
Example 17. The method of example 16, wherein forming the plurality of needle-shaped field plate trenches comprises: forming an interlayer dielectric on the polysilicon layer; etching through the interlayer dielectric, the polysilicon layer, and the gate oxide layer to form material stacks on the first main surface in the active device region and on the oxide in the recess in the termination region; and etching into the semiconductor substrate between the material stacks, wherein the etching in the termination region includes etching through the oxide in the recess.
Example 18. The method of example 17, wherein forming the plurality of transistors cells comprises: implanting body regions and source regions into the semiconductor substrate between the material stacks in the active device region, wherein the portion of the polysilicon layer that remains in the material stacks in the active device region forms planar gate electrodes that are separated from the first main surface by the gate oxide layer.
Example 19. The method of example 18, further comprising: after implanting the body regions and the source regions and before etching into the semiconductor substrate between the material stacks to form the plurality of needle-shaped field plate trenches, forming an oxide spacer on sidewalls of the material stacks and a nitride spacer on the oxide spacer.
Example 20. The method of any of examples 17 through 19, further comprising: forming an opening that extends through the interlayer dielectric to expose the polysilicon layer in the termination region; forming a blanket tungsten layer over the semiconductor wafer so that the blanket tungsten layer electrically contacts field electrodes in the needle-shaped field plate trenches and source and body regions of the transistor cells between the material stacks, and electrically contacts the polysilicon layer through the opening that extends through the interlayer dielectric in the termination region; forming a blanket power metal layer on the blanket tungsten layer; and patterning the blanket power metal layer and the blanket tungsten layer to provide a first contact pad for the field electrodes and the source and body regions, and a second contact pad for the polysilicon layer.
Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
