This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. 2023-102705 filed on Jun. 22, 2023, the entire contents of which are incorporated by reference herein.
The present invention relates to semiconductor devices.
WO2022/054560A1 discloses a semiconductor device including a socket arranged on the inner side of an outer edge of a sealing member in a direction in which a semiconductor element and a metallic member overlap with each other, and discloses that the semiconductor device can be a power conversion device having three levels or multiple levels. JP2007-234693A discloses a semiconductor device including a positive-side external connection terminal and a negative-side external connection terminal separately overlapping with each other so as to be exposed on a top surface of the semiconductor device.
JP2004-153243A discloses a semiconductor device having a structure in which insulating sheets are inserted between the respective electrodes exposed on a top surface of a case. JP2022-67815A discloses a semiconductor device including a side-surface terminal and top-surface terminals.
JP2017-118816A discloses a three-level semiconductor module including three main terminals that are arranged parallel to each other inside the module.
Development in power semiconductor modules has been promoted that have a configuration in which a plurality of external terminals are deposited close to each other (laminated) so as to be opposed parallel to each other and project from a side surface of a sealing resin in order to reduce a wiring inductance. However, arranging the plural external terminals having the parts projecting from the sealing resin in a stepped manner so as to be connected to an external circuit impedes a reduction in the entire size of such a power semiconductor module.
In view of the foregoing problems, the present invention provides a semiconductor device including a plurality of external terminals arranged to be opposed parallel to each other while achieving a reduction in size.
An aspect of the present invention inheres in a semiconductor device including: an insulated circuit substrate; a semiconductor chip provided on a top surface side of the insulated circuit substrate; a sealing resin provided so as to seal the semiconductor chip; a first external terminal electrically connected to the semiconductor chip so as to be exposed on a first side surface of the sealing resin; a second external terminal electrically connected to the semiconductor chip and having a part opposed parallel to the first external terminal on an upper side of the first external terminal so as to be exposed on a top surface of the sealing resin; and a first insulating member interposed between the first external terminal and the second external terminal.
With reference to the drawings, first to sixth embodiments of the present invention will be described below.
In the drawings, the same or similar elements are indicated by the same or similar reference numerals. The drawings are schematic, and it should be noted that the relationship between thickness and planer dimensions, the thickness proportion of each layer, and the like are different from real ones. Moreover, in some drawings, portions are illustrated with different dimensional relationships and proportions. The first to sixth embodiments described below merely illustrate schematically devices and methods for specifying and giving shapes to the technical idea of the present invention, and the span of the technical idea is not limited to materials, shapes, structures, and relative positions of elements described herein.
Additionally, definitions of directions such as “upper and lower” and “left and right” in the following description are simply definitions for convenience of description, and do not limit the technological concept of the present invention. For example, when observing an object rotated by 90 degrees, the “upper and lower” is converted to “left and right” to be read, and when observing an object rotated by 180 degrees, the “upper and lower” are read reversed, which should go without saying.
In the following description, a “first main electrode” of a semiconductor chip means an electrode through which a main current flows into or flows out of the semiconductor chip. The “first main electrode” is assigned to any one of a source electrode or a drain electrode when the semiconductor chip implements a field-effect transistor (FET) or a static induction transistor (SIT). The “first main electrode” is assigned to any one of an emitter electrode or a collector electrode when the semiconductor chip implements an insulated-gate bipolar transistor (IGBT). The “first main electrode” is assigned to any one of an anode electrode or a cathode electrode when the semiconductor chip implements a static induction (SI) thyristor or a gate turn-off (GTO) thyristor. A “second main electrode” of the semiconductor chip is assigned to any one of the source electrode or the drain electrode, which is not assigned as the first main electrode, when the semiconductor chip implements the FET or the SIT. The “second main electrode” is assigned to any one of the emitter electrode or the collector electrode, which is not assigned as the first main electrode, when the semiconductor chip implements the IGBT. The “second main electrode” is assigned to any one of the anode electrode or the cathode electrode, which is not assigned as the first main electrode, when the semiconductor chip implement the SI thyristor or the GTO thyristor. That is, when the “first main electrode” is the source electrode, the “second main electrode” means the drain electrode. When the “first main electrode” is the emitter electrode, the “second main electrode” means the collector electrode. When the “first main electrode” is the anode electrode, the “second main electrode” means the cathode electrode.
A term “first external terminal” as recited in claims corresponds to one of a positive electrode terminal, a negative electrode terminal, an intermediate terminal, and an output terminal when the semiconductor device has a three-level configuration, and corresponds to one of the positive electrode terminal, the negative electrode terminal, and the output terminal when the semiconductor device has a two-level configuration. A term “second external terminal” as recited in claims corresponds to one of the positive electrode terminal, the negative electrode terminal, the intermediate terminal, and the output terminal other than that corresponding to the first external terminal when the semiconductor device has the three-level configuration, and corresponds to one of the positive electrode terminal, the negative electrode terminal, and the output terminal other than that corresponding to the first external terminal when the semiconductor device has the two-level configuration. A term “third external terminal” as recited in claims corresponds to one of the positive electrode terminal, the negative electrode terminal, the intermediate terminal, and the output terminal other than those corresponding to the first external terminal and the second external terminal when the semiconductor device has the three-level configuration, and corresponds to one of the positive electrode terminal, the negative electrode terminal, and the output terminal other than those corresponding to the first external terminal and the second external terminal when the semiconductor device has the two-level configuration. A term “fourth external terminal” as recited in claims corresponds to one of the positive electrode terminal, the negative electrode terminal, the intermediate terminal, and the output terminal other than those corresponding to the first external terminal to the third external terminal when the semiconductor device has the three-level configuration.
A semiconductor device according to a first embodiment is illustrated below with a power semiconductor module implementing a circuit for a single phase (a three-level circuit) of a three-level power conversion device (a three-level inverter).
The positive electrode terminal P is connected to a drain of a transistor T1. A source of the transistor T1 is connected to the output terminal O and a drain of a transistor T2. A source of the transistor T2 is connected to the negative electrode terminal N.
The intermediate terminal M is connected to a source of a transistor T3. A drain of the transistor T3 is connected to a drain of a transistor T4. A source of the transistor T4 is connected to the source of the transistor T1 and the drain of the transistor T2.
The transistors T1 to T4 are internally provided with body diodes D1 to D4, respectively, each serving as a freewheeling diode (FWD) connected in antiparallel. A capacitor C1 is connected between the positive electrode terminal P and the intermediate terminal M. A capacitor C2 is connected between the intermediate terminal M and the negative electrode terminal N.
As illustrated in
The positive electrode terminal 21 projects from the side surface of the sealing resin 7 and extends in one direction. The positive electrode terminal 21 includes a bonding region 21a to which an external circuit such as the capacitor C1 illustrated in
The negative electrode terminal 22 is arranged over the positive electrode terminal 21 with a plate-like (sheet-like) insulating member (insulating sheet) 61 interposed. The negative electrode terminal 22 projects from the side surface of the sealing resin 7 on the same side on which the positive electrode terminal 21 projects so as to extend in the direction substantially parallel to the extending direction of the positive electrode terminal 21. The negative electrode terminal 22 includes a bonding region 22a to which an external circuit such as the capacitor C2 illustrated in
The intermediate terminal 24 is exposed to an opening 7a provided on the top surface of the sealing resin 7. The intermediate terminal 24 includes a bonding region 24a to which the external circuits such as the capacitors C1 and C2 illustrated in
The output terminal 23 projects from the side surface of the sealing resin 7 on the opposite side of the positive electrode terminal 21 and the negative electrode terminal 22 so as to extend in the direction opposite to the extending direction of the positive electrode terminal 21 and the negative electrode terminal 22. The output terminal 23 includes a bonding region 23a, as schematically indicated by the broken line, to which an external circuit such as a load can be bonded by laser welding, for example. The bonding region 23a may be provided with a screw hole so as to be attached to the external circuit by screw fastening.
As illustrated in
The cooling plate 8 is bonded to the bottom surface of the insulated circuit substrate 1 via solder, sintered material, or thermal compound, for example. The cooling plate 8 includes copper (Cu), aluminum (Al), composite material (AlSiC) of Al and silicon carbide (SiC), and composite material (MgSiC) of magnesium (Mg) and silicon carbide (SiC), for example. The cooling plate 8 is not necessarily provided on the bottom surface of the insulated circuit substrate 1 so as to lead the bottom surface of the insulated circuit substrate 1 to be exposed on the bottom surface of the sealing resin 7. Alternatively, a cooling fin may be provided, instead of the cooling plate 8, on the bottom surface side of the insulated circuit substrate 1.
The insulated circuit substrate 1 may be a direct copper bonded (DCB) substrate or an active metal brazed (AMB) substrate, for example. The insulated circuit substrate 1 includes an insulating plate 11, conductive plates (conductive foils) 12a to 12c provided on the top surface side of the insulating plate 11, and a heat-releasing plate (a conductive foil) 13 provided on the bottom surface side of the insulating plate 11.
The insulating plate 11 as used herein can be a ceramic plate mainly including aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or boron nitride (BN), or a resin insulating layer including polymer material, for example. The heat-releasing plate 13 is not necessarily provided on the bottom surface side of the insulating plate 11 when the insulating plate 11 is the resin insulating layer. The conductive plates 12a to 12c and the heat-releasing plate 13 each include copper (Cu) and aluminum (Al), for example. The planar pattern, the number, and the arranged positions of the conductive plates 12a to 12c may be determined as appropriate.
The semiconductor chips 4a to 4d illustrated in
The semiconductor chips 4a to 4d are bonded onto the conductive plate 12a of the insulated circuit substrate 1 via bonding material (not illustrated) such as solder or sintered material. The semiconductor chips 4e to 4h and 4m to 4p are bonded onto the conductive plate 12b of the insulated circuit substrate 1 via bonding material (not illustrated) such as solder or sintered material. The semiconductor chips 4i to 4l are bonded onto the conductive plate 12c of the insulated circuit substrate 1 via bonding material (not illustrated) such as solder or sintered material.
The first embodiment is illustrated with the case in which the semiconductor chips 4a to 4p are each a metal-oxide-semiconductor field-effect-transistor (MOSFET). The semiconductor chips 4a to 4p may each be an insulated gate bipolar transistor (IGBT), a thyristor such as a static induction (SI) thyristor and a gate turn-off (GTO) thyristor, or a diode, for example. The semiconductor chips 4a to 4p are each made of a semiconductor substrate including material such as silicon (Si), silicon carbide (SIC), gallium nitride (GaN), and gallium oxide (Ga2O3). The arranged positions and the number of the semiconductor chips 4a to 4p may be determined as appropriate.
As illustrated in
The conductive plate 12a of the insulated circuit substrate 1 is bonded to the drain electrodes 41a and 41b of the semiconductor chips 4a and 4b via bonding material such as solder or sintered material. One end of a lead frame 26 is bonded to the source electrodes 42a and 42b of the semiconductor chips 4a and 4b via bonding material (not illustrated) such as solder or sintered material. The conductive plate 12b of the insulated circuit substrate 1 is bonded to the other end of the lead frame 26 via bonding material (not illustrated) such as solder or sintered material. Control terminals (not illustrated) are electrically connected to the gate electrodes of the semiconductor chips 4a and 4b via bonding wires (not illustrated). Control signals are applied to the gate electrodes of the semiconductor chips 4a and 4b through the control terminals so as to control ON-OFF states of current flowing between the drain electrodes 41a and 41b and the source electrodes 42a and 42b of the semiconductor chips 4a and 4b.
The semiconductor chip 4e includes a drain electrode 41e provided on the bottom surface side, and a source electrode 42e and a gate electrode (not illustrated) provided on the top surface side. The semiconductor chip 4f includes a drain electrode 41f provided on the bottom surface side, and a source electrode 42f and a gate electrode (not illustrated) provided on the top surface side.
The conductive plate 12b of the insulated circuit substrate 1 is bonded to the drain electrodes 41e and 41f of the semiconductor chips 4e and 4f via bonding material (not illustrated) such as solder or sintered material. The intermediate terminal 24 is bonded to the source electrodes 42e and 42f of the semiconductor chips 4e and 4f via bonding material (not illustrated) such as solder or sintered material. Control terminals (not illustrated) are electrically connected to the gate electrodes of the semiconductor chips 4e and 4f via bonding wires (not illustrated). Control signals are applied to the gate electrodes of the semiconductor chips 4e and 4f through the control terminals so as to control ON-OFF states of current flowing between the drain electrodes 41e and 41f and the source electrodes 42e and 42f of the semiconductor chips 4e and 4f.
The semiconductor chips 4c, 4d, and 4g to 4p illustrated in
The positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24 illustrated in
The positive electrode terminal 21 has a flat plate-like shape. The positive electrode terminal 21 is bonded to the conductive plate 12a of the insulated circuit substrate 1 by laser welding, for example. The positive electrode terminal 21 may be bonded to the conductive plate 12a of the insulated circuit substrate 1 via a conductive member such as a copper block or a lead frame, or may have a part bent into an L-like shape or a Z-like shape so as to be attached to the conductive plate 12a of the insulated circuit substrate 1. The positive electrode terminal 21 is electrically connected to the drain electrodes 41a and 41b on the lower side of the semiconductor chips 4a and 4b. The positive electrode terminal 21 is also electrically connected to the drain electrodes on the lower side of the semiconductor chips 4c and 4d illustrated in
As illustrated in the cross-sectional view of
As illustrated in
A large amount of current exceeding several hundreds of amperes flows through the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, and the intermediate terminal 24. A wiring inductance (L) needs to be reduced so as to suppress a surge voltage (V=L×di/dt), since the surge voltage is caused by an influence of the wiring inductance upon the turn ON/OFF operation of the current to result in damage to the semiconductor chips 4a to 4p if the surge voltage exceeds a breakdown voltage of the semiconductor chips 4a to 4p. While an increase in thickness and a decrease in length of the wire or a division of a plurality of current paths arranged in parallel is effective for reducing the inductance, an increase of influence of mutual electromagnetic induction to reduce an apparent inductance is effective such that the respective current paths are arranged close to each other (laminated) so as to be directed in the directions opposite to each other in both ways in order to reduce the size.
To deal with this, as illustrated in
As illustrated in
As illustrated in
The respective insulating members 61 and 62 as used herein can be an insulating sheet or can include insulating material having high insulating and heat-resistance properties such as polyimide or polyamide. The respective insulating members 61 and 62 may include epoxy resin or polyphenylene sulfide (PPS) resin instead. When the resin material is used for the respective insulating members 61 and 62, a plate-like (sheet-like) resin material may be interposed, or the respective terminals such as the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 may be prepared as an integrated component together with resin material by primary molding so as to be deposited on the respective semiconductor chips 4a to 4p. The respective insulating members 61 and 62 may have a smaller thickness than each of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24. The thickness of the respective insulating members 61 and 62 is in a range of 0.1 millimeters or greater and 1.0 millimeters or smaller, for example.
As illustrated in
As illustrated in
The output terminal 23 is electrically connected to the source electrodes 42a and 42b on the upper side of the semiconductor chips 4a and 4b and the drain electrodes 41e and 41f on the lower side of the semiconductor chips 4e and 4f. The output terminal 23 is also electrically connected to the source electrodes on the upper side of the semiconductor chips 4c and 4d and the drain electrodes on the lower side of the semiconductor chips 4g, 4h, and 4m to 4p illustrated in
The sealing resin 7 seals the insulated circuit substrate 1 and the respective semiconductor chips 4a to 4p and the like. The sealing resin 7 as used herein can include resin having insulating properties such as thermosetting silicone gel or epoxy resin.
As described above, the semiconductor device according to the first embodiment has the configuration in which the three terminals of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 are deposited close to each other (laminated) with the respective insulating members 61 and 62 interposed, and two of the positive electrode terminal 21 and the negative electrode terminal 22 on the lower side project from the side surface of the sealing resin 7, while the other intermediate terminal 24 on the uppermost side is exposed on the top surface of the sealing resin 7. This configuration can decrease the distance d1 and the thickness t1 of the part of the positive electrode terminal 21 and the negative electrode terminal 22 projecting from the sealing resin 7, so as to achieve a reduction in the entire size, as compared with a case in which three of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 project from the same side surface of the sealing resin 7.
An example of a method of manufacturing the semiconductor device according to the first embodiment is described below.
The heat-releasing plate 13 of the insulated circuit substrate 1 is bonded onto the cooling plate 8 illustrated in
Next, the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, the intermediate terminal 24, and the lead frame 26 are bonded onto the conductive plates 12a to 12c of the insulated circuit substrate 1 and the semiconductor chips 4a to 4p via bonding material such as solder or sintered material. The positive electrode terminal 21 and the negative electrode terminal 22 are deposited close to each other with the insulating member 61 interposed, and the negative electrode terminal 22 and the intermediate terminal 24 are deposited close to each other with the insulating member 62 interposed.
Next, the insulated circuit substrate 1, the semiconductor chips 4a to 4p, the positive electrode terminal 21, the negative electrode terminal 22, the output terminal 23, the intermediate terminal 24, the lead frame 26, and the insulating member 61 and the like are fixed (chucked) from the respective upper and lower sides with metal dies 91 and 92 (refer to
As illustrated in
A method of manufacturing the semiconductor device of the first comparative example forms the sealing resin 7 by transfer molding by use of the metal dies 91 and 92, as illustrated in
A semiconductor device of a second comparative example has the same configuration as the semiconductor device according to the first embodiment illustrated in
The configuration of the semiconductor device of the second comparative example inevitably increases the distance d3 and the thickness t3 of the part of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 projecting from the same side surface of the sealing resin 7, impeding a reduction in the entire size of the device.
The execution of resin molding upon manufacture without the outline and size changed can contribute to a standardization of components of the manufacturing device regardless of whether a two-level circuit or a three-level circuit is manufactured. The method of manufacturing the semiconductor device of the second comparative example, however, needs to change the shape of the metal dies, since the number of the terminals projecting from the same side surface of the sealing resin 7 is increased, and the distance d3 and the thickness t3 of the part of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 projecting from the sealing resin 7 are increased, which obstructs the outline of the metal dies 91 and 92 used for the transfer molding in the semiconductor device of the first comparative example illustrated in
In contrast, the configuration of the semiconductor device according to the first embodiment can contribute to the standardization of the manufacturing components so as to use the common metal dies 91 and 92 for the transfer molding in each of the semiconductor device according to the first embodiment illustrated in
A semiconductor device according to a second embodiment differs from the semiconductor device according to the first embodiment having the three-level circuit configuration illustrated in
The plan view (the top view) of the semiconductor device according to the second embodiment is the same as the plan view (the top view) of the semiconductor device of the first comparative example illustrated in
As illustrated in
As described above, the semiconductor device according to the second embodiment has the two-level circuit configuration including the positive electrode terminal 21 and the negative electrode terminal 22 deposited close to each other with the insulating member 61 interposed, in which the positive electrode terminal 21 on the lower side, which is one of the two terminals, projects from the side surface of the sealing resin 7, and the other negative electrode terminal 22 on the upper side is exposed on the top surface of the sealing resin 7. This configuration can decrease the distance d4 and the thickness t4 of the part of the positive electrode terminal 21 projecting from the sealing resin 7, so as to achieve a reduction in the entire size, as compared with a case in which both the positive electrode terminal 21 and the negative electrode terminal 22 project from the side surface of the sealing resin 7.
The cross-sectional view as viewed from direction A-A in
As described above, the semiconductor device according to the third embodiment has the configuration in which the negative electrode terminal 22 is deposited close to the positive electrode terminal 21 and the intermediate terminal 24 (laminated together), in which the positive electrode terminal 21 and the intermediate terminal 24 on the lower side project from the side surface of the sealing resin 7, while the negative electrode terminal 22 on the upper side is exposed on the top surface of the sealing resin 7. This configuration can decrease the distance d4 and the thickness t4 of the part of each of the positive electrode terminal 21 and the intermediate terminal 24 projecting from the sealing resin 7 (refer to
Further, the configuration of the semiconductor device according to the third embodiment can lead the outline illustrated in
The transfer molding for the semiconductor device according to the fourth embodiment uses the metal die 91 provided with a projection 91a, as illustrated in FIG. 20. The execution of the transfer molding while a part of the intermediate terminal 24 to be exposed on the top surface of the sealing resin 7 is in contact with the projection 91a of the metal die 91 provides the opening 7a in the sealing resin 7. The other configurations of the semiconductor device according to the fourth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and overlapping explanations are not repeated below.
As described above, the semiconductor device according to the fourth embodiment has the configuration in which the three terminals of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 are deposited close to each other (laminated) with the respective insulating members 61 and 62 interposed, and two of the positive electrode terminal 21 and the negative electrode terminal 22 on the lower side project from the side surface of the sealing resin 7, while the other intermediate terminal 24 on the uppermost side is exposed on the top surface of the sealing resin 7. This configuration can decrease the distance d1 and the thickness t1 of the part of the positive electrode terminal 21 and the negative electrode terminal 22 projecting from the sealing resin 7, so as to achieve a reduction in the entire size, as compared with a case in which three of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 project from the side surface of the sealing resin 7. Further, the configuration in which the top surface of the intermediate terminal 24 is recessed downward from the top surface of the sealing resin 7 leads a conductive member (not illustrated), which is to be connected to the intermediate terminal 24, to be fitted into the recessed shape, so as to facilitate the mutual positioning.
The transfer molding for the semiconductor device according to the fifth embodiment uses the metal die 91 provided with a recess 91b corresponding to the projection on the top surface side of the intermediate terminal 24, as illustrated in
As described above, the semiconductor device according to the fifth embodiment has the configuration in which the three terminals of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 are deposited close to each other (laminated) with the respective insulating members 61 and 62 interposed, and two of the positive electrode terminal 21 and the negative electrode terminal 22 on the lower side project from the side surface of the sealing resin 7, while the other intermediate terminal 24 on the uppermost side is exposed on the top surface of the sealing resin 7. This configuration can decrease the distance d1 and the thickness t1 of the part of the positive electrode terminal 21 and the negative electrode terminal 22 projecting from the sealing resin 7, so as to achieve a reduction in the entire size, as compared with a case in which three of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 project from the side surface of the sealing resin 7. Further, the configuration in which the top surface of the intermediate terminal 24 projects upward from the top surface of the sealing resin 7 can increase the thickness of the intermediate terminal 24, so as to suppress an increase in temperature of the insulating member 62 located immediately under a welding position when the intermediate terminal 24 and a conductive member (not illustrated) are bonded together by laser welding.
As described above, the semiconductor device according to the sixth embodiment has the configuration in which the three terminals of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 are deposited close to each other (laminated) with the respective insulating members 61 and 62 interposed, and two of the positive electrode terminal 21 and the negative electrode terminal 22 on the lower side project from the side surface of the sealing resin 7, while the other intermediate terminal 24 on the uppermost side is exposed on the top surface of the sealing resin 7. This configuration can decrease the distance d1 and the thickness t1 of the part of the positive electrode terminal 21 and the negative electrode terminal 22 projecting from the sealing resin 7, so as to achieve a reduction in the entire size, as compared with a case in which three of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 project from the side surface of the sealing resin 7.
As described above, the invention has been described according to the first to sixth embodiments, but it should not be understood that the description and drawings implementing a portion of this disclosure limit the invention. Various alternative embodiments of the present invention, examples, and operational techniques will be apparent to those skilled in the art from this disclosure.
For example, while the first, fourth, and sixth embodiments have been illustrated with the laminate wiring structure including the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 deposited in this order from the lower side, the deposited order may be changed as appropriate. The laminate wiring structure may include the positive electrode terminal 21, the intermediate terminal 24, and the negative electrode terminal 22 deposited in this order from the lower side, for example. Alternatively, the position of any of the positive electrode terminal 21, the negative electrode terminal 22, and the intermediate terminal 24 may be replaced with the position of the output terminal 23.
While the second embodiment has been illustrated with the laminate wiring structure including the positive electrode terminal 21 and the negative electrode terminal 22 deposited sequentially from the lower side, the laminate wiring structure may include the negative electrode terminal 22 and the positive electrode terminal 21 deposited sequentially from the lower side. Alternatively, the position of either the positive electrode terminal 21 or the negative electrode terminal 22 may be replaced with the position of the output terminal 23.
While the first to sixth embodiments have been illustrated with the semiconductor device having the two-level circuit or three-level circuit configuration, the present invention may also be applied to a semiconductor device implementing a multiple-level circuit such as a four-level circuit.
The configurations disclosed in the first to sixth embodiments may be combined as appropriate within a range that does not contradict with the scope of the respective embodiments. As described above, the invention includes various embodiments of the present invention and the like not described herein. Therefore, the scope of the present invention is defined only by the technical features specifying the present invention, which are prescribed by claims, the words and terms in the claims shall be reasonably construed from the subject matters recited in the present specification.
Number | Date | Country | Kind |
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2023-102705 | Jun 2023 | JP | national |