This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-047150, filed on Mar. 22, 2021, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a semiconductor device.
There is provided a surface mount type package that enables surface mounting of a semiconductor device on a wiring board to mount the semiconductor device on the wiring board at a high density. As the surface mount type package, for example, a MAP (Mold Array Package) type SON (Small Outlined Non-leaded Package) and a QFN (Quad Flat Non-leaded Package) are known. In the related art, there is known a semiconductor device to which a MAP type QFN is applied. In the related art, the semiconductor device includes a semiconductor chip, a die pad, leads, bonding wires, and a sealing resin. The semiconductor chip is bonded to the die pad. The leads are placed around the die pad. The bonding wires electrically connect the semiconductor chip and the leads. The sealing resin seals the semiconductor chip, the die pad, the leads, and the bonding wires.
A higher performance and a higher quality of a semiconductor device require not only a higher performance and a higher quality of a semiconductor chip, but also modification of a package structure of a semiconductor device.
Some embodiments of the present disclosure provide a semiconductor device with a higher performance and a higher quality.
According to some embodiments of the present disclosure, there is provided a semiconductor device, including: a semiconductor element having an element main surface and an element back surface spaced apart from each other in a thickness direction, and including a plurality of main surface electrodes arranged on the element main surface; a die pad on which the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in a first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member, and configured to electrically connect the plurality of main surface electrodes and the plurality of leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the plurality of leads, and the plurality of connecting members, and having a rectangular shape when viewed in the thickness direction, wherein each of the plurality of leads is configured to entirely overlap with the resin member when viewed in the thickness direction, and arranged along an outer edge of the resin member when viewed in the thickness direction, wherein the at least one first lead has a first pad surface and includes a plurality of first portions and a second portion, wherein the first pad surface includes a plurality of openings and spans the plurality of first portions and the second portion, wherein each of the plurality of first portions has a first back surface facing a side opposite to the first pad surface, wherein the second portion has a second back surface facing the side opposite to the first pad surface and located closer to the first pad surface than the first back surface in the thickness direction, wherein the plurality of first portions includes a pair of outer portions located at both ends of the at least one first lead in a second direction orthogonal to the thickness direction and the first direction, and an inner portion interposed between the pair of outer portions in the second direction, and wherein the first connecting member is bonded to the first pad surface in the inner portion.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.
Embodiments of a semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, the same or similar elements are designated by the same reference numerals and duplicated description thereof will be omitted. The terms such as “first,” “second,” “third,” and the like in the present disclosure are used merely as labels and are not necessarily intended to indicate an order of those objects.
In the present disclosure, “a certain object A being formed in a certain object B” and “a certain object A being formed on a certain object B” include “the certain object A being formed directly in the certain object B” and “the certain object A being formed in the certain object B with another object interposed between the certain object A and the certain object B,” unless otherwise specified. Similarly, “a certain object A being arranged in a certain object B” and “a certain object A being arranged on a certain object B” include “the certain object A being arranged directly in the certain object B” and “the certain object A being arranged in the certain object B with another object interposed between the certain object A and the certain object B,” unless otherwise specified. Similarly, “a certain object A being positioned on a certain object B” includes “the certain object A being positioned on the certain object B with the certain object A in contact with the certain object B” and “the certain object A being positioned on the certain object B with another object interposed between the certain object A and the certain object B,” unless otherwise specified. In addition, “a certain object A overlapping with a certain object B as viewed in a certain direction” includes “the certain object A overlapping with the entirety of the certain object B” and “the certain object A overlapping with a part of the certain object B,” unless otherwise specified.
For convenience of explanation, the thickness direction of each of the semiconductor element 1, the resin member 2, the die pad 3, and the plurality of leads 4 is referred to as “thickness direction z.” One side in the thickness directions z may be referred to as an upper side, and the other side may be referred to as a lower side. Further, in the following description, “in a plan view” refers to being viewed along the thickness direction z. The direction orthogonal to the thickness direction z is referred to as “first direction y.” The first direction y is the vertical direction in the plan view (see
The semiconductor device A1 is a surface mount type package. The package structure of the semiconductor device A1 is, for example, a MAP type QFN. The semiconductor device A1 has a rectangular shape in the plan view. In the semiconductor device A1, the dimension in the first direction y is, for example, 3 mm or more and 12 mm or less, and the dimension in the second direction x is, for example, 3 mm or more and 12 mm or less. Further, in the semiconductor device A1, the dimension in the thickness direction z is, for example, 0.5 mm or more and 1.5 mm or less.
The semiconductor element 1 is an element that exerts an electrical function of the semiconductor device A1. The semiconductor element 1 has a rectangular shape in the plan view. The semiconductor element 1 is, for example, an integrated circuit element, but may be an active function element, a passive function element, or the like. In the present embodiment, the semiconductor element 1 is a power IC and includes a power component 101 and a control circuit component 102 as shown in
As shown in
As shown in
The semiconductor element 1 is bonded to the die pad 3 by, for example, a bonding material (not shown). The bonding material may be insulating or conductive. However, when the electrodes are arranged on the element back surface 10b of the semiconductor element 1, the semiconductor element 1 is bonded to the die pad 3 by a conductive bonding material, such that the electrodes arranged on the element back surface 10b are electrically connected to the die pad 3 via the conductive bonding material.
The resin member 2 is a sealing material that protects the semiconductor element 1. The resin member 2 is made of an insulating resin material. The resin material is, for example, a black epoxy resin. The resin member 2 covers, for example, the semiconductor element 1, a part of the die pad 3, parts of a plurality of leads 4, parts of the plurality of third leads 43, and the plurality of connecting members 7. The resin member 2 has a rectangular shape in the plan view. The resin member 2 has a resin main surface 21, a resin back surface 22, a pair of first resin side surfaces 23, and a pair of second resin side surfaces 24.
As shown in
The pair of first resin side surfaces 23 and the pair of second resin side surfaces 24 are connected to both the resin main surface 21 and the resin back surface 22, respectively, and are interposed between the resin main surface 21 and the resin back surface 22 in the thickness direction z. The pair of first resin side surfaces 23 and the pair of second resin side surfaces 24 respectively extend upward from the resin back surface 22 and stand upright in the illustrated example. The pair of first resin side surfaces 23 are spaced apart from each other in the first direction y and are arranged substantially in parallel. The pair of first resin side surfaces 23 face opposite sides. The pair of second resin side surfaces 24 are spaced apart from each other in the second direction x and are arranged substantially in parallel. The pair of second resin side surfaces 24 face opposite sides. As shown in
The semiconductor element 1 is mounted on the die pad 3. The die pad 3 has a rectangular shape in the plan view. The die pad 3 is located at the center of the semiconductor device A1 in the plan view. The die pad 3 is made of, for example, copper or a copper alloy.
As shown in
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As shown in
The first portion 31 is a portion where the semiconductor element 1 is mounted. As shown in
As shown in
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As shown in
The third portion 33 extends from one of the pair of end edges 310b of the first portion 31 and extends to one of the pair of end edges 301b of the die pad main surface 30a. In the illustrated example, the third portion 33 is connected to the central portion of one of the pair of end edges 310b in the first direction y. As shown in
The fourth portion 34 extends from the other of the pair of end edges 310b of the first portion 31 and extends to the other of the pair of end edges 301b of the die pad main surface 30a. In the illustrated example, the fourth portion 34 is connected to the central portion of the other of the pair of end edges 310b in the first direction y. As shown in
As shown in
The die pad 3 includes a plurality of recesses 35. As shown in
The die pad 3 is formed with a pair of clamp marks 39. Each of the pair of clamp marks 39 is recessed in the thickness direction z from the die pad main surface 30a. Each clamp mark 39 is a pressing mark formed by a clamp member described later and exhibits a scratch-like shape slightly recessed from the die pad main surface 30a. One pair of clamp marks 39 is formed on each of the third portion 33 and the fourth portion 34. For example, the pair of clamp marks 39 are formed at the center of the third portion 33 in the plan view and the center of the fourth portion 34 in the plan view, respectively. The clamp marks 39 may not be formed on the die pad 3.
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The plurality of leads 4 (the plurality of first side leads 41 and the plurality of second side leads 42) includes first leads 5 and second leads 6. In the semiconductor device A1, as shown in
As shown in
In each first lead 5, the first pad surface 50a faces one side (upper side) in the thickness direction z and faces the same side as the element main surface 10a, as shown in
As shown in
As shown in
In the semiconductor device A1, as shown in
The first pad surface 50a includes a plurality of openings 503, as shown in
As shown in
In each first lead 5, the plurality of first portions 51 is arranged in the first width direction. As shown in
In each first lead 5, the plurality of first portions 51 includes a pair of outer portions 511 and one or more inner portions 512 (two inner portions 512 in the semiconductor device A1), as shown in
As shown in
In each first lead 5, the second portion 52 is connected to each of the plurality of first portions 51. As shown in
In each first lead 5, the second portion 52 includes a plurality of connecting portions 521 and a connecting portion 522, as shown in
As shown in
Each first lead 5 includes a plurality of recesses 55. As shown in
In the semiconductor device A1, each first lead 5 is formed with a notch 505 as shown in
Each first lead 5 is formed with a pair of clamp marks 59. Each of the pair of clamp marks 59 is recessed in the thickness direction z from the first pad surface 50a. Each clamp mark 59 is a pressing mark formed by a clamp member described later and exhibits a scratch-like shape slightly recessed from the first pad surface 50a. One pair of clamp marks 59 is formed on each of one pair of outer portions 511. In some embodiments, as shown in
The second lead 6 is electrically connected to the second main surface electrode 13 of the semiconductor element 1 via the connecting member 7 (second connecting member 72). As shown in
In each second lead 6, the second pad surface 60a faces the same side as the first pad surface 50a. Therefore, the second pad surface 60a faces one side (upper side) in the thickness direction z. The connecting member 7 (second connecting member 72) is bonded to the second pad surface 60a. The second pad surface 60a is subjected to, for example, a process of plating a base with a Ni layer and an Ag layer in the named order, but such a process of plating may not be performed or a process of plating with other conductive materials may be performed. The second pad surface 60a has an end edge 601 and an end edge 602, as shown in
The end edge 601 overlaps with the outer edge 20 of the resin member 2 when viewed in the thickness direction z. The direction in which the end edge 601 extends is referred to as a “second width direction.” In each of the second leads 6 of the plurality of first side leads 41, the second width direction coincides with the second direction x, and in each of the second leads 6 of the plurality of second side leads 42, the second width direction coincides with the first direction y.
The end edge 602 extends from the end edge 601 toward the die pad 3 while being orthogonal to the end edge 601 when viewed in the thickness direction z. The direction in which the end edge 602 extends is referred to as a “second length direction.” In each of the second leads 6 of the plurality of first side leads 41, the second length direction coincides with the first direction y, and in each of the second leads 6 of the plurality of second side leads 42, the second length direction coincides with the second direction x. As shown in
In each second lead 6, the connecting member 7 (second connecting member 72) is bonded to the first portion 61 as shown in
In each second lead 6, the second portion 62 is connected to the first portion 61, as shown in
As shown in
As shown in
The plurality of connecting members 7 electrically connects two portions spaced apart from each other. Each of the plurality of connecting members 7 electrically connects any one of the plurality of main surface electrodes 11 and any one of the plurality of leads 4. The plurality of connecting members 7 includes a plurality of first connecting members 71 and a plurality of second connecting members 72.
Each of the plurality of first connecting members 71 is, for example, a bonding wire, and contains aluminum or an aluminum alloy as a constituent material. Each of the plurality of first connecting members 71 is bonded to any one of the plurality of first main surface electrodes 12 and any one of the plurality of first leads 5 to electrically connect them. Each first connecting member 71 is bonded by, for example, wedge bonding. The material and bonding method of each first connecting member 71 are not limited to the above-mentioned examples. For example, the constituent material of each first portion 61 may include gold or a gold alloy, or copper or a copper alloy instead of aluminum or an aluminum alloy. Further, each first connecting member 71 may be bonded by ball bonding. In addition, each of the plurality of first connecting members 71 may be, for example, a bonding ribbon instead of the bonding wire.
Each of the plurality of second connecting members 72 is, for example, a bonding wire, and the constituent material thereof includes gold or a gold alloy, or copper or a copper alloy. Each of the plurality of second connecting members 72 is bonded to any one of the plurality of second main surface electrodes 13 and any one of the plurality of second leads 6 to electrically connect them. Each second connecting member 72 is bonded by, for example, ball bonding. The material and bonding method of each second connecting member 72 are not limited to the above-mentioned examples.
In the examples shown in
In the semiconductor device A1, as described above, each first connecting member 71 is bonded by wedge bonding. In the wedge bonding, the first connecting member 71 and an object to be bonded are bonded by applying ultrasonic vibration while pressing the first connecting member 71 against the object to be bonded (the first main surface electrode 12 and the first lead 5). The object to be bonded is fixed with a clamp member to suppress the swing of the object to be bonded due to the pressing force and ultrasonic vibration at this time. The clamp member has tip portions formed in the shape of a thin rod, and the object to be bonded is fixed by pressing the object to be bonded with the tip portions. In the present embodiment, each first connecting member 71 is bonded to the first main surface electrode 12 and the first lead 5. Therefore, the die pad 3 and the first lead 5 are fixed by the clamp member. At this time, by pressing the die pad 3 with the clamp member (the tip portions thereof), a pair of clamp marks 39 are formed by the pressing force of the clamp member. Further, by pressing the first lead 5 with the clamp member (the tip portions thereof), a pair of clamp marks 59 are formed by the pressing force of the clamp member. Even when the second connecting member 72 is bonded, ultrasonic vibration may be applied while pressing the second connecting member 72 against the object to be bonded (the main surface electrode 11 and the second lead 6). However, the pressing force and the ultrasonic vibration at that time are weaker than the pressing force and ultrasonic vibration when bonding the first connecting member 71. The clamp member may not be used when bonding the second connecting member 72. The bonding of each second connecting member 72 is performed after the bonding of each first connecting member 71.
The actions and effects of the semiconductor device A1 are as follows.
In the semiconductor device A1, the first lead 5 has the first pad surface 50a and includes the first portion 51 and the second portion 52. The first pad surface 50a spans the first portion 51 and the second portion 52. The back surface 52a of the second portion 52 is located closer to the first pad surface 50a than the back surface 51a of the first portion 51 in the thickness direction z. In this configuration, the second portion 52 is thinner than the first portion 51. Therefore, when the first connecting member 71 is bonded to the second portion 52, the first lead 5 may be deformed or cracked. This is because when the first connecting member 71 is bonded, the first connecting member 71 is pressed against the first lead 5 so that the pressing force is applied to the first lead 5 to generate stress in the first lead 5. Further, at the time of bonding the first connecting member 71, the first lead 5 may be pressed by the clamp member to fix the first lead 5. At this time, if the second portion 52 is pressed by the clamp member, the first lead 5 may be deformed or cracked due to the pressing force of the clamp member. If the first lead 5 is deformed by the pressing force of the clamp member, it may not be possible to secure an appropriate bonding strength for bonding the first connecting member 71. Therefore, in the semiconductor device A1, by forming the plurality of openings 503 on the first pad surface 50a, it is possible to determine the position of the first portion 51 with reference to the plurality of openings 503. That is, the semiconductor device A1 can determine the position suitable for bonding the first connecting member 71 and the position suitable for clamping with the clamp member. Accordingly, the semiconductor device A1 can suppress deformation and cracking of the first lead 5. This may be a package structure for achieving a high quality.
In the semiconductor device A1, the plurality of openings 503 includes the plurality of first openings 503a and the plurality of second openings 503b. According to this configuration, the regions to be pressed by the clamp member (the positions of the pair of outer portions 511) can be determined by the plurality of first openings 503a, and the region to be bonded with the first connecting member 71 (the position of the inner portion 512) can be determined by the plurality of second openings 503b. For example, in the example shown in
In the semiconductor device A1, the die pad 3 has the die pad main surface 30a and includes the first portion 31, the second portion 32, the third portion 33, and the fourth portion 34. The die pad main surface 30a spans the first portion 31, the second portion 32, the third portion 33, and the fourth portion 34. The back surface 31a of the first portion 31, the back surface 33a of the third portion 33, and the back surface 34a of the fourth portion 34 are flush with one another, and the back surface 32a of the second portion 32 is located on the side of the die pad main surface 30a in the thickness direction z from the back surface 31a. In this configuration, the second portion 32 is thinner than the first portion 31, and the third portion 33 and the fourth portion 34 have the same thickness as the first portion 31. At the time of bonding the first connecting member 71, the die pad 3 (and the semiconductor element 1 mounted thereon) may be fixed by, for example, a clamp member. At this time, the clamp member presses the periphery of the first portion 31 on which the semiconductor element 1 is mounted. Unlike the semiconductor device A1, in a semiconductor device in which the die pad 3 does not include the third portion 33 and the fourth portion 34, the second portion 32 is arranged on the entire circumference of the first portion 31. In this case, the second portion 32 is pressed by the clamp member to fix the die pad 3. However, since the second portion 32 is thinner than the first portion 31, the die pad 3 may be deformed or cracked due to the pressing force of the clamp member. When the die pad 3 is deformed by the pressing force of the clamp member, the semiconductor element 1 mounted on the die pad 3 may be peeled off. Therefore, in the semiconductor device A1, the third portion 33 and the fourth portion 34 can be pressed with the clamp member by providing the third portion 33 and the fourth portion 34 having the same thickness as the first portion 31 around the first portion 31. Accordingly, the semiconductor device A1 can suppress deformation and cracking of the die pad 3. This may be a package structure for achieving a high quality.
In the semiconductor device A1, when the first connecting member 71 is bonded to the first main surface electrode 12, the semiconductor element 1 is fixed by fixing the third portion 33 and the fourth portion 34 with the clamp member. Therefore, in the semiconductor device A1, the third portion 33 and the fourth portion 34 are arranged to sandwich the first portion 31 in the second direction x. At this time, in the plan view, the line segment L1 connecting the center of the third portion 33 and the center of the fourth portion 34 overlaps with the semiconductor element 1. According to this configuration, when the die pad 3 is fixed by the clamp member, the semiconductor element 1 can be fixed in a stable posture. That is, the semiconductor device A1 may have a package structure for appropriately fixing the semiconductor element 1.
In the semiconductor device A1, the pair of openings 302 are formed on the die pad main surface 30a of the die pad 3. The pair of openings 302 are formed, for example, at the boundary between the first portion 31 and the third portion 33 and the boundary between the first portion 31 and the fourth portion 34. According to this configuration, it is possible to determine the positions of the third portion 33 and the fourth portion 34, i.e., the clampable regions, with reference to the pair of openings 302. For example, in the example shown in
In the semiconductor device A1, the third portion 33 includes the tapered portion 331, and the opening 302 is formed at the boundary between the third portion 33 and the first portion 31. In the die pad 3, the opening 302 is a portion recessed from the die pad main surface 30a in the thickness direction z, and the second portion 32 is a portion recessed from the lower side in the thickness direction z. Therefore, if the distance between the opening 302 and the second portion 32 close to the opening 302 is not appropriately secured in the plan view, the rigidity of the die pad 3 may decrease. Thus, in the semiconductor device A1, by allowing the tapered portion 331 to be included in the third portion 33, it becomes possible to appropriately secure the distance between the opening 302 and the second portion 32 close to the opening 302, which makes it possible to suppress a decrease in the rigidity of the die pad 3. This also applies to the configuration in which the fourth portion 34 includes the tapered portion 341. That is, the semiconductor device A1 has a package structure which may be used to suppress a decrease in the rigidity of the die pad 3 in forming the pair of openings 302.
In the semiconductor device A1, the plurality of leads 4 includes the first lead 5 and the second lead 6. The first lead 5 has the first pad surface 50a to which the first connecting member 71 is bonded, and the second lead 6 has a second pad surface 60a to which the second connecting member 72 is bonded. When viewed in the thickness direction z, the first pad surface 50a is larger than the second pad surface 60a. According to this configuration, it is possible to bond a larger number of first connecting members 71 to the first lead 5 or bond a connecting member 7 having a large wire diameter to the first lead 5. Therefore, it is possible to allow a large current to flow through the semiconductor element 1. Further, the first lead 5 is larger than the second lead 6 and, therefore, has a good conductivity. Accordingly, the semiconductor device A1 has a package structure which may be used to improve the performance.
In the semiconductor device A1, the semiconductor element 1 includes the power component 101 and the control circuit component 102. The power component 101 often operates with a relatively larger current than the control circuit component 102. Therefore, in the semiconductor device A1, the first lead 5 may be installed at the plurality of leads 4, which is a package structure that may be used to mount such a semiconductor element 1.
In the semiconductor device A1, the first lead 5 is arranged at a position closer to the power component 101 than the control circuit component 102. According to this configuration, it is possible shorten the distance between the first main surface electrode 12 of the semiconductor element 1 and the first lead 5, which is an arrangement that may be used to bond the first connecting member 71.
In the semiconductor device A1, the plurality of first side leads 41 includes the first lead 5, and the plurality of second side leads 42 does not include the first lead 5. Further, each first connecting member 71 is bonded to each first lead 5 and the semiconductor element 1 (each first main surface electrode 12) by wedge bonding. When the first connecting member 71 is wedge-bonded to the first lead 5 of the plurality of first side leads 41 and the semiconductor element 1 (first main surface electrode 12), for example, both ends of the die pad 3 in the second direction x are pressed by the clamp member. At this time, for example, the clamp member presses one end of the die pad 3 in the second direction x from one side in the second direction x with respect to the one end, and the clamp member presses the other end of the die pad 3 in the second direction x from the other side in the second direction x with respect to the other end. In the semiconductor device A1, one end of the die pad 3 in the second direction x is the third portion 33, and the other end of the die pad 3 in the second direction x is the fourth portion 34. With such a pressing method, it becomes difficult to connect the semiconductor element 1 and the plurality of second side leads 42 by the first connecting member 71 due to the arrangement of the clamp member. Therefore, in the semiconductor device A1, by adopting the configuration in which the plurality of second side leads 42 does not include the first lead 5, it is not necessary to bond each first connecting member 71 may not be bonded to the plurality of second side leads 42. This makes it possible to suppress a difficulty in bonding the first connecting member 71 to the plurality of second side leads 42 as described above. In other words, the third portion 33 and the fourth portion 34 are arranged on the side where the plurality of second side leads 42 not including the first lead 5 are arranged, with respect to the first portion 31, to suppress the aforementioned difficulty.
In the semiconductor device A1, each of the first leads 5 faces the side opposite to the first pad surface 50a in the thickness direction z and has the plurality of first exposed surfaces exposed from the resin back surface 22. In the semiconductor device A1, the first exposed surface is the back surface 51a in each inner portion 512. Further, the second lead 6 has the second exposed surface facing the side opposite to the second pad surface 60a in the thickness direction z and exposed from the resin back surface 22. In the semiconductor device A1, the second exposed surface is the back surface 61a of the first portion 61. When viewed in the thickness direction z, the back surface 51a (each first exposed surface) of each inner portion 512 is larger than the back surface 61a (second exposed surface). According to this configuration, when the semiconductor device A1 is mounted on a circuit board of an electronic device or the like, a bonding area between the back surface 51a of each inner portion 512 of the first portion 51 and the circuit board is larger than the bonding area between the back surface 61a of the second lead 6 and the circuit board. Therefore, the semiconductor device A1 may make a conductivity from the first lead 5 to the circuit board better than a conductivity from the second lead 6 to the circuit board. Further, in the semiconductor device A1, as described above, the first pad surface 50a of the first lead 5 is larger than the second pad surface 60a of the second lead 6. Therefore, it is easy to make the back surface 51a of each inner portion 512 larger than each back surface 61a.
Next, other embodiments of the semiconductor device of the present disclosure will be described.
In the first lead 5 according to the second embodiment of the present disclosure, each second opening 503b is arranged in each connecting portion 521. Therefore, by using the plurality of second openings 503b arranged in the first direction y (first length direction) as one set, it can be determined that the intermediate portions of the adjacent two sets of the plurality of the second openings 503b in the second direction x (first width direction) are the respective inner portions 512. That is, since it can be determined that each of the intermediate portions is a position suitable for bonding the first connecting member 71, if each of the first connecting members 71 is bonded (wedge-bonded) to each of the intermediate portions, each first connecting member 71 can be bonded to each inner portion 512.
In the first lead 5 according to the third embodiment of the present disclosure, each second opening 503b is arranged in each connecting portion 521. Therefore, it can be determined that the intermediate portions of the adjacent two second openings 503b in the second direction x (first width direction) are the respective inner portions 512. That is, since it can be determined that each of the intermediate portions is a position suitable for bonding the first connecting member 71, if each of the first connecting members 71 is bonded (wedge-bonded) to each of the intermediate portions, each first connecting member 71 can be bonded to each inner portion 512.
In the first lead 5 of the semiconductor device A4, the pair of second openings 503b are arranged at both ends of each inner portion 512 in the second direction x (first width direction). Therefore, it can be determined that the region interposed between the pair of second openings 503b in the second direction x (first width direction) is each inner portion 512. That is, since it can be determined that this region is a position suitable for bonding the first connecting member 71, if each first connecting member 71 is bonded (wedge-bonded) to the region, each first connecting member 71 can be bonded to each inner portion 512.
In the first lead 5 of the semiconductor device A5, each second opening 503b is arranged at the end of each inner portion 512 on the side farther from the first resin side surface 23 in the first direction y (first length direction). Therefore, it can be determined that the region closer to the first resin side surface 23 than each second opening 503b in the first direction y (first length direction) is each inner portion 512. That is, since it can be determined that this region is a position suitable for bonding the first connecting member 71, if each first connecting member 71 is bonded (wedge-bonded) to the region, each first connecting member 71 can be bonded to each inner portion 512.
In the first lead 5 of the semiconductor device A6, each first opening 503a is arranged at the end of the outer portion 511 on the side farther from the first resin side surface 23 in the first direction y (first length direction). Therefore, it can be determined that the region closer to the first resin side surface 23 than each first opening 503a in the first direction y (first length direction) is each outer portion 511. That is, since it can be determined that this region is a position suitable for being pressed by the clamp member, if the region is pressed by the clamp member, each outer portion 511 can be pressed by the clamp member.
Each of the semiconductor devices A2 to A6 has the same effects as those of the semiconductor device A1. The configuration (arrangement and shape) of each first opening 503a shown in the semiconductor device A6 can also be applied to the semiconductor devices A2 to A5.
In the first to sixth embodiments of the present disclosure, the number, arrangement, size, and the like of the first lead 5 and the second lead 6 in the plurality of leads 4 can be appropriately changed depending on the configuration of the semiconductor element 1. The configuration of the semiconductor element 1 includes the number and arrangement of the power components 101, the number and arrangement of the control circuit components 102, the number and arrangement of the plurality of main surface electrodes 11 (the first main surface electrodes 12 and the second main surface electrodes 13), and so forth. For example, as shown in
In the first to the sixth embodiments of the present disclosure, each semiconductor device A1 to A6 includes one semiconductor element 1. Unlike this configuration, each semiconductor device A1 to A6 may include a plurality of semiconductor elements 1. For example,
In the first to sixth embodiments of the present disclosure, each of the semiconductor devices A1 to A6 has a package structure of MAP type QFN. However, each of the semiconductor devices A1 to A6 may have another package structure (e.g., MAP type SON).
In the first to sixth embodiments of the present disclosure, each of the semiconductor devices A1 to A6 includes the plurality of third leads 43. However, unlike this configuration, each of the semiconductor devices A1 to A6 may not include the third lead 43. Such a configuration that does not include the third lead 43 can also be applied to the above-mentioned other modifications (see
In the first to the sixth embodiments of the present disclosure, there is shown the example in which the first lead 5 is formed with the notch 505. However, unlike this configuration, the first lead 5 may not have the notch 505. For example,
In the first to sixth embodiments of the present disclosure, there is shown the example in which the plurality of recesses 55 is formed in the first lead 5. However, a through-hole may be formed in place of each recess 55. The through-hole is configured to include each opening 503 (the first opening 503a or the second opening 503b) formed in the first pad surface 50a. The through-hole penetrates the first lead 5 in the thickness direction z. For example,
In the first to sixth embodiments of the present disclosure, the arrangement and number of the third portion 33 and the fourth portion 34 of the die pad 3 are not limited to the illustrated examples and may be changed as appropriate. For example, the die pad 3 may include a plurality of third portions 33 arranged in the first direction y. Further, the die pad 3 may include a plurality of fourth portions 34 arranged in the first direction y. In the illustrated example, the third portion 33 and the fourth portion 34 are connected to the central portion of each end edge 310b in the first direction y. However, the third portion 33 and the fourth portion 34 may be out of alignment to one side or the other side in the first direction y. In order to clamp the die pad 3 with a clamp member and appropriately fix the semiconductor element 1, the line segment L1 connecting the centers of the third portion 33 and the fourth portion 34 may be arranged to overlap with the semiconductor element 1 in the plan view. In addition, the die pad 3 may not include the third portion 33 and the fourth portion 34.
In the first to sixth embodiments of the present disclosure, there is shown the example in which the plurality of recesses 35 is formed in the die pad 3. However, a through-hole may be formed in place of each recess 35. The through hole is configured to include each opening 302 formed in the die pad main surface 30a and is formed to penetrate the die pad 3 in the thickness direction z.
In the first to sixth embodiments of the present disclosure, the pair of openings 302 are formed on the die pad main surface 30a of the die pad 3. However, unlike this configuration, the openings 302 may not be formed. Similarly, although the plurality of openings 503 is formed on the first pad surface 50a of the first lead 5, unlike this configuration, the openings 503 may not be formed.
The semiconductor device according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device of the present disclosure may be changed in design variously. For example, the semiconductor device of the present disclosure includes embodiments relating to the following supplementary notes.
A semiconductor device, including:
a semiconductor element having an element main surface and an element back surface spaced apart from each other in a thickness direction, and including a plurality of main surface electrodes arranged on the element main surface;
a die pad on which the semiconductor element is mounted;
a plurality of leads including at least one first lead arranged on one side in a first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction;
a plurality of connecting members including a first connecting member, and configured to electrically connect the plurality of main surface electrodes and the plurality of leads; and
a resin member configured to seal the semiconductor element, a part of the die pad, parts of the plurality of leads, and the plurality of connecting members, and having a rectangular shape when viewed in the thickness direction,
wherein each of the plurality of leads is configured to entirely overlap with the resin member when viewed in the thickness direction, and arranged along an outer edge of the resin member when viewed in the thickness direction,
wherein the at least one first lead has a first pad surface, and includes a plurality of first portions and a second portion,
wherein the first pad surface includes a plurality of openings, and spans the plurality of first portions and the second portion,
wherein each of the plurality of first portions has a first back surface facing a side opposite to the first pad surface,
wherein the second portion has a second back surface facing the side opposite to the first pad surface and located closer to the first pad surface than the first back surface in the thickness direction,
wherein the plurality of first portions includes a pair of outer portions located at both ends of the at least one first lead in a second direction orthogonal to the thickness direction and the first direction, and an inner portion interposed between the pair of outer portions in the second direction, and
wherein the first connecting member is bonded to the first pad surface in the inner portion.
The semiconductor device of Supplementary Note 1, wherein the at least one first lead includes a recess recessed in the thickness direction from the first pad surface, and wherein the recess includes one of the plurality of openings.
The semiconductor device of Supplementary Note 1 or 2, wherein the at least one first lead includes a through-hole that penetrates the at least one first lead in the thickness direction, and
wherein the through-hole includes one of the plurality of openings.
The semiconductor device of Supplementary Note 3, wherein the through-hole is arranged in the second portion of the at least one first lead.
[Supplementary Note 5]
The semiconductor device of any one of Supplementary Notes 1 to 4, wherein the plurality of leads further includes at least one second lead,
wherein the plurality of connecting members further includes a second connecting member,
wherein the at least one second lead has a second pad surface to which the second connecting member is bonded, and
wherein the first pad surface is larger than the second pad surface when viewed in the thickness direction.
The semiconductor device of Supplementary Note 5, wherein the semiconductor element includes a power component including a power element and a control circuit component constituting a control circuit of the power element,
wherein the plurality of main surface electrodes includes a first main surface electrode electrically connected to the power component and a second main surface electrode electrically connected to the control circuit component,
wherein the first main surface electrode is electrically connected to the at least one first lead via the first connecting member, and
wherein the second main surface electrode is electrically connected to the at least one second lead via the second connecting member.
The semiconductor device of Supplementary Note 5 or 6, wherein the resin member has a resin back surface, a pair of first resin side surfaces, and a pair of second resin side surfaces,
wherein the resin back surface faces the same direction as the element back surface in the thickness direction,
wherein the pair of first resin side surfaces are spaced apart from each other in the first direction,
wherein the pair of second resin side surfaces are spaced apart from each other in the second direction, and
wherein each of the plurality of leads is exposed from the resin back surface.
The semiconductor device of Supplementary Note 7, wherein the plurality of leads includes a plurality of first side leads arranged such that the die pad is interposed among the plurality of first side leads in the first direction and respectively exposed from one of the pair of first resin side surfaces, and
wherein the plurality of first side leads includes the at least one first lead.
The semiconductor device of Supplementary Note 8, wherein the plurality of leads includes a plurality of second side leads arranged such that the die pad is interposed among the plurality of second side leads in the second direction and respectively exposed from one of the pair of second resin side surfaces, and
wherein the plurality of second side leads includes the at least one second lead.
The semiconductor device of any one of Supplementary Notes 7 to 9, wherein the first back surface of each of the plurality of first portions is exposed from the resin back surface, and
wherein the second back surface of the second portion is covered with the resin member.
The semiconductor device of any one of Supplementary Notes 1 to 10, wherein the plurality of openings includes a pair of first openings located on an outermost side on each of one side and the other side in the second direction, and
wherein each of the pair of first openings is formed on the first pad surface of each of the pair of outer portions.
The semiconductor device of Supplementary Note 11, wherein the pair of first openings is formed on a side of the pair of outer portions closer to the inner portion in the second direction.
The semiconductor device of Supplementary Note 11 or 12, wherein the plurality of openings includes a second opening located between the pair of first openings in the second direction.
The semiconductor device of Supplementary Note 13, wherein the second portion includes a connecting portion connected to two of the plurality of first portions adjacent to each other in the second direction, and
wherein the second opening is formed in the connecting portion.
The semiconductor device of Supplementary Note 13, wherein the second opening is formed in at least a part of an outer edge of the inner portion when viewed in the thickness direction.
The semiconductor device of any one of Supplementary Notes 1 to 15, wherein the first connecting member is a bonding wire bonded by wedge bonding.
The semiconductor device of any one of Supplementary Notes 1 to 16, further including: a plurality of third leads extending from an outer edge of the die pad toward an outer edge of the resin member when viewed in the thickness direction.
The semiconductor device of Supplementary Note 17, wherein the die pad has a rectangular shape when viewed in the thickness direction, and
wherein the plurality of third leads extends from four corners of the die pad toward four corners of the resin member, respectively, when viewed in the thickness direction.
The semiconductor device of Supplementary Note 18, wherein the at least one first lead includes a notch located adjacent to one of the plurality of third leads and formed along the adjacent third leads when viewed in the thickness direction.
According to the present disclosure in some embodiments, it is possible to provide a semiconductor device with higher performance and higher quality.
While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.
Number | Date | Country | Kind |
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2021-047150 | Mar 2021 | JP | national |