Patent Application
20250040188
This application claims benefit of priority to Korean Patent Application No. 10-2023-0098170 filed on Jul. 27, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
Example embodiments of the present disclosure relate to a semiconductor device.
As demand for high performance, speed, and/or multifunctionality of semiconductor devices has increased, integration density of semiconductor devices have also increased. In manufacturing semiconductor devices having fine patterns in response to the trend for high integration density of semiconductor devices, it may be necessary to implement patterns having a fine width or a fine spacing. Also, to overcome limitations in operation properties according to reduction of a size of planar MOSFET (metal oxide semiconductor FET), there have been efforts to develop a semiconductor device including FinFETs having a three-dimensional channel.
An example embodiment of the present disclosure provides a semiconductor device having improved reliability.
According to an example embodiment of the present disclosure, a semiconductor device includes a substrate; an active region including: a first active pattern extending in a first, horizontal, direction on the substrate and, at a first height above a bottom surface of the substrate in a third, vertical, direction, having a first width in a second, horizontal, direction perpendicular to the first direction, a second active pattern extending in the first direction and, at the first height, having a second width in the second direction smaller than the first width, and a transition active pattern extending in the first direction and connecting the first active pattern to the second active pattern; gate structures intersecting the active region and extending in the second direction on the substrate; a plurality of sets of channel layers, each set including channel layers extending in the first direction, disposed in consecutive order from the active region, and spaced apart from each other in the third direction, which is perpendicular to an upper surface of the substrate, and each set surrounded by a respective gate structure on the active region; and source/drain regions disposed sides of the gate structures, and including a first source/drain region disposed on the first active pattern, a second source/drain region disposed on the second active pattern, and a transition source/drain disposed on the transition active pattern. The active region is symmetrical in the second direction with respect to a central axis of the active region extending in the first direction, each of the source/drain regions is disposed on the active region and includes a first epitaxial layer disposed on a first set of the plurality of channel layers and a second set of the plurality of channel layers, and a second epitaxial layer disposed on the first epitaxial layer, at a second height above the bottom surface of the substrate in the third direction, a first sidewall thickness of the first epitaxial layer of the first source/drain region in the first direction is greater than a second sidewall thickness of the first epitaxial layer of the second source/drain region in the first direction, and at the second height, the first epitaxial layer of the transition source/drain region has a first sidewall having a first transition sidewall thickness in the first direction and a second transition sidewall having a second transition sidewall thickness in the first direction, smaller than the first transition sidewall thickness.
According to an example embodiment of the present disclosure, a semiconductor device includes a substrate; an active region extending in a first, horizontal, direction on the substrate, and including a first active pattern at a first height above a bottom surface of the substrate in a vertical direction and having a first width in a second, horizontal, direction, a second active pattern having a second width in the second direction different from the first width, and a transition active pattern connecting the first active pattern to the second active pattern; gate structures intersecting the active region each gate structure extending in the second direction across the substrate; source/drain regions disposed on sides of the gate structures, and including a first source/drain region disposed on the first active pattern, a second source/drain region disposed on the second active pattern, and a transition source/drain region disposed on the transition active pattern. Each of the source/drain regions is disposed on the active region and includes a first epitaxial layer having a recessed upper surface and a second epitaxial layer disposed on the first epitaxial layer, at a second height above a bottom surface of the substrate in a vertical direction, a first sidewall thickness of the first epitaxial layer of the first source/drain region in the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source/drain region in the first direction, at the second height, thicknesses of opposing sidewalls of the first epitaxial layer of the transition source/drain region in the first direction are different, and a vertical level of a lowermost end of the second epitaxial layer of the first source/drain region, a vertical level of a lowermost end of the second epitaxial layer of the second source/drain region, and a vertical level of a lowermost end of the second epitaxial layer of the transition source/drain region are different from each other.
According to an example embodiment of the present disclosure, a semiconductor device includes a substrate; an active region extending in a first direction on the substrate, and including a first active pattern having a first width in a second direction crossing the first direction, a second active pattern having a second width in the second direction smaller than the first width, and a transition active pattern connecting the first active pattern to the second active pattern, gate structures intersecting the active region on the substrate and extending in the second direction; a plurality of sets of channel layers, each set including channel layers extending in the first direction, disposed in consecutive order from the active region, and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, and each set surrounded by a respective gate structure on the active region, the plurality of sets of channel layers arranged apart from each other in the first direction; and source/drain regions disposed between gate structures adjacent each other in the first direction, and including a first source/drain region disposed on the first active pattern, a second source/drain region disposed on the second active pattern, and a transition source/drain region disposed on the transition active pattern. Each of the source/drain regions is disposed on the active region and includes a first epitaxial layer disposed between adjacent sets of the plurality of channel layers and a second epitaxial layer disposed on the first epitaxial layer, at a first vertical height above a bottom surface of the substrate, the transition source/drain region has a first transition sidewall thickness, in the first direction, of the first epitaxial layer of the transition source/drain region and a second transition sidewall thickness, smaller than a first transition sidewall thickness, and a vertical level of a lowermost end of the second epitaxial layer of the transition source/drain region is higher than a vertical level of a lowermost end of the second epitaxial layer of the first source/drain region and is lower than a vertical level of a lowermost end of the second epitaxial layer of the second source/drain region.
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in combination with the accompanying drawings, in which:
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.
Referring to
In the semiconductor device 100, the active region 105 may have a fin structure, the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140, and on the channel structure 140. Accordingly, the semiconductor device 100 may include transistors having a multi-bridge channel FET structure (MBCFET™), which is a gate-all-around type field effect transistor.
The substrate 101 may have an upper surface extending in the X-direction and the Y-direction. The substrate 101 may include or be formed of a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator layer (SOI), or a semiconductor on insulator layer (SeOI).
The substrate 101 may include an active region 105 disposed in an upper portion of the substrate 101. The active region 105 may be defined by the device isolation layer 110 in the substrate 101 and may be disposed to extend lengthwise in the first direction, for example, the X-direction. An item, layer, or portion of an item or layer described as extending “lengthwise” in a particular direction has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width. In some examples, the active region 105 may be described as a component separate from the substrate 101.
The active region 105 may include a first active pattern 105A extending in the first direction (e.g., the X-direction) on the substrate 101 and having a first width Wa in the second direction (e.g., the Y-direction), a second active pattern 105B having a second width Wb in the second direction different from the first width Wa, and a transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B. The first width Wa and second width Wb may refer to a width of each active pattern at a particular vertical level (e.g., at a particular height above the bottom surface of the substrate), an example bottom surface is depicted in
The active region 105 may partially protrude from the device isolation layer 110, and an upper surface of the active region 105 may be disposed at a level higher than a level of an upper surface of the device isolation layer 110. An upper surface of the active region 105 may have a downwardly curved shape. In example embodiments, the upper surface of each of the first active pattern 105A, second active pattern 105B, and transition active pattern 105T may have a downwardly curved shape (e.g., a concave shape). The active region 105 may include a portion of the substrate 101 (e.g., formed by etching other portions of the substrate), or may include an epitaxial layer grown from the substrate 101. In either case, the active region 105 is provided with the substrate 101. The active region 105 may be partially recessed into both sides of the gate structures 160 and recess regions may be formed, and source/drain regions 150 may be disposed in the recess regions. The source/drain region 150 may extend from a lower surface of the interlayer insulating layer 190 disposed between the gate structures 160 and may be disposed within the active region 108.
In example embodiments, the active region 105 may or may not include a well region including impurities. For example, in the case of a P-type transistor (PFET), the well region may include N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an N-type transistor (nFET), the well region may include P-type impurities such as boron (B), gallium (Ga), or indium (In). For example, the well region may be disposed at a predetermined depth from the upper surface of the active region 105.
In example embodiments, the active region 105 may be symmetrical in the second direction (e.g., the Y-direction) with respect to a central axis CL of the active region 105 extending in the first direction (e.g., the X-direction). This structure affects the prevention of contact between the second epitaxial layer 152 and the gate structures 160, such that a semiconductor device having improved electrical properties and reliability may be provided.
The device isolation layer 110 may define an active region 105 in the substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. The device isolation layer 110 may expose an upper surface of active region 105 and may partially expose the upper portion. In some example embodiments, the device isolation layer 110 may have a wavy upper surface such that a level thereof may increase toward the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, oxide, nitride, or a combination thereof.
The gate structures 160 may be disposed to intersect the active region 105 and the channel structures 140 and to extend in the second direction, for example, the Y-direction, on the active region 105 and the channel structures 140. A functional channel region of transistors may be formed in the active region 105 and/or the channel structures 140 intersecting the gate electrodes 165 of the gate structures 160. Each of the gate structures 160 may include a gate electrode 165, gate dielectric layers 162 between the gate electrode 165 and the first to fourth channel layers 141, 142, 143, and 144, and a gate spacer layers 164 on side surfaces of the gate electrode 165. In example embodiments, each of the gate structures 160 may further include a gate capping layer 166 on the upper surface of the gate electrode 165.
The gate dielectric layers 162 may be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may be disposed to cover at least a portion of the surfaces of the gate electrode 165. For example, gate dielectric layers 162 may be disposed to surround the entirety of surfaces other than the upper surface of the gate electrode 165. The gate dielectric layers 162 may extend to a region between the gate electrode 165 and the gate spacer layers 164, but an example embodiment thereof is not limited thereto. The gate dielectric layers 162 may include or be formed of oxide, nitride, or a high-K material. The high-K material may refer to a dielectric material having a higher dielectric constant than that of silicon oxide (SiO2). The high-k material may be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3). In example embodiments, the gate dielectric layer 162 may be formed of a multilayer film.
The gate electrode 165 may fill a space between the first to fourth channel layers 141, 142, 143, and 144 on the active region 105 and may extend to the active region 105. The gate electrode 165 may be spaced apart from the first to fourth channel layers 141, 142, 143, and 144 by the gate dielectric layers 162. The gate electrode 165 may include or be formed of a conductive material, for example, a metal nitride such as titanium nitride film (TiN), tantalum nitride film (TAN), or tungsten nitride film (WN), and/or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo) or a semiconductor material such as doped polysilicon. In example embodiments, the gate electrode 165 may include two or more multilayers.
The gate spacer layers 164 may be disposed on both side surfaces (e.g., opposite side surfaces) of the gate electrode 165 on the channel structure 140. The gate spacer layers 164 may insulate the source/drain regions 150 from the gate electrode 165. The gate spacer layers 164 may have a multi-layer structure in example embodiments. The gate spacer layers 164 may be formed of oxide, nitride and oxynitride, and in some embodiments may be formed of a low-K film.
The gate capping layer 166 may be disposed on the gate electrode 165, and a bottom surface thereof may be surrounded by (e.g., covered by) the gate electrode 165 and the gate spacer layers 164.
The channel structures 140 may be disposed on the active region 105 in region in which the active region 105 intersects the gate structures 160. Each of the channel structures 140 may include first to fourth channel layers 141, 142, 143, and 144, which are a plurality of channel layers spaced apart from each other in the third direction (e.g., Z-direction) perpendicular to the upper surface of the substrate 101. The first to fourth channel layers 141, 142, 143, and 144 may be disposed in order from the active region 105. For example, a plurality of sets of channel layers each set including channel layers extending in the first direction (e.g., a first channel layer 141 pattern, second channel layer 142 pattern, third channel layer 143 pattern, and fourth channel layer 144 pattern), may be disposed in consecutive order from the active region 105, and spaced apart from each other in the third direction (e.g., Z-direction). Each set of channel layers may be surrounded by a respective gate structure 160 on the active region 105. The channel structures 140 may be connected to the source/drain regions 150. The channel structures 140 may have a width equal to or similar to the gate structures 160 in the X-direction, and may have a width equal to or smaller than that of the active region 105 in the Y-direction. On the cross-sectional surface in the Y-direction, the channel layer disposed in a lower portion among the first to fourth channel layers 141, 142, 143, and 144 may have a width equal to or greater than that of the channel layer disposed in an upper portion.
In example embodiments, the plurality of channel layers 141, 142, 143, and 144 disposed on the first active pattern 105A may have a width CHa of the first channel in the second direction (e.g., the Y-direction), the plurality of channel layers 141, 142, 143, and 144 disposed on the second active pattern 105B may have a width CHb of the second channel in the second direction (e.g., the Y-direction), smaller than the width CHa of the first channel, and the plurality of channel layers 141, 142, 143, and 144 disposed on the transition active pattern 105T may have a width of the transition channel in the second direction (e.g., the Y-direction) CHt, smaller than the width CHa of the first channel and greater than the width CHb of the second channel. For example, for any given vertical level (e.g., height above a bottom surface of the substrate 101), a width in the second direction (e.g., the Y-direction) of a channel layer disposed on the first active pattern 105A may be greater than a width in the second direction (e.g., the Y-direction) of a channel layer disposed on the second active pattern 105B, and a width in the second direction (e.g., the Y-direction) of a channel layer disposed on the transition active pattern 105T may be greater than the width in the second direction (e.g., the Y-direction) of the channel layer disposed on the second active pattern 105B and less than the width in the second direction (e.g., the Y-direction) of the channel layer disposed on the first active pattern 105A. Stated another way, each set of channel layers disposed on the first active pattern 105A may include consecutively ordered channel layers having a first set of widths, and each set of channel layers disposed on the second active pattern 105B may include consecutively ordered channel layers having a second set of widths in the second direction, where each width of the second set of widths smaller than a respective width of the first set of widths. On the plan diagram, each of the width CHa of the first channel and the width CHb of the second channel may have a constant width, and the width CHt of the transition channel may gradually increase or decrease along the first direction (e.g. X-direction). In one embodiment, each set of channel layers disposed on the transition active pattern 105T may include consecutively ordered channel layers having a third set of widths in the second direction, each width of the third set of widths being smaller than a respective width of the first set of widths and greater than a respective width of the second set of widths.
The number of channel layers included in the channel structure 140 and the shape thereof may vary in example embodiments. As illustrated in
The channel structures 140 may be formed of a semiconductor material, and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the channel structures 140 may be formed of the same material as that of the active region 105. In some example embodiments, the channel structures 140 may include an impurity region disposed in a region adjacent to the source/drain regions 150.
The source/drain regions 150 may be disposed in recess regions partially recessed into an upper portion of the active region 105 on opposite sides of the gate structures 160 in the X-direction. The source/drain region 150 may be disposed to cover the side surfaces in the X-direction of each of the first to fourth channel layers 141, 142, 143, and 144 of the channel structures 140. The uppermost surfaces of the source/drain regions 150 may be disposed at a level the same as or similar to a level of the lower surface of the gate electrodes 165 on the channel structures 140, and the level may vary in example embodiments. The source/drain regions 150 may include or be formed of at least one semiconductor material, for example, silicon (Si) and/or germanium (Ge), and may further include impurities.
In example embodiments, the source/drain regions 150 may include a first source/drain region 150A disposed on the first active pattern 105A, a second source/drain region 150B disposed on the second active pattern 105B, and a transition source/drain region 150T disposed on the transition active pattern 105T.
Each of the source/drain regions 150 may include a first epitaxial layer 151 and a second epitaxial layer 152 disposed on the first epitaxial layer 151. According to another example embodiment, the source/drain regions 150 may further include a plurality of epitaxial layers in addition to the first epitaxial layer 151 and the second epitaxial layer 152.
For each set of first to fourth channel layers 141, 142, 143, and 144, a first epitaxial layer 151 may cover side surfaces in the X-direction of the first to fourth channel layers 141, 142, 143, and 144, and may cover side surfaces in the X-direction of the gate structures 160 formed below and around the channel structures 140. The first epitaxial layer 151 may cover an internal side surface and a bottom surface of the recess region in which the source/drain region 150 is disposed, and may extend as an integrated layer in the source/drain region 150. The first epitaxial layer 151 may have a side surface protruding curvedly below each channel structures 141, 142, 143, and 144 toward the gate structures 160, and accordingly, the side surface may have a curve. The overall surface of the first epitaxial layer 151 that contacts sides of a stack of alternating channel structures 140 may have a wave shape, also described as a concave-convex shape. During a manufacturing process, the first epitaxial layer 151 may be grown to a relatively small thickness on the side surface of the fourth channel layer 144 due to the gate spacer layers 164 of the gate structures 160. On the plan diagram, the external side surface of at least a portion of the first epitaxial layer 151 and the second epitaxial layer 152 may be a facet along a crystal plane, but an example embodiment thereof is not limited thereto. The source/drain regions 150 are not limited to the shapes illustrated. Depending on whether the source/drain regions 150 are N-type or P-type transistors, the source/drain regions 150 may be formed of different materials or may have different shapes. The cross-sectional surface of the source/drain regions 150 in the second direction (e.g., the Y-direction) may have a pentagonal shape, a hexagonal shape, or a polygonal shape having gentle angles, but example embodiments thereof are not limited thereto.
Since the first epitaxial layer 151 is formed by epitaxial growth from the sidewall of the plurality of channel layers 141, 142, 143, and 144, a thickness of the sidewall of the plurality of channel layers 141, 142, 143, and 144 may be determined by a width in the second direction (e.g., the Y-direction). As illustrated in
Since the width in the second direction (e.g., the Y-direction) of the plurality of channel layers 141, 142, 143, and 144 in contact with both side surfaces of the transition source/drain region 150T may be different, the thicknesses in the first direction (e.g., the X-direction) of the opposing sidewalls of the first epitaxial layer 151 of the transition source/drain region 150T may be different at any particular vertical level. In example embodiments, at a particular vertical level, the transition source/drain region 150T may have a thickness Tt1 of the first transition sidewall along the first direction (e.g., the X-direction) of the first epitaxial layer 151 of the transition source/drain region 150T and a thickness Tt2 of the second transition sidewall smaller than the thickness Tt1 of the first transition sidewall. In one embodiment, this is because the width CHa of the first channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Ta of the first sidewall may be substantially equal to the thickness Tt1 of the first transition sidewall, and the thickness Tb of the second sidewall may be substantially equal to the thickness Tt2 of the second transition sidewall, but an example embodiment thereof is not limited.
The second epitaxial layer 152 may cover the first epitaxial layer 151 and may fill the recess region. Other than the upper surface of the second epitaxial layer 152, the second epitaxial layer 152 may be surrounded by the first epitaxial layer 151. At certain heights, widths Pa, Pb, Pt along the X-direction of the second epitaxial layer 152 between adjacent first epitaxial layers 151 may be greater than respective thicknesses Ta, Tb, Tt1, Tt2 at the sidewall of each of the first epitaxial layer 151. In example embodiments, at a particular height, the width Pt of the second epitaxial layer 152 of the transition source/drain region 150T in the first direction (e.g., the X-direction) may be larger than the width Pa of the second epitaxial layer 152 of the first source/drain region 150A along the first direction (e.g., the X-direction) and may be smaller than the width Pb of the second epitaxial layer 152 of the second source/drain region 150B along the first direction (e.g., the X-direction).
The second epitaxial layer 152 may include or be formed of the same material as that of the first epitaxial layer 151, but a composition and/or doping concentration may be different from that of the first epitaxial layer 151. When the semiconductor device 100 is a pFET, the source/drain region 150 may include silicon germanium (SiGe), and a concentration of germanium (Ge) of the second epitaxial layer 152 may be higher than a concentration of germanium (Ge) of the first epitaxial layer 151. For example, a concentration of germanium (Ge) of the first epitaxial layer 151 may be in a range from about 1 at % to about 15 at %, and a concentration of germanium (Ge) of the second epitaxial layer 152 may be in a range from about 20 at % to about 100 at %. Also, the second epitaxial layer 152 may have a doping concentration of impurities higher than that of the first epitaxial layer 151. When the semiconductor device 100 is a pFET, impurities may be at least one of boron (B), gallium (Ga), and indium (In), and when the semiconductor device 100 is an nFET, the impurities may be phosphorus (P), arsenic (As), and antimony (Sb). Thus, according to these various embodiments, the first epitaxial layer 151 has a different material composition from the second epitaxial layer 152.
In example embodiments, on a cross-sectional surface viewed in the first direction (e.g., the X-direction) a level La (e.g., vertical height) of a lowermost end of the second epitaxial layer 152 of the first source/drain region 150A, a level Lb (e.g., vertical height) of a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B, and a level Lt (e.g., vertical height) of a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T may be different. For example, on a cross-sectional surface in the first direction (e.g., the X-direction), the level Lt of the lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T may be higher than the level La of the lowermost end of the second epitaxial layer 152 of the first source/drain region 150A, and may be lower than the level Lb of the lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In example embodiments, on a cross-sectional surface viewed in the first direction (e.g., the X-direction) a thickness Dt from a lowermost end of the first epitaxial layer 151 of the transition source/drain region 150T to a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T may be greater than the thickness Da from the lowermost end of the first epitaxial layer 151 of the first source/drain region 150A to the lowermost end of the second epitaxial layer 152 of the first source/drain region 150A, and may be smaller than the thickness Db from the lowermost end of the first epitaxial layer 151 of the second source/drain region 150B to the lowermost end of the second epitaxial layer 152 of the second source/drain region 150B. This may be because the first width Wa in the second direction (e.g., the Y-direction) of the first active pattern 105A may be greater than the second width Wb in the second direction (e.g., the Y-direction) of the second active pattern 105B and the width Wt in the second direction (e.g., the Y-direction) of transition active pattern 105T may be smaller than the first width Wa and larger than the second width Wb.
Due to the above-described structure, the second epitaxial layer 152 of the transition source/drain region 150T may be spaced apart from the gate structures 160 (e.g., from the gate dielectric 162 and gate electrode portions 165 of the gate structures 160), such that leakage current occurring when the second epitaxial layer 152 and the gate structures 160 are in contact with each other may be prevented. Accordingly, a semiconductor device having improved electrical properties and reliability may be provided.
The interlayer insulating layer 190 may cover the source/drain regions 150 and the gate structures 160, and may be disposed to cover the device isolation layer 110. The interlayer insulating layer 190 may include or be formed of at least one of oxide, nitride, and oxynitride, and may include or be, for example, a low-K material. In example embodiments, the interlayer insulating layer 190 may include a plurality of insulating layers.
The contact plugs 180 may penetrate through the interlayer insulating layer 190, may be connected to the source/drain regions 150, and may apply an electrical signal to the source/drain regions 150. The contact plugs 180 may have an inclined side surface of which a width of the lower portion decreases further than the width of the upper portion depending on an aspect ratio, but an example embodiment thereof is not limited thereto. The contact plugs 180 may extend downwardly, for example, to a region below the lower surface of the fourth channel layer 144 on the channel structure 140, but an example embodiment thereof is not limited thereto. The contact plugs 180 may be in contact with the second epitaxial layers 152 of the source/drain regions 150. In another example embodiment, the contact plugs 180 may not be disposed to be recessed into the source/drain regions 150, but may be disposed to be in contact with the upper surface of the source/drain regions 150.
Each of the contact plugs 180 may include or be formed of a metal silicide layer disposed on a lower end including the lower surface, and may further include a barrier layer forming the side surfaces of the contact plug 180 and extending to the upper surface of the metal silicide layer. The barrier layer may include or may be, for example, a metal nitride such as a titanium nitride film (TiN), a tantalum nitride film (TaN), or a tungsten nitride film (WN). The contact plugs 180 may include or be a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments, the number of conductive layers included in the contact plugs 180 and the arrangement form thereof may vary.
An interconnection structure such as a contact plug may be further disposed on the gate electrode 165, and an interconnection structure connected to the contact plugs 180 may be further disposed on the contact plugs 180.
In the description of example embodiments below, the descriptions overlapping those described above with reference to
Referring to
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The source/drain regions 150 may further include a third source/drain region 150C on the third active pattern 105C. The first width Wa of the first active pattern 105A, the second width Wb of the second active pattern 105B, and the third width Wc of the third active pattern 105C may be different, and the width Cha of the first channel, the width CHb of the second channel, and the width CHc of the third channel are different, the thickness Tc of the third sidewall of the first epitaxial layer 151 of the third source/drain region 150C along the first direction (e.g., the X-direction) may be different from the thickness Ta of the first sidewall and the thickness Tb of the second sidewall. In example embodiments, the thickness Ta of the first sidewall may be greater than the thickness Tb of the second sidewall and the thickness Tc of the third sidewall, and the thickness Tc of the third sidewall may be greater than the thickness Tb of the second sidewall.
The transition source/drain region 150T may be disposed on the transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B, and the transition source/drain region 150T′ may be disposed on the transition active pattern 105T′ connecting the second active pattern 105B to the third active pattern 105C.
In example embodiments, at a particular vertical level, the transition source/drain region 150T between the first source/drain region 150A and the second source/drain region 150B may have a thickness Tt1 of the first transition sidewall of the first epitaxial layer 151 of the transition source/drain region 150T along the first direction (e.g., the X-direction) and a thickness Tt2 of the second transition sidewall smaller than the thickness Tt1 of the first transition sidewall, which may be because the width CHa of the first channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Ta of the first sidewall may be substantially equal to the thickness Tt1 of the first transition sidewall, and the thickness Tb of the second sidewall may be substantially equal to the thickness Tt2 of the second transition sidewall, but example embodiments thereof are not limited thereto.
In example embodiments, at a particular vertical level, the transition source/drain region 150T′ between the second source/drain region 150B and the third source/drain region 150C may have a thickness Tt1′ of the first transition sidewall of the first epitaxial layer 151 of the transition source/drain region 150T′ along the first direction (e.g., the X-direction) and a thickness Tt2′ of the second transition sidewall, which is greater than the thickness Tt1′ of the first transition sidewall, which may be because the width CHc of the third channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Tb of the second sidewall may be substantially the same as the thickness Tt1′ of the first transition sidewall, and the thickness Tc of the third sidewall may be substantially the same as the thickness Tt2′ of the second transition sidewall, but example embodiments thereof is not limited thereto.
In example embodiments, at a particular vertical level, the width Pt of the second epitaxial layer 152 of the transition source/drain region 150T in the first direction (e.g., the X-direction), disposed between the first source/drain region 150A and the second source/drain region 150B, may be greater than a width Pa of the second epitaxial layer 152 of the first source/drain region 150A along the first direction (e.g., the X-direction), and may be smaller than a width Pb of the second epitaxial layer 152 of the second source/drain region 150B along the first direction (e.g., the X-direction).
In example embodiments, at a particular vertical level, the width Pt′ of the second epitaxial layer 152 of the transition source/drain region 150T′ in the first direction (e.g., the X-direction), disposed between the second source/drain region 150B and the third source/drain region 150C, may be smaller than a width Pb of the second epitaxial layer 152 of the second source/drain region 150B in the first direction (e.g., the X-direction), and may be larger than the width Pc along the first direction (e.g., the X-direction) of the second epitaxial layer 152 of the third source/drain region 150C.
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), a level Lt of a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T disposed between the first source/drain region 150A and the second source/drain region 150B may be may be higher than a level La of a lowermost end of the second epitaxial layer 152 of the first source/drain region 150A and lower than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction), a Level Lt′ of a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T′ disposed between the second source/drain region 150B and the third source/drain region 150C may be may be higher than a level Lc of a lowermost end of the second epitaxial layer 152 of the third source/drain region 150C and lower than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), a thickness Dt from a lowermost end of the first epitaxial layer 151 of the transition source/drain region 150T disposed between the first source/drain region 150A and the second source/drain region 150B to a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T may be greater than a thickness Da from a lowermost end of the first epitaxial layer 151 of the first source/drain region 150A to a lowermost end of the second epitaxial layer 152 of the first source/drain region 150A and may be smaller than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source/drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), the thickness Dt′ from a lowermost end of the first epitaxial layer 151 of transition source/drain region 150T′ disposed between the second source/drain region 150B and the third source/drain region 150C to a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T′ may be greater than a thickness Dc from a lowermost end of the first epitaxial layer 151 of the third source/drain region 150C to a lowermost end of the second epitaxial layer 152 of the third source/drain region 150C, and may be smaller than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source/drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In
In the description of the example embodiment below, descriptions overlapping those described above with reference to
Referring to
The source/drain regions 150 may further include a third source/drain region 150C on the third active pattern 105C. The thickness Tc of the third sidewall of the first epitaxial layer 151 of the third source/drain region 150C in the first direction (e.g., the X-direction) may be different from the thickness Ta of the first sidewall and the thickness Tb of the second sidewall. In example embodiments, the thickness Ta of the first sidewall may be greater than the thickness Tb of the second sidewall and the thickness Tc of the third sidewall, and the thickness Tb of the second sidewall may be greater than the thickness Tc of the third sidewall.
In example embodiments, at a particular vertical level, the transition source/drain region 150T disposed between the first source/drain region 150A and the second source/drain region 150B may have a thickness Tt1 of the first transition sidewall of the first epitaxial layer 151 of the transition source/drain region 150T along the first direction (e.g., the X-direction) and a thickness Tt2 of the second transition sidewall smaller than the thickness Tt1 of the first transition sidewall, which may be because the width CHa of the first channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Ta of the first sidewall may be substantially equal to the thickness Tt1 of the first transition sidewall, and the thickness Tb of the second sidewall may be substantially equal to the thickness Tt2 of the second transition sidewall, but example embodiments thereof is not limited.
In example embodiments, at a particular vertical level, the transition source/drain region 150T′ between the second source/drain region 150B and the third source/drain region 150C may have a thickness Tt1′ of the first transition sidewall of the first epitaxial layer 151 of the transition source/drain region 150T′ along the first direction (e.g., the X-direction) and a thickness Tt2′ of the second transition sidewall, smaller than the thickness Tt1′ of the first transition sidewall. In example embodiments, the thickness Tb of the second sidewall may be substantially the same as the thickness Tt1′ of the first transition sidewall, and the thickness Tc of the third sidewall may be substantially the same as the thickness Tt2′ of the second transition sidewall, but example embodiments thereof are not limited thereto.
In example embodiments, at a particular vertical level, the width Pt of the second epitaxial layer 152 of the transition source/drain region 150T in the first direction (e.g., the X-direction), disposed between the first source/drain region 150A and the second source/drain region 150B, may be greater than the width Pa of the second epitaxial layer 152 of the first source/drain region 150A along the first direction (e.g., the X-direction), and may be smaller than the width Pb along the first direction (e.g., the X-direction) of the second epitaxial layer 152 of the second source/drain region 150B.
In example embodiments, at a particular vertical level, the width Pt′ of the second epitaxial layer 152 of the transition source/drain region 150T′ in the first direction (e.g., the X-direction), disposed between the second source/drain region 150B and the third source/drain region 150C, may be greater than the width Pb of the second epitaxial layer 152 of the second source/drain region 150B along the first direction (e.g., the X-direction), and may be smaller than the width Pc of the second epitaxial layer 152 of the third source/drain region 150C in the first direction (e.g., the X-direction).
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), a level Lt of a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T disposed between the first source/drain region 150A and the second source/drain region 150B may be higher than a level La of a lowermost end of the second epitaxial layer 152 of the first source/drain region 150A and may be lower a level Lb of a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), a level Lt′ of a lowermost end of the second epitaxial layer 152 of the transition source/drain region 150T′ disposed between the second source/drain region 150B and the third source/drain region 150C may be higher than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B and may be lower than a level Lc of a lowermost end of the second epitaxial layer 152 of the third source/drain region 150C.
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), a thickness Dt from a lowermost end of the first epitaxial layer 151 of transition source/drain region 150T to a lowermost end of the second epitaxial layer 152 of transition source/drain region 150T disposed between the first source/drain region 150A and the second source/drain region 150B may be greater than a thickness Da from a lowermost end of the first epitaxial layer 151 of the first source/drain region 150A to a lowermost end of the second epitaxial layer 152 of the first source/drain region 150A, and may be smaller than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source/drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source/drain region 150B.
In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), a thickness Dt′ from a lowermost end of the first epitaxial layer 151 of transition source/drain region 150T′ to a lowermost end of the second epitaxial layer 152 of transition source/drain region 150T′, disposed between second source/drain region 150B and third source/drain region 150C, may be greater than a thickness Db from the lowermost end of the first epitaxial layer 151 of the second source/drain region 150B to the lowermost end of the second epitaxial layer 152 of the second source/drain region 150B and may be smaller than a thickness Dc from the lowermost end of the first epitaxial layer 151 of the third source/drain region 150C to the lowermost end of the second epitaxial layer 152 of the third source/drain region 150C.
Referring to
The internal spacer layers 130 may be disposed in parallel with the gate electrodes 165 and the gate dielectric layers 162 between the first to fourth channel layers 141, 142, 143, and 144 in the third direction (e.g., Z-direction). The side surface of the internal spacer layers 130 may be in contact with the source/drain region 150. The gate electrodes 165 may be stably spaced apart from and may be electrically isolated from the source/drain regions 150 by the internal spacer layers 130. The internal spacer layers 130 may have a shape in which a side surface opposing the gate electrodes 165 may have an inwardly rounded shape, rounded toward the gate electrodes 165 (e.g., to have a convex surface facing the gate electrodes 165), but an example embodiment thereof is not limited thereto. The internal spacer layers 130 may be formed of oxide, nitride and oxynitride, and for example, may be formed of a low-K film.
In some example embodiments, the internal spacer layers 130 may be applied only to a portion of devices of the semiconductor device 100c. For example, in an nFET, the internal spacer layers 130 may be applied, and in a pFET, the internal spacer layer 130 may not be provided to improve crystallinity of silicon germanium (SiGe) in the source/drain regions 150.
Referring to
The sacrificial layers 120 may be replaced with the gate dielectric layers 162 and the gate electrodes 165 disposed below the fourth channel layer 144 through a subsequent process, as illustrated in
The sacrificial layers 120 and the first to fourth channel layers 141, 142, 143, and 144 may be formed by performing an epitaxial growth process from the stacked structure. Each of the sacrificial layers 120 and the first to fourth channel layers 141, 142, 143, and 144 may have a thickness ranging from about 1 nm to about 20 nm. The number of sacrificial layers 120 and the number of channel layers alternately stacked may vary in example embodiments.
Referring to
The active structure may include the active region 105, the sacrificial layers 120, and the first to fourth channel layers 141, 142, 143, and 144. The active structure may be formed in the form of a line extending in one direction, for example, the X-direction, and may be spaced apart from adjacent active structures in the Y-direction. The active region 105, the sacrificial layers 120, and the first to fourth channel layers 141 to 141 may be sequentially stacked in the vertical direction (the Z-direction). The width of the active structure in the second direction (the Y-direction) may gradually narrow along the vertical direction (the Z-direction).
An insulating material may be filled in the regions from which a portion of each of the active region 105, the sacrificial layers 120, and the first to fourth channel layers 141, 142, 143, and 144 are removed, and the device isolation layer 110 may be formed by removing a portion of the insulating material such that the active region 105 may protrude. The upper surface of device isolation layer 110 may be formed on a level lower than a level of the upper surface of active region 105.
When an active structure is formed, a width of the active patterns 105A, 105B, and 105T in the second direction (e.g., the Y-direction) may be formed differently for each region. The active region 105 may include a first active pattern 105A having, at a first vertical level, a first width Wa, a second active pattern 105B having, at the first vertical level, a second width Wb different from the first width Wa, and a transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B. Since the transition active pattern 105T connects the first active pattern 105A to the second active pattern 105B, which have different widths, the width Wt of the transition active pattern 105T, at the first vertical level, in the second direction (e.g., the Y-direction) may gradually decrease or increase along the first direction (e.g., the X-direction).
Referring to
The sacrificial gate structures 170 may be configured as dielectric structures formed through a subsequent process in the region in which the gate dielectric layer 162 and the gate electrode 165 are disposed on the first to fourth channel layers 141, 142, 143, and 144, as illustrated in
The gate spacer layers 164 may be formed on both (e.g., opposite) sidewalls of sacrificial gate structures 170. The gate spacer layers 164 may be formed by forming a film having a uniform thickness along upper surfaces and side surfaces of the sacrificial gate structures 170 and the active structures, and performing anisotropic etching. The gate spacer layers 164 may be formed of a low-K material and, for example, may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.
Referring to
The recess regions RC may be formed by removing a portion of the exposed sacrificial layers 120 and a portion of first to fourth channel layers 141, 142, 143, and 144 using the sacrificial gate structures 200 and the gate spacer layers 164 as masks. Accordingly, the first to fourth channel layers 141, 142, 143, and 144 may form channel structures 140 having a limited length in the X-direction.
The sacrificial layers 120 may be selectively etched with respect to the channel structures 140 by, for example, a wet etching process and may be removed to a predetermined depth from the side surface in the X-direction. The sacrificial layers 120 may have side surfaces curved inward by etching the side surfaces as described above. However, the specific shape of the side surface of sacrificial layers 120 is not limited to the example illustrated in
Referring to
The first epitaxial layer 151 may extend to be in contact with the first to fourth channel layers 141, 142, 143, and 144 and the sacrificial layers 120 in the recess region RC. Accordingly, the upper surface of the first epitaxial layer 151 may be formed in a recessed shape and may be formed to have an almost U-shape. The surface on which the first epitaxial layer 151 is in contact with the first to fourth channel layers 141, 142, 143, and 144 and the sacrificial layers 120 may have a wavy shape. An inner surface of the first epitaxial layer 151 may have a smooth, non-wavy shape.
The first epitaxial layer 151 may include or be formed of silicon germanium (SiGe) doped with a group 3 element. In example embodiment, the first epitaxial layer 151 may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (TI). The first epitaxial layer 151 may be formed by supplying silicon (Si) and germanium (Ge) source gas along with supply of carrier gas. In an example embodiment, the carrier gas may be hydrogen (H2) gas, and the silicon (Si) source gas may be, for example, silane (SiH4), dichlorosilane (SiH2Cl2; DCS), or chlorosilane (SiH3Cl; MCS), and the germanium (Ge) source gas may be, for example, germanium tetrahydride (GeH4). The second epitaxial layer 152 (see
Since the first epitaxial layer 151 is formed by epitaxial growth from a sidewall and the active region 105 of the plurality of channel layers 141, 142, 143, and 144, the thicknesses of the sidewalls of the first epitaxial layer 151 Ta, Tb, Tt1, Tt2 and the thicknesses Da, Db, and Dt of the lower portion may be different.
The thicknesses Ta, Tb, Tt1, and Tt2 of the sidewalls of the first epitaxial layer 151 may be determined by a width of the plurality of channel layers 141, 142, 143, and 144 in the second direction (e.g., the Y-direction). As illustrated in
The thicknesses Da, Db, and Dt of the lower portion of the first epitaxial layer 151 may be affected by the first width Wa of the first active pattern 105A, the second width Wb of the second active pattern 105B, and the width Wt of the transition active pattern 105T in the second direction (e.g., the Y-direction). In example embodiments, on a cross-sectional surface in the first direction (e.g., the X-direction, as viewed from the Y-direction), the thickness Dt of a lower portion of the first epitaxial layer 151 of the transition source/drain region 150T in the vertical direction may be greater than the thickness Da of a lower portion of the first epitaxial layer 151 of the first source/drain region 150A in the vertical direction, and may be smaller than the thickness Db of the lower part of the first epitaxial layer 151 of the second source/drain region 150B in the vertical direction.
The example embodiment in
Referring to
The second epitaxial layer 152 may include or be formed of silicon (Si) doped with a group 3 element. For example, the second epitaxial layer 152 may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (TI). The second epitaxial layer 152 may be formed to a level higher than a level of the upper surface of the fourth channel layer 144, but example embodiments thereof are not limited thereto. In example embodiments, a plurality of epitaxial layers may be further formed on the second epitaxial layer 152. The width Pt of the second epitaxial layer 152 of the transition source/drain region 150T in the first direction (e.g., the X-direction) may be greater than the width Pa of the second epitaxial layer 152 of the first source/drain region 150A in the first direction (e.g., the X-direction), and may be smaller than the width Pb of the second epitaxial layer 152 of the second source/drain region 150B in the first direction (e.g., the X-direction).
Referring to
The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structures 170 and the source/drain region 150 and performing a planarization process.
The sacrificial layers 120 and the sacrificial gate structures 170 may be selectively removed with respect to the gate spacer layers 164, the interlayer insulating layer 190, and the first to fourth channel layers 141, 142, 143, and 144. First, the upper gap regions UR may be formed by removing the sacrificial gate structures 170, and the lower gap regions LR may be formed by removing the sacrificial layers 120 exposed through the upper gap regions UR. For example, when the sacrificial layers 120 include silicon germanium (SiGe) and the first to fourth channel layers 141, 142, 143, and 144 include silicon (Si), the sacrificial layers 120 may be selectively removed with respect to the first to fourth channel layers 141, 142, 143, and 144 by performing a wet etching process using peracetic acid as an etchant.
Referring to
The gate dielectric layer 162 may be formed to conformally cover the internal surfaces of the upper gap regions UR and the lower gap regions LR. The gate electrode 165 may be formed to completely fill the upper gap regions UR and the lower gap regions LR. The gate electrode 165 and the gate spacer layers 164 may be removed from the upper gap regions UR to a predetermined depth downwardly. In the upper gap regions UR, the gate capping layer 166 may be formed in the region from which the gate electrode 165 and the gate spacer layers 164 are removed. Accordingly, the gate structures 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layers 164, and the gate capping layer 166 may be formed.
Thereafter, referring to
The contact holes exposing the source/drain regions 150 may be formed by patterning the interlayer insulating layer 190. Thereafter, the contact plugs 180 may be formed by filling the contact holes with a conductive material.
Specifically, after depositing a material forming a barrier layer in the contact holes, a metal-semiconductor compound layer as a silicide layer may be formed on the lower end by performing the silicide process. Thereafter, the contact plugs 180 may be formed by depositing a conductive material to fill the contact holes. Accordingly, the semiconductor device 100 in
According to the aforementioned example embodiments, by disposing the transition source/drain region on the transition active pattern connecting the first active pattern to the second active pattern with different widths, and using the structure in which the sidewalls of the first epitaxial layer of the transition source/drain region have different thicknesses and the symmetrical structure of the active region, contact between the second epitaxial layer and the gate structures may be prevented, such that a semiconductor device having improved electrical properties and reliability may be provided.
While the example embodiments have been illustrated and described above, it will be configured as apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.
It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact.
Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, compositions, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, composition, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, compositions, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.
Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim).
Embodiments described herein will be described referring to plan views and/or cross-sectional views by way of ideal schematic views. Accordingly, the exemplary views may be modified depending on manufacturing technologies and/or tolerances. Therefore, the disclosed embodiments are not limited to those shown in the views, but include modifications in configuration formed on the basis of manufacturing processes. Therefore, regions exemplified in figures may have schematic properties, and shapes of regions shown in figures may exemplify specific shapes of regions of elements to which aspects of the invention are not limited.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0098170 | Jul 2023 | KR | national |
