Patent Application
20080214015
Generally, semiconductor devices are used in a variety of electronic applications, such as computers, cellular phones, personal computing devices, and many other applications. Home, industrial, and automotive devices that in the past comprised only mechanical components now have electronic parts that require semiconductor devices, for example.
Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically comprise thin films of conductive, semiconductive, and insulating materials that are patterned and etched to form integrated circuits (IC's). There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single die or chip.
Insulating materials comprise dielectric materials that are used in many types of semiconductor devices. Silicon dioxide (SiO2) is a common dielectric material used in semiconductor device manufacturing, for example, which has a dielectric constant or k value of about 3.9. Some semiconductor applications require the use of a high k dielectric material having a higher k value than the k value of silicon dioxide, for example. Some transistors require a high k dielectric material as a gate dielectric material, and some capacitors require a high k dielectric material as an insulating material between two conductive plates, as examples, to reduce leakage current and increase capacitance.
A dynamic random access memory (DRAM) is a memory device that can be used to store information. A DRAM cell in a memory array typically includes two elements: a storage capacitor and an access transistor. Data can be stored into and read out of the storage capacitor by passing a charge through the access transistor and into the capacitor. The capacitance, or the amount of charge held by the capacitor per applied voltage, is measured in farads and depends upon the area of the plates, the distance between them, and the dielectric value of the insulator, as examples.
High k dielectric materials are typically used as an insulating material in the storage capacitor of DRAM cells or as a gate dielectric in transistors. High-k dielectric materials are typically used in conjunction with metal electrodes. Some examples of high k dielectric materials are HfO2, ZrO2, and TiO2. However, these dielectric materials exhibit a Fermi-level pinning effect in some applications. A Fermi-level pinning effect can occur at the interface of a conductive material and a dielectric material. Fermi-level pinning causes an increased charge in the dielectric material, which causes a change of the band alignment and a change in the observed effective work function of the metal.
In electronics, the term “work function” refers to the energy (usually measured in electron volts) needed to remove an electron from the Fermi level to a point an infinite distance away outside the surface. The work function of a semiconductor or conductor directly affects the threshold voltage of a transistor when the material is used as a gate electrode, for example. The work function also affects the band offset of the dielectric material and the electrode material of a memory capacitor and thus also affects the electronic leakage current through a capacitor. However, Fermi-level pinning caused by the use of high k gate dielectric materials as a gate dielectric or capacitor dielectric pins or fixes the work function.
What are needed in the art are improved high dielectric constant (k) dielectric materials and methods of formation thereof in semiconductor devices.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide improved methods of forming high k dielectric materials and structures thereof.
In accordance with a preferred embodiment of the present invention, a method of fabricating a semiconductor device includes providing a workpiece, and forming a dielectric material over the workpiece. Forming the dielectric material includes forming a first layer of a first material and forming a second layer of a second material. The first material includes AO2, wherein A includes at least one Group IVB element. The second material includes BxOy, wherein B includes at least one Group 1A, IIA, IIIA, IIIB, or Lanthanide series element.
The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
Metals that exhibit a high vacuum work function show a much lower work function when brought into contact with HfO2/ZrO2 based dielectric materials, due to the Fermi-level pinning effect, after annealing in high temperatures. One cause of the Fermi-level pinning effect is the generation of oxygen vacancies in the HfO2/ZrO2 dielectric material. The generated oxygen vacancies are usually positively charged, reducing the observed work function. A negative charge can also be produced due to electron capture, which may play a role in the mid-gap shift of N type materials when the Fermi-level of a metal electrode traps the energy level.
Embodiments of the present invention achieve technical advantages by reducing the amount of Fermi-level pinning of a conductive material, by forming a high k dielectric material that includes at least one dopant or element having a larger cationic radius than atoms of a tetravalent oxide in the high k dielectric material. The Fermi-level pinning effect is reduced by the introduction of charge compensated oxygen vacancies, leading to a reduction of charged oxygen vacancies in the dielectric material.
The present invention will be described with respect to preferred embodiments in specific contexts, namely in the formation of high k dielectric materials and electrodes in semiconductor devices such as capacitors and transistors. The invention may also be applied, however, to the formation of dielectric materials in other applications where high k dielectric materials are required, for example, and in other applications where conductive materials are formed adjacent to insulating materials.
A high k dielectric material 104 is formed over the workpiece 102, as shown in
The high k dielectric material 104 preferably comprises an oxide of at least one tetravalent element, for example. The tetravalent element is also referred to herein as A. The oxide of the at least one tetravalent element A preferably comprises an oxide of an element from Group IVB of the period table of elements. The oxide of the at least one tetravalent element A preferably comprises an oxide of Zr, Hf, or Ti, for example, although alternatively, the oxide may comprise other materials. The oxide may comprise one, or more than one, element A, for example.
The high k dielectric material 104 preferably also includes at least one dopant. The at least one dopant is also referred to herein as B. The at least one dopant B preferably comprises an element having an atom that has a larger size than the atom of the at least one tetravalent element A, for example. In particular, the element B preferably comprises an atom having a larger cationic radius than the cationic radius of the atom of element A, in accordance with embodiments of the present invention. The at least one dopant B preferably comprises one or more elements from Group 1A, IIA, IIIA, or IIIB of the periodic table of elements, for example. The at least one dopant B may comprise a trivalent element in Group IIIA, Group IIIB or the Lanthanide series larger than Hf, Zr, or Ti, such as Y, La, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Sc, In, Tl, or other elements, as examples. The at least one dopant B may comprise a divalent element in Group IIA larger than Hf, Zr, or Ti, such as Mg, Ca, Sr, Ba, or other elements, as examples. The at least one dopant B may comprise a monovalent element in Group 1A larger than Hf, Zr, or Ti, such as Li, Na, K, Rb, Cs, or other elements, as examples. The at least one dopant B may comprise one, or more than one, of the elements previously listed, for example.
If the at least one dopant B comprises In, Ti, Ba, Na, K, Rb, or Cs, the workpiece 102 preferably comprises a semiconductor material other than silicon, because these particular elements may be thermodynamically unstable on silicon in some applications, for example. The workpiece 102 in these embodiments may comprise a semiconductive material such as GaAs, InP, InSb, SiGe, Ge, GaP, GaN, or ZnS, as examples, although other materials may also be used for the workpiece 102.
The dopant or element B of the high k dielectric material 104 may comprise an oxide of the dopant or element B, or the dopant or element B may be doped into another oxide material. If the dopant or element B is doped into the high k dielectric material 104, the dopant concentration of B is preferably about 5 to 50 in molecular percent of the high k dielectric material 104, for example, although alternatively, other concentrations may also be used.
The high k dielectric material 104 preferably comprises a material that reduces a Fermi-pinning effect of a subsequently deposited conductive material, to be described further herein. While the atoms of the element A introduces charged oxygen vacancies in the high k dielectric material, advantageously, the larger atoms of the element B having a larger cationic radius than the cationic radius of the element A atoms in the high k dielectric material 104 reduce the number of the charged oxygen vacancies introduced by element A in the high k dielectric material 104, preventing oxygen from moving into a subsequently-deposited conductive material (such as conductive material 114 shown in
The first material 106 preferably comprises a material comprising AO2, wherein A comprises a tetravalent element such as Zr, Hf, Ti, or combinations thereof. The second material 108 preferably comprises a material comprising BxOy, wherein B comprises an element from Group 1A, IIA, IIIA, IIIB, or the Lanthanide series, such as Y, La, Pr, Nd, Pm, Eu, Gd, Th, Dy, Ho, Er, Tm, Yb, Lu, Sc, In, Tl, Mg, Ca, Sr, Ba, Li, Na, K, Rb, Cs, or combinations thereof, and wherein x and y indicate the stoichiometry of the second material 108, e.g., the amount of the at least one element B and the amount of oxygen O in the second material 108, for example. The at least one element B is also referred to herein as a dopant.
As an example, the first material 106 may comprise ZrO2, and the second material 108 may comprise GdxOy. The second material 108 may be doped with the at least one element B, or the second material 108 may comprise an oxide of the at least one element B, for example, in accordance with embodiments of the present invention. Alternatively, the second material 108 may comprise an oxide of at least one element B, and the second material 108 may also be doped with another, different, at least one element B, in other embodiments of the present invention.
In a second embodiment, the second material 108 is formed first. The first material 106 is preferably disposed over the second material 108 which is formed directly over, abutting, and adjacent to the workpiece 102, as shown in
In this embodiment, in some applications, the dielectric material 104 comprises a single layer of an insulating material comprised of AxByOz, wherein B comprises at least one element comprising In, Tl, Mg, Ca, Ba, Li, Na, K, Rb, or Cs. Element B may also comprise one or more of the elements In, Tl, Mg, Ca, Ba, Li, Na, K, Rb, or Cs combined with one or more other elements from Group IA, IIA, IIIA, IIIB, or the Lanthanide series, such as Y, La, Pr, Nd, Pm, Eu, Gd, Th, Dy, Ho, Er, Tm, Yb, Lu, Sc, In, Tl, Mg, Ca, Sr, Ba, Li, Na, K, Rb, Cs, or combinations thereof, in this embodiment.
The various material layers of the dielectric material 104 may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other deposition methods, or combinations thereof, for example.
In a fourth embodiment, the high k dielectric material 104 comprises a fourth material 112 disposed over the third material 110, as shown in
In the embodiments shown in
In some embodiments, the dielectric material 104 preferably does not comprise silicon. In other embodiments, the dielectric material 104 preferably does not comprise nitrogen or a nitride material.
Next, a layer of conductive material 114 is deposited over the high k dielectric material 104.
In some embodiments, a conductive material 126 may also be disposed beneath the high k dielectric material, as shown in
The material layers 130, 128, 126, and 124 may then be patterned using lithography to form transistors or capacitors from at least the electrode materials 114 and/or 126 and the dielectric layer 104 (not shown in
The novel methods and structures described herein are shown implemented in a planar structure in
Embodiments of the present invention include the novel dielectric materials 104 and electrode materials 114 and 126, and also methods of manufacturing semiconductor devices 100 using the novel dielectric materials 104 and electrode materials 114 and 126 described herein.
The high k dielectric material 104 is implemented as a gate dielectric material 104, and the conductive material 114 is implemented as a transistor gate 114. The transistor 120 includes a gate dielectric material 104 comprising the novel high k dielectric material layer 104 described herein and a gate electrode 114 comprising conductive material 114 formed over the high k dielectric material layer 104. Source and drain regions S and D are formed proximate the gate electrode 114 in the workpiece 102, and a channel region C is disposed between the source and drain regions S and D in the workpiece 102. The transistor 120 may be separated from adjacent devices by shallow trench isolation (STI) regions 118 formed in the workpiece 102, and insulating sidewall spacers 116 may be formed on sidewalls of the gate electrode 114 and the gate dielectric 104, as shown.
Advantageously, because of the novel materials of the gate dielectric material 104, the P type gate electrode 114 has reduced Fermi-level pinning, because the larger atoms of the dopant or element B within the gate dielectric material 104 reduces the number of charged oxygen vacancies in the gate dielectric material 104, which reduces the Fermi-level pinning. Thus, a desired threshold voltage of the transistor 120 can be achieved.
To form a DRAM memory cell 236 comprising a storage capacitor utilizing the novel high k dielectric material 204 of embodiments of the present invention, a sacrificial material 222 comprising an insulator such as a hard mask material is deposited over a workpiece 202, and deep trenches 232 are formed in the sacrificial material 222 and the workpiece 202. An optional conductive material 226 may be formed over the patterned workpiece 202 and sacrificial material 222, as shown in phantom in
Next, excess amounts of electrode materials 214 and 224 and dielectric material 204 are removed from over the top surface of the workpiece 202, e.g., using a chemical mechanical polish (CMP) process and/or etch process. The materials 214 and 224, and high k dielectric material layer 204 are also recessed below the top surface of the workpiece 202, for example. The sacrificial material 222 is also removed, as shown in
An oxide collar 228 may be formed by thermal oxidation of exposed portions of the trench 232 sidewalls. The trench 232 may then be filled with a conductor such as polysilicon 221. Both the polysilicon 221 and the oxide collar 228 are then etched back to expose a sidewall portion of the workpiece 202 which will form an interface between an access transistor 234 and the capacitor 236 formed in the deep trench 232 in the workpiece 202, for example.
After the collar 228 is etched back, a buried strap 221 may be formed at the top of the trench 232 by deposition of a conductive material, such as doped polysilicon. Regions 224 and 221 comprising polysilicon are preferably doped with a dopant such as arsenic or phosphorus, for example. Alternatively, regions 224 and 221 may comprise a conductive material other than polysilicon (e.g., a metal).
The strap material 221 and the workpiece 202 may then be patterned and etched to form STI regions 230. The STI regions 230 may be filled with an insulator such as an oxide deposited by a high density plasma process (i.e., HDP oxide). The access transistor 234 may then be formed to create the structure shown in
If the optional conductive material 226 lining the trench 232 is not included, the workpiece 202 proximate the high k dielectric material layer 204 lining the deep trench 232 comprises a first capacitor plate. If the optional conductive material 226 is included, the conductive material 226 and the workpiece 202 proximate the high k dielectric material layer 204 lining the deep trench 232 comprises the first capacitor plate. The high k dielectric material layer 204 comprises a capacitor dielectric, and materials 214 and 224 comprise a second capacitor plate of the deep trench storage capacitor of the DRAM memory cell 236. The access transistor 234 is used to read or write to the DRAM memory cell 236, e.g., by the electrical connection established by the strap 221 to a source or drain of the transistor 234 near the top of the deep trench 232, for example.
To form the MIM capacitor 340, a bottom capacitor plate 326 is formed over a workpiece 302. The bottom capacitor plate 326 may be formed in an insulating material (not shown) that may comprise an inter-level dielectric layer (ILD), for example. The bottom capacitor plate 326 may include liners and barrier layers, for example, not shown.
The novel high k dielectric material 304 described with reference to
An additional insulating material 336 may be deposited over the top capacitor plate 314, and the insulating material 336 may be patterned with patterns for contacts (not shown) that will make electrical contact to the top plate 314 and the underlying bottom plate 326, respectively. The insulating material 336 may be filled in later with a conductive material to form the contacts in the patterns, for example, not shown.
Thus, in
Embodiments of the present invention may also be implemented in other structures that require a dielectric material. For example, the novel processing methods, high k dielectric material layers 104, 204, and 304, and electrode materials 114, 214, and 314 described herein may be implemented in planar transistors, vertical transistors, planar capacitors, stacked capacitors, vertical capacitors, deep or shallow trench capacitors, and other devices. Embodiments of the present invention may be implemented in stacked capacitors where both plates reside above a substrate or workpiece, for example.
Advantages of embodiments of the present invention include providing novel methods and structures having a high dielectric constant or k value. The high k dielectric materials 104, 204, and 304 described herein advantageously may have a dielectric constant or k value of about 10 or greater in some embodiments, and more preferably have a dielectric constant of greater than 20 in other embodiments, for example. The amount of Fermi-level pinning of the conductive material 114, 214, and 314 is reduced by the formation of a high k dielectric material 104, 204, and 304 that includes at least one dopant or element B having a larger cationic radius than atoms of a tetravalent element A oxide in the high k dielectric material 104, 204, and 304. The Fermi-level pinning effect is reduced by the introduction of charged oxygen vacancies by the use of element A in the dielectric material 104, 204, and 304, and by the reduction of the charged oxygen vacancies by the use of element B in the dielectric material 104, 204, and 304. Thus, desired threshold voltages, work functions, and dielectric constant values may be achieved in the devices the novel dielectric material 104, 204, and 304 are used in, for example.
Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
