Patent Application
20240397714
The present application claims priority under 35 U.S.C. § 119 (a) to Korean patent application number 10-2023-0066024 filed on May 23, 2023, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.
Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to an electronic device including a semiconductor memory device having a vertical channel structure and a method of manufacturing the semiconductor memory device.
Recently, the paradigm for a computer environment has been converted into ubiquitous computing so that computer systems can be used anytime and anywhere. Due to this, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. In general, such portable electronic devices use a memory system which employs a semiconductor memory device, in other words, use a data storage device. The data storage device is used as a main memory device or an auxiliary memory device for portable electronic devices.
The data storage device using a semiconductor memory device is advantageous in that, since there is no mechanical driving part, stability and durability are excellent, an information access speed is high, and power consumption is low. The data storage device, as examples of the memory system having such advantages, includes a universal serial bus (USB) memory device, memory cards having various interfaces, a solid state drive (SSD), etc.
Semiconductor memory devices are roughly classified into a volatile memory device and a nonvolatile memory device.
The nonvolatile memory device has relatively low write and read speeds, but retains data stored therein even when the supply of power is interrupted. Therefore, the nonvolatile memory device is used to store data to be retained regardless of whether power is supplied. Examples of the nonvolatile memory device include a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The flash memory is classified into a NOR type and a NAND type.
An embodiment of the present disclosure may provide for a semiconductor memory device. The semiconductor memory device may include a gate stacked body in which a plurality of interlayer insulating layers and a plurality of conductive patterns are alternately stacked, and a plurality of channel structures disposed to extend in a vertical direction in the gate stacked body disposed in a cell region, wherein the plurality of conductive patterns extend in a horizontal direction in the cell region, and extend in the vertical direction or in a direction between the vertical direction and the horizontal direction in a word line contact region adjacent to the cell region.
An embodiment of the present disclosure may provide for a semiconductor memory device. The semiconductor memory device may include a gate stacked body formed in a cell region and in a word line contact region adjacent to the cell region in a horizontal direction, and a plurality of channel structures disposed to extend in a vertical direction in the gate stacked body disposed in the cell region, wherein the gate stacked body includes a plurality of interlayer insulating layers and a plurality of conductive patterns that are alternately stacked, and wherein the plurality of conductive patterns extend in the horizontal direction in the cell region, and extend in the vertical direction or in a direction between the vertical direction and the horizontal direction in the word line contact region and are then exposed to an upper surface of the gate stacked body.
An embodiment of the present disclosure may provide for a method of manufacturing a semiconductor memory device. The method may include forming a buffer layer on a substrate including a cell region and a word line contact region, forming a trench by etching the buffer layer and the substrate in the word line contact region to a certain depth, forming a stacked body, in which first material layers and second material layers are alternately stacked, on an entire structure, wherein the stacked body is formed along a sidewall and a lower surface of the trench and formed such that an upper surface of the stacked body in the word line contact region is lower than a lower surface of the buffer layer in the cell region, forming a plurality of channel structures extending in a vertical direction in the stacked body and the buffer layer in the cell region, replacing the second material layers with third material layers that are conductive patterns, removing the substrate such that the lower surface of the buffer layer is exposed, and removing a portion of the stacked body disposed at a position lower than the lower surface of the buffer layer, together with the substrate, thus exposing the third material layers, and forming contacts coupled to the exposed third material layers, respectively.
Specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are provided as examples to describe embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure may be practiced in various forms, and should not be construed as being limited to the embodiments described in the specification or application.
Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings so that those skilled in the art can practice the technical spirit of the present disclosure.
Various embodiments of the present disclosure are directed to a semiconductor memory device, in which conductive patterns enclosing a vertical channel structure can be coupled to contacts, and a method of manufacturing the semiconductor memory device.
Referring to
The peripheral circuit PC may control a program operation of storing data in the memory cell array 20, a read operation of outputting data stored in the memory cell array 20, and an erase operation of erasing data stored in the memory cell array 20.
In an embodiment, the peripheral circuit PC may include a voltage generator 31, a row decoder 33, a control circuit 35, and a page buffer group 37.
The memory cell array 20 may include a plurality of memory blocks. The memory cell array 20 may be coupled to the row decoder 33 through word lines WL, and may be coupled to the page buffer group 37 through bit lines BL.
The control circuit 35 may control the voltage generator 31, the row decoder 33, and the page buffer group 37 in response to a command CMD and an address ADD.
The voltage generator 31 may generate various operating voltages, such as an erase voltage, a ground voltage, a program voltage, a verify voltage, a pass voltage, and a read voltage, which are used for a program operation, a read operation, and an erase operation, under the control of the control circuit 35.
The row decoder 33 may select a memory block under the control of the control circuit 35. The row decoder 33 may apply the operating voltages to the word lines WL coupled to the selected memory block.
The page buffer group 37 may be coupled to the memory cell array 20 through the bit lines BL. The page buffer group 37 may store data received from an input/output circuit (not illustrated) under the control of the control circuit 35 during a program operation. The page buffer group 37 may sense voltages or currents of the bit lines BL under the control of the control circuit 35 during a read operation or a verify operation. The page buffer group 37 may select the bit lines BL under the control of the control circuit 35.
Structurally, the memory cell array 20 may overlap a part of the peripheral circuit PC.
Referring to
Each of the plurality of cell strings CS1 and CS2 may include at least one source select transistor SST coupled to the source line SL, at least one drain select transistor DST coupled to the corresponding bit line BL, and a plurality of memory cells MC1 to MCn coupled in series to each other between the source select transistor SST and the drain select transistor DST.
Gates of the plurality of memory cells MC1 to MCn may be respectively coupled to the plurality of word lines WL1 to WLn stacked to be spaced apart from each other. The plurality of word lines WL1 to WLn may be arranged between a source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 may be spaced apart from each other at the same level.
A gate of the source select transistor SST may be coupled to the source select line SSL. A gate of the drain select transistor DST may be coupled to the drain select line DSL1 or DSL2 corresponding to the drain select transistor DST.
The source line SL may be coupled to a source of the source select transistor SST. A drain of the drain select transistor DST may be coupled to a bit line BL corresponding to the drain select transistor DST.
The plurality of cell strings CS1 and CS2 may be divided into cell string groups coupled to the two or more drain select lines DSL1 and DSL2, respectively. Cell strings coupled to the same word line and the same bit line may be independently controlled by different drain select lines. Further, cell strings coupled to the same drain select line may be independently controlled by different bit lines.
In an embodiment, two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. The plurality of cell strings CS1 and CS2 may include first cell strings CS1 of a first cell string group coupled to the first drain select line DSL1 and second cell strings CS2 of a second cell string group coupled to the second drain select line DSL2.
Referring to
Each of the gate stacked bodies GST may include a source select line SSL, a plurality of word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 separated from each other at the same level by a separation structure DSM.
The source select line SSL and the plurality of word lines WL1 to WLn may extend in a first direction FD and a second direction SD, and may be formed in planar shapes parallel to each other on the upper surface of the substrate SUB. The first direction FD and the second direction SD may be directions parallel to the substrate SUB, and the first direction FD and the second direction SD may be orthogonal to each other. For example, the first direction FD may be a direction in which the X axis of an XYZ coordinate system faces, and the second direction SD may be a direction in which the Y axis of the XYZ coordinate system faces.
The plurality of world lines WL1 to WLn may be stacked to be spaced apart from each other in a third direction TD. The third direction TD may be a direction that is vertical to the substrate SUB and orthogonal to the first direction FD and the second direction SD. For example, the third direction TD may be a direction in which the Z axis of the XYZ coordinate system faces. The plurality of word lines WL1 to WLn may be arranged between the two or more drain select lines DSL1 and DSL2 and the source select line SSL.
The gate stacked bodies GST may be separated from each other by a slit SI. The separation structure DSM may be formed to be shorter than the slit SI in the third direction TD, and may overlap the plurality of word lines WL1 to WLn.
Each of the separation structure DSM and the slit SI may extend in a linear shape, a zigzag shape, or a wave shape. The width of each of the separation structure DSM and the slit SI may be variously changed depending on the design rule.
The source select line SSL according to an embodiment may be arranged closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2.
The semiconductor memory device 10 may include a source line SL disposed between the gate stacked bodies GST and the peripheral circuit PC and a plurality of bit lines BL spaced farther apart from the peripheral circuit PC than the source line SL. The gate stacked bodies GST may be disposed between the plurality of bit lines BL and the source line SL.
Referring to
The upper structure T may include gate stacked bodies GST separated by an insulating pattern 128 and an insulating layer 115, channel structures 125 penetrating the gate stacked bodies GST to extend in a third direction TD, and a bit line connection structure BL_CS and a first coupling structure 1st_CS that are disposed under the gate stacked bodies GST. The insulating pattern 128 and the insulating layer 115 may extend in the third direction TD, and the gate stacked body GST in a first cell region CR_1 and the gate stacked body GST in a second cell region CR_2 may be physically separated from each other by the insulating layer 115.
Each gate stacked body GST may include first material layers 111 and third material layers 129, which are alternately stacked in a vertical direction. The first material layers 111 may be defined as interlayer insulating layers, and the third material layers 129 may be defined as conductive patterns for word lines. Each of the third material layers 129 may include various conductive materials, such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and may include two or more kinds of conductive materials. For example, each of the third material layers 129 may include tungsten and a titanium nitride layer (TiN) configured to enclose the surface of tungsten. Tungsten is a low-resistance material and is capable of decreasing the resistance of the third material layers 129. The titanium nitride layer (TiN) may be a barrier layer, and may prevent tungsten and the interlayer insulating layers from directly contacting each other. Each of the third material layers 129 may extend in a second direction SD, which is a horizontal direction, in the first cell region CR_1 and the second cell region CR_2, and may extend in a third direction TD, which is a vertical direction, or in a direction between the third direction TD and the second direction SD in a word line contact region WCR between the first cell region CR_1 and the second cell region CR_2, and may then be exposed to the upper surface of the corresponding gate stacked body GST. The third material layers 129 extending in the third direction TD or in the direction between the third direction TD and the second direction SD and exposed to the upper surfaces of the gate stacked bodies GST may be defined as word line extensions WL_EXT. The third material layers 129 extending in the second direction SD, which is the horizontal direction, in the first cell region CR_1 and the second cell region CR_2 and the word line extensions WL_EXT extending in the third direction TD, which is the vertical direction, or in the direction between the third direction TD and the second direction SD in the word line contact region WCR may be made of the same material. The word line extensions WL_EXT may extend to the position equal to or higher than that of the upper surface of a buffer layer 103 formed in the first cell region CR_1 and the second cell region CR_2.
Among the third material layers 129, a third material layer 129 adjacent to line patterns 137 may be used as a drain select line. The line patterns 137 may be bit lines. In other embodiments, the second material layers 129 of two or more layers, which are adjacent to the line patterns 137 and are successively stacked, may be used as drain select lines. Among the third material layers 129, at least one third material layer 129 adjacent to source line layers 301 may be used as a source select line. Furthermore, the remaining third material layers 129, other than the third material layers 129 used as the drain select line and the source select line, may be used as word lines.
Each channel structure 125 may penetrate the corresponding gate stacked body GST in the third direction TD, which is the vertical direction, and the first end of the channel structure 125 may be formed to protrude higher than the corresponding gate stacked body GST. The channel structure 125 may be formed in a hollow type. The channel structure 125 may include a core insulating layer 121 configured to fill a central region of the channel structure 125, a capping conductive layer 123 disposed under the core insulating layer 121, a channel layer 119 enclosing the surfaces of the core insulating layer 121 and the capping conductive layer 123, and a memory layer 117 enclosing the sidewall of the channel layer 119. The channel layer 119 may be used as a channel region for a cell string corresponding thereto. The channel layer 119 may be formed of a semiconductor material. In an embodiment, the channel layer 119 may include a silicon layer. The channel structure 125 may be formed to protrude higher than the interlayer insulating layer disposed in the uppermost portion of the corresponding gate stacked body GST. The channel structure 125 may be formed to penetrate the buffer layer 103 formed on the corresponding gate stacked body GST. The protruding end of the channel structure 125 may be formed to directly contact the corresponding source line layer 301. For example, the channel layer 119 of the channel structure 125 may be formed to be directly coupled to the source line layer 301.
The memory layer 117 may include a tunnel insulating layer enclosing the sidewall of the channel layer 119, a data storage layer enclosing the tunnel insulating layer, and a blocking insulating layer enclosing the data storage layer. The memory layer 117 may be formed to have the same length as the channel structure 125 in the vertical direction.
The word line connection structure WL_CS may be disposed on the gate stacked bodies GST. The word line connection structure WL_CS may include source line layers 301 coupled to the channel structures 125, a plurality of insulating layers 303 and 307 configured to cover the source line layers 301 and the gate stacked bodies GST, first contacts 305A penetrating the insulating layer 303 to couple the source line layers 301 to first contact pads 309A, and second contacts 305B penetrating the insulating layer 303 to couple respective word line extensions WL_EXT exposed to the upper surfaces of the gate stacked bodies GST to second contact pads 309B. Because respective word line extensions WL_EXT are exposed to the upper surfaces of the gate stacked bodies GST, the second contacts 305B for coupling the third material layers 129 of the gate stacked bodies GST to the second contact pads 309B may be disposed only on the gate stacked bodies GST without needing to extend into the gate stacked bodies GST. That is, the second contacts 305B may be disposed only at the position equal to or higher than that of the upper surfaces of the gate stacked bodies GST.
The bit line connection structure BL_CS may be disposed under the gate stacked bodies GST. The bit line connection structure BL_CS may include a first insulating layer 131, a second insulating layer 135, contact plugs 133, and line patterns 137. The line patterns 137 used as bit lines may be coupled to respective channel structures 125 through the contact plugs 133 penetrating the first insulating layer 131.
The first coupling structure 1st_CS may be disposed under the bit line connection structure BL_CS. The first coupling structure 1st_CS may include a first insulating structure 141 including a plurality of insulating layers 141A to 141D, first connection structures 143, 145, 147, and 149 formed in the first insulating structure 141, and the first connection structures 143, 145, 147, and 149 may be electrically connected to each other through contact plugs (not illustrated). The first connection structures 143, 145, 147, and 149 may include one or more first bonding metals 149 having a surface exposed to the outside of the first insulating structure 141.
The lower structure U may include a complementary metal oxide semiconductor (CMOS) circuit structure CMOS including a plurality of transistors 200 formed on a second substrate 201, and a second coupling structure 2nd_CS formed on the CMOS circuit structure CMOS. The plurality of transistors 200 may be formed in respective active regions of the second substrate 201 partitioned by isolation layers 203.
The second coupling structure 2nd_CS may include a second insulating structure 211 and second connection structures 220 formed in the second insulating structure 211. The second connection structures 220 may include various conductive patterns 213, 215, 217, 219, 221, and 223 that are embedded in the second insulating structure 211. The second insulating structure 211 may include two or more insulating layers 211A to 211D which are sequentially stacked.
The upper structure T and the lower structure U may have a structure in which they are adhered to each other through a bonding structure. For example, the exposed conductive patterns 149 of the first coupling structure 1st_CS of the upper structure T and the exposed conductive patterns 223 of the second coupling structure 2nd_CS of the lower structure U may be disposed to face each other, and may be adhered to each other. The one or more first bonding metals 149 and the one or more conductive patterns 223 may be defined as a bonding metal.
Referring to
Thereafter, a trench 105 may be formed in the first substrate 101 by sequentially etching the buffer layer 103 and the first substrate 101 in the word line contact region WCR. The depth of the trench 105 may be formed to be greater than the thickness of a stacked body ST to be subsequently formed.
Thereafter, the stacked body ST may be formed by alternately stacking first material layers 111 and second material layers 113 on top of one another on the buffer layer 103 and the trench 105. The first material layers 111 and the second material layers 113 may be made of materials having etching rates different from that of the first substrate 101.
In an embodiment, the first material layers 111 may include an insulating material for interlayer insulating layers. The second material layers 113 may include a material having an etching rate different from that of the first material layers 111. For example, the first material layers 111 may include silicon oxide, and the second material layers 113 may include silicon nitride. Although the following drawings illustrate embodiments in which the first material layers 111 are formed of the insulating material and the second material layers 113 are formed of sacrificial layers, the present disclosure is not limited thereto. The material properties of the first material layers 111 and the second material layers 113 may be variously changed. For example, the first material layers 111 may include an insulating material for interlayer insulating layers, and the second material layers 113 may include a conductive material for conductive patterns.
The stacked body ST may be formed on the buffer layer 103 in the first cell region CR_1 and the second cell region CR_2, and may be formed along the sidewall and the lower surface of the trench 105 in the word line contact region WCR. The stacked body ST may include a protrusion P extending into the first substrate 101 in the word line contact region WCR. Accordingly, the second material layers 113 may extend in parallel to a second direction SD in the first cell region CR_1 and the second cell region CR_2, and may extend into the first substrate 101 in the word line contact region WCR. That is, the second material layers 113 may extend in a third direction TD or in a direction between the third direction TD and the second direction SD in the word line contact region WCR.
The position of the lowest upper surface, among upper surfaces of the stacked body ST formed in the trench 105, may be lower than that of the lower surface of the buffer layer 103 in the first cell region CR_1 and the second cell region. Among the second material layers 113 included in the stacked body ST, one second material layer 113 disposed in the uppermost portion may extend to a position, deeper than the upper surface of the first substrate 101 in the first cell region CR_1 and the second cell region CR_2, in the word line contact region WCR.
The central region of the trench 105 may be filled with an insulating layer 115. The insulating layer 115 may include oxide.
Referring to
The plurality of holes H may be formed in various shapes depending on an etching material used to form the plurality of holes H.
In an embodiment, the plurality of holes H may be formed using a first etching material. The etching rates of the first material layers 111 and the second material layers 113 corresponding to the first etching material may be higher than the etching rate of the first substrate 101 corresponding to the first etching material. As a result, the widths of ends of the plurality of holes H extending into the first substrate 101 may be formed to be narrower than those of the plurality of holes H passing through the first material layers 111 and the second material layers 113.
Thereafter, a channel structure 125 may be formed in each of the plurality of holes H. The channel structure 125 may include a memory layer 117 and a channel layer 119, and may further include a core insulating layer 121 and a capping conductive layer 123.
In an embodiment, the memory layer 117 may be formed along the sidewall and the lower surface of each of the plurality of holes H. The memory layer 117 may be formed by sequentially stacking a blocking insulating layer, a data storage layer, and a tunnel insulating layer on the surface of each of the plurality of holes H. The memory layer 117 may be formed in a liner shape. Thereafter, the channel layer 119 may be formed on the surface of the memory layer 117. The channel layer 119 may include a semiconductor layer used as a channel region. For example, the channel layer 119 may include polysilicon. In an embodiment, the channel layer 119 may be formed in a liner shape, and the central region of each of the plurality of holes H may include a portion that is not filled with the channel layer 119. When the channel layer 119 is formed in a liner shape, the central region of each of the plurality of holes H may be filled with the core insulating layer 121 on the channel layer 119. Thereafter, a recess region may be defined by partially etching an upper portion of the core insulating layer 121, and the capping conductive layer 123 may be formed in the recess region. The core insulating layer 121 may include oxide, and the capping conductive layer 123 may include conductive dopants. The conductive dopants may include an n-type dopant for junctions. The conductive dopants may include a counter-doped p-type dopant.
In other embodiments, the channel layer 119 may be formed to fill the central region of each of the plurality of holes H, wherein the core insulating layer 121 and the capping conductive layer 123 may be omitted.
Referring to
Subsequently, the second material layers (e.g., 113 of
Thereafter, the horizontal spaces from which the second material layers (e.g., 113 of
As described above, the gate stacked body GST may be formed on the first substrate 101 by replacing the second material layers 113 as sacrificial layers with the third material layers 129. The gate stacked body GST may include a structure in which the first material layers 111, as interlayer insulating layers, and the third material layers 129, as conductive patterns, are alternately stacked. The gate stacked body GST may be penetrated by the channel structures 125, and the channel structures 125 may extend into the first substrate 101.
Referring to
Thereafter, contact plugs 133 penetrating the first insulating layer 131 may be formed. The contact plugs 133 may extend to contact the channel structures 125, respectively. Subsequently, a second insulating later 135 that covers the contact plugs 133 may be formed. The second insulating layer 135 may include oxide. Then, line patterns 137 to be respectively coupled to the contact plugs 133 may be formed in the second insulating layer 135. The line patterns 137 may be bit lines coupled to the contact plugs 133.
Referring to
The first connection structures 143, 145, 147, and 149 may include first bonding metal 149 having a surface exposed to the outside of the first insulating structure 141.
Referring to
The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial layer substrate formed using a selective epitaxial growth method.
The transistors 200 may be formed in respective active regions of the second substrate 201 partitioned by isolation layers 203. Each of the transistors 200 may a gate insulating layer 207 and a gate electrode 209 stacked in the active region corresponding thereto and junctions 205a and 205b formed in active regions disposed on both sides of the gate electrode 209. Each of the junctions 205a and 205b may include conductive dopants for implementing a transistor corresponding thereto. Each of the junctions 205a and 205b may include at least one of an n-type dopant and a p-type dopant.
After the plurality of transistors 200 are formed, second connection structures 220 coupled to the transistors 200 constituting the CMOS circuit, and a second insulating structure 211 configured to cover the second connection structures 220 and the transistors 200 may be formed.
The second insulating structure 211 may include two or more insulating layers 211A to 211D. The second connection structures 220 may be embedded in the second insulating structure 211. Each of the second connection structures 220 may include a plurality of conductive patterns 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structures 220 may be changed in various forms without being limited to the example illustrated in the drawing.
The conductive patterns 213, 215, 217, 219, 221, and 223 included in each of the second connection structures 220 may include second bonding metal 223 having a surface exposed to the outside of the second insulating structure 211.
Referring to
Thereafter, the first bonding metal 149 and the second bonding metal 223 are adhered to each other. For this, after heat is applied to the first bonding metal 149 and the second bonding metal 223, the first bonding metal 149 and the second bonding metal 223 may be hardened. The present disclosure is not limited thereto, and various processes of coupling the first bonding metal 149 and the second bonding metal 223 to each other may be introduced.
Referring to
Portions of the channel structures 125 protruding higher than the buffer layer 103 may be etched together in the above-described grinding process, whereby respective channel layers 119 of the channel structures 125 may be exposed.
Thereafter, source line layers 301 contacting respective channel layers 119 of the channel structures 125 may be formed. Each of the source line layers 301 may be formed of a polysilicon layer doped with N-type impurities. Thereafter, an insulating layer 303 configured to cover the source line layers 301 and the gate stacked bodies GST may be formed. The insulating layer 303 may include oxide.
Referring to
Thereafter, an insulating layer 307 covering the first contacts 305A and the second contacts 305B may be formed on the insulating layer 303, and first contact pads 309A and second contact pads 309B coupled to the first contacts 305A and the second contacts 305B, respectively, may be formed in the insulating layer 307.
As described above, according to the embodiment of the present disclosure, the third material layers 129 used as word lines may be formed to extend in the direction of the surfaces of the gate stacked bodies GST in the word line contact region WCR, and may be formed such that the ends of the third material layers 129 are exposed in the word line contact region WCR during the process of removing the first substrate (e.g., 101 of
Referring to
The semiconductor memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips. The semiconductor memory device 1120 may be the semiconductor memory devices described with reference to
The memory controller 1110 may control the semiconductor memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as a working memory of the CPU 1112, the CPU 1112 may perform overall control operations for data exchange of the memory controller 1110, and the host interface 1113 may be provided with a data exchange protocol of a host coupled to the memory system 1100. Further, the error correction block 1114 detects and corrects an error included in data that is read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. In addition, the memory controller 1110 may further include a read only memory (ROM) or the like that stores code data for interfacing with the host.
The above-described memory system 1100 may be a memory card or a solid state drive (or a solid state disk: SSD) in which the semiconductor memory device 1120 and the memory controller 1110 are combined with each other. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., host) through one of various interface protocols, such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnection-express (PCI-E), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and Integrated Drive Electronics (IDE).
According to an embodiment of the present disclosure, by extending a plurality of interlayer insulating layers and a plurality of conductive patterns, which extend in a horizontal direction in a cell region, in a vertical direction in a word line contact region, the plurality of interlayer insulating layers and the plurality of conductive patterns may be exposed to the upper surface or the lower surface of a gate stacked body, thus enabling the conductive patterns to be coupled to contacts.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0066024 | May 2023 | KR | national |
