Patent Application
20250022860
This application claims priority to and the benefit thereof under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0091955, filed Jul. 14, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a semiconductor package and a manufacturing method thereof.
As a device for supplying a power to semiconductor chips in a semiconductor package, a power distribution module (PDM) is used. The power distribution module (PDM) has a function of distributing a single power supply supplied from the outside of the semiconductor package differently according to the semiconductor chips and supplying the distributed power to each of the semiconductor chips.
Meanwhile, since the semiconductor chips have a fine pitch I/O, to be electrically connected to a substrate having a normal pitch I/O, an interposer is required as an intermediary between the semiconductor chips and the substrate. Therefore, conventionally, since the power distribution module (PDM) was disposed on the substrate, and the power distributed from the power distribution module (PDM) reaches the individual semiconductor chips through the substrate and the interposer between the semiconductor chips and the substrate, every time it passes through a node, the voltage decreases, resulting in a significant deterioration in a power transmission efficiency.
Therefore, it is desirable to develop a new package technology that may solve this problem.
A power distribution structure including a power distribution module (PDM) and a surface mounting device (SMD), and a composite interposer including a redistribution structure on the power distribution structure may be disposed between the semiconductor chips and the substrate.
A semiconductor package according to an embodiment includes an interposer including a power distribution structure, and a redistribution structure on the power distribution structure; a first semiconductor die on the interposer; and a second semiconductor die on the interposer, wherein the power distribution structure may include a power distribution module connected to a bottom surface of the redistribution structure; a plurality of conductive posts connected to the bottom surface of the redistribution structure; and a molding material molding the power distribution module and the plurality of conductive posts.
A semiconductor package according to an embodiment includes an interposer including a power distribution structure and a redistribution structure on the power distribution structure; a plurality of external connection members connected to a bottom surface of the interposer; a first semiconductor die on the interposer; and a second semiconductor die on the interposer, wherein the power distribution structure may include a power distribution module connected to a bottom surface of the redistribution structure; a surface mounting device connected to the bottom surface of the redistribution structure; a plurality of conductive posts connected to the bottom surface of the redistribution structure, wherein each conductive post of the plurality of conductive posts electrically connects the redistribution structure to an external connection member of the plurality of external connection members; and a molding material for molding the side surface of the plurality of conductive posts, the power distribution module, and the surface mounting device.
A method of manufacturing a semiconductor package according to an embodiment includes forming a redistribution structure on a carrier; forming a plurality of conductive posts on a first surface of the redistribution structure; mounting a power distribution module on the first surface of the redistribution structure; molding the power distribution module and the plurality of conductive posts with a first molding material on the first surface of the redistribution structure; removing the carrier from the redistribution structure; and mounting a logic die and a memory die on a second surface that is an opposite side to the first surface of the redistribution structure.
The power distribution structure including the power distribution module (PDM) and the surface mounting device (SMD), and the composite interposer including the redistribution structure on the power distribution structure may be disposed between the semiconductor chips and the substrate.
As a result, it is possible to significantly shorten the power transmission path from the power distribution module (PDM) and the surface mounting device (SMD) to the individual semiconductor chip, thereby removing a parasitic resistance in the substrate, increasing a power efficiency, and improving a power control response time.
Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the attached drawings so that the person of ordinary skill in the art may easily implement the inventive concept. However, the inventive concept may be modified in various ways and is not limited to the examples described herein.
In the drawings, elements irrelevant to the description of the inventive concept are omitted for simplicity of explanation, and like reference numerals designate like elements throughout the specification.
Further, since sizes and thicknesses of constituent members shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, the inventive concept is not limited to the illustrated sizes and thicknesses.
Throughout the specification, when it is described that a part is “connected” to another part, the part may be “directly connected” to the other element or “connected” to the other part through a third part (e.g., intervening elements may be present). In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact.
In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, in the specification, the word “on” or “above” means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction.
Further, in the specification, the phrase “on a plane” means when an object portion is viewed from above, and the phrase “on a cross-section” means when a cross-section taken by vertically cutting an object portion is viewed from the side.
Hereinafter, a semiconductor package and a manufacturing method of a semiconductor package of an example embodiment will be described with reference to drawings.
Referring to
In an embodiment, the semiconductor package 100 may include a 2.5D semiconductor package. In an embodiment, the semiconductor package 100 may include a fan out wafer level package (FOWLP) or a fan out panel level package (FOPLP).
The external connection structure 110 may be disposed on the bottom surface of the composite interposer 140. The external connection structure 110 may include conductive pads 111, an insulation layer 112, and external connection members 113. The conductive pads 111 may electrically connect the conductive posts 121 of the power distribution structure 120 to the external connection members 113. Each conductive pad 111 may contact one of the conductive posts 121 and a corresponding one of the external connection members 113. The insulation layer 112 may include a plurality of openings for a soldering. The insulation layer 112 may prevent the external connection members 113 from being short-circuited with each other. The external connection members 113 may electrically connect the semiconductor package 100 to a substrate (not shown) or an external device (not shown). An upper surface of the insulation layer 112 may be at a higher level than upper surfaces of the external connection members 113, and a bottom surface of the insulation layer 112 may be at a lower level than bottom surfaces of the external connection members 113. For example, bottom surfaces of the external connection members 113 may be recessed from the bottom surface of the insulation layer 112.
The composite interposer 140 may include a power distribution structure 120 and a redistribution structure 130. The composite interposer 140 serves as an intermediate medium electrically connecting the first semiconductor die 160 and the second semiconductor die 170 having an I/O of a fine pitch to a substrate (not shown) having an I/O of a normal pitch.
The power distribution structure 120 may include conductive posts 121, a power distribution module (PDM) 122, a surface mounting device (SMD) 123, and a first molding material 124. The external connection structure 110 may be disposed on the bottom surface of the power distribution structure 120. The redistribution structure 130 may be disposed on the upper surface of the power distribution structure 120. In example embodiments, the surface mounting device (SMD) 123 may be a plurality of a surface mounting devices (SMD) 123.
The conductive posts 121 may be disposed between the conductive pads 111 of the external connection structure 110 and the first redistribution lines 131 of the redistribution structure 130. The conductive posts 121 may electrically connect the first redistribution lines 131 of the redistribution structure 130 to the conductive pads 111 of the external connection structure 110. In example embodiments, upper surfaces of the conductive posts 121 may contact bottom surfaces of the first redistribution lines 131, and bottom surfaces of the conductive posts 121 may contact upper surfaces of the conductive pads 111. The conductive posts 121 may be disposed to penetrate the first molding material 124. The side surfaces of the conductive posts 121 may be surrounded by the first molding material 124. For example, the first molding material 124 may contact the side surfaces of the conductive posts 121.
The power distribution module (PDM) 122 may be disposed on the bottom surface of the first redistribution lines 131 of the redistribution structure 130. The power distribution module (PDM) 122 may be directly electrically connected to the first redistribution lines 131 of the redistribution structure 130. In an embodiment, the power distribution module (PDM) 122 may be electrically connected only through the first redistribution lines 131 of the redistribution structure 130. The power distribution module (PDM) 122 may be embedded in the first molding material 124 except for a portion in contact with the bottom surface of the first redistribution lines 131. For example, an upper surface of the power distribution module (PDM) 122 may be lower than an upper surface of the first molding material 124. In example embodiments, the first molding material 124 may surround the power distribution module (PDM) 122, and may contact a bottom surface, side surfaces, and a portion of the upper surface of the power distribution module (PDM) 122. The power distribution module (PDM) 122 may include connection members 125. In an embodiment, the connection members 125 may include micro bumps. The connection members 125 may electrically connect the power distribution module (PDM) 122 to the first redistribution lines 131 of the redistribution structure 130. For example, the connection members 125 may be disposed between the power distribution module (PDM) 122 and the first redistribution lines 131, and may contact the power distribution module (PDM) 122 and the first redistribution lines 131. In example embodiments, the first molding material 124 may surround side surfaces of the connection members 125, and may contact the side surfaces of the connection members 125.
The power distribution module (PDM) 122 is a device that supplies a power to semiconductor chips. The power distribution module (PDM) 122 has a function of distributing a single power supply supplied from the outside of the semiconductor package differently according to the semiconductor chips and supplying the distributed power to each of the semiconductor chips. For example, the power distribution module (PDM) 122 may receive power from a single power source, and distribute the received power to the semiconductor chips based on individual power requirements of the semiconductor chips. In an embodiment, the power distribution module (PDM) 122 may include at least one of a controller, a buck converter, a capacitor, a resistor, and an inductor. In an embodiment, the power distribution module (PDM) 122 may include a regulator.
The surface mounting device (SMD) 123 may be disposed on the bottom surface of the first redistribution line 131 of the redistribution structure 130. The surface mounting device (SMD) 123 may be directly electrically connected to the first redistribution line 131 of the redistribution structure 130. In an embodiment, the surface mounting device (SMD) 123 may be electrically connected only through the first redistribution line 131 of the redistribution structure 130. The surface mounting device (SMD) 123 may be embedded in the first molding material 124 except for a portion in contact with the bottom surface of the first redistribution line 131. For example, an upper surface of the surface mounting device (SMD) 123 may be lower than an upper surface of the first molding material 124. In example embodiments, the first molding material 124 may surround the surface mounting device (SMD) 123, and may contact a bottom surface, side surfaces, and a portion of the upper surface of the surface mounting device (SMD) 123. The surface mounting device (SMD) 123 may provide additional functions or a programming to the entire semiconductor package 100. In an embodiment, the surface mounting device (SMD) 123 may include at least one of a resistor, an inductor, a capacitor, and a jumper. The surface mounting device (SMD) 123 may include connection members 126. In an embodiment, the connection members 126 may include micro bumps. The connection members 126 may electrically connect the surface mounting device (SMD) 123 to the first redistribution lines 131 of the redistribution structure 130. For example, the connection members 126 may be disposed between the surface mounting device (SMD) 123 and the first redistribution lines 131, and may contact the surface mounting device (SMD) 123 and the first redistribution lines 131. In example embodiments, the first molding material 124 may surround side surfaces of the connection members 126, and may contact the side surfaces of the connection members 126.
In an embodiment, the surface mounting device (SMD) 123 may include an integrated stack capacitor (ISC) chip. The integrated stack capacitor (ISC) chip is a chip including a capacitor structure that is continuously extended in a vertical cylinder structure in which tens of thousands or more are arranged. The integrated stack capacitor (ISC) chip may suppress a power noise in a high frequency band of hundreds of MHz and has a much larger capacitance density than a multilayer ceramic capacitor (MLCC) or a land side capacitor (LSC). By including these integrated stack capacitor (ISC) chips in the composite interposer 140, a power transmission path to the first semiconductor die 160 and the second semiconductor die 170 may be significantly shortened, and a power integrity (PI) of the semiconductor package 100 may be improved.
The first molding material 124 may be disposed between the external connection structure 110 and the redistribution structure 130, and may mold the side surface of the conductive posts 121, the power distribution module (PDM) 122, and the surface mounting device (SMD) 123.
In the power distribution structure 120 including the power distribution module (PDM) 122 that distributes the single supply power supplied from the outside of the semiconductor package differently according to the semiconductor chips, the input voltage of the power distribution structure 120 may be higher than the output voltage of the power distribution structure 120, and the output current of the power distribution structure 120 may be higher than the input current of the power distribution structure 120.
According to the present disclosure, the power transmission path from the power distribution module (PDM) 122 and the surface mounting device (SMD) 123 to the first semiconductor die 160 and the second semiconductor die 170 may be greatly shortened, it may remove a parasitic resistance in the substrate, increase a power efficiency, and improve a power control response time.
The redistribution structure 130 may be disposed on the power distribution structure 120. The redistribution structure 130 may include a dielectric material layer 138. In addition, the redistribution structure 130 may include first redistribution lines 131, first redistribution vias 132, second redistribution lines 133, second redistribution vias 134, third redistribution lines 135, third redistribution vias 136, and fourth redistribution lines 137, which are disposed within the dielectric material layer 138. In another embodiment, the redistribution structure 130 including fewer or greater numbers of redistribution lines and redistribution vias is included within the scope of the present disclosure.
The dielectric material layer 138 may protect and insulate the first redistribution lines 131, the first redistribution vias 132, the second redistribution lines 133, the second redistribution vias 134, the third redistribution lines 135, the third redistribution vias 136, and the fourth redistribution lines 137. A first molding material 124 may be disposed under the bottom surface of the dielectric material layer 138, and an insulating member 153 and a second molding material 180 may be disposed on the upper surface of the dielectric material layer 138. For example, the first molding material 124 may contact the bottom surface of the dielectric material layer 138, and the insulating member 153 and the second molding material 180 may contact the upper surface of the dielectric material layer 138.
The first redistribution lines 131 may be disposed between the first redistribution vias 132 and the conductive posts 121, between the first redistribution vias 132 and the power distribution module (PDM) 122, and between the first redistribution vias 132 and the surface mounting device (SMD) 123. The first redistribution lines 131 may electrically connect the first redistribution vias 132 to the conductive posts 121, the power distribution module (PDM) 122, and the surface mounting device (SMD) 123 in a horizontal direction. The first redistribution vias 132 may be disposed between the second redistribution lines 133 and the first redistribution lines 131. The first redistribution vias 132 may electrically connect the second redistribution lines 133 to the first redistribution lines 131 in a vertical direction. The second redistribution lines 133 may be disposed between the second redistribution vias 134 and the first redistribution vias 132. The second redistribution lines 133 may electrically connect the second redistribution vias 134 to the first redistribution vias 132 in a horizontal direction. The second redistribution vias 134 may be disposed between the third redistribution lines 135 and the second redistribution lines 133. The second redistribution vias 134 may electrically connect the third redistribution lines 135 to the second redistribution lines 133 in a vertical direction. The third redistribution lines 135 may be disposed between the third redistribution vias 136 and the second redistribution vias 134. The third redistribution lines 135 may electrically connect the third redistribution vias 136 to the second redistribution vias 134 in a horizontal direction. The third redistribution vias 136 may be disposed between the fourth redistribution lines 137 and the third redistribution lines 135. The third redistribution vias 136 may electrically connect the fourth redistribution lines 137 to the third redistribution lines 135 in a vertical direction. The fourth redistribution lines 137 may be disposed between the connection members 152 of the interconnect structure 150 and the third redistribution vias 136. The fourth redistribution lines 137 may electrically connect the connection members 152 of the interconnect structure 150 to the third redistribution vias 136. In an embodiment, the first redistribution vias 132, the second redistribution vias 134, and the third redistribution vias 136 may have the width of the uppermost part smaller than the width of the lowermost part. For example, each of the first redistribution vias 132, the second redistribution vias 134, and the third redistribution vias 136 may have a tapered shape.
The first semiconductor die 160 may be disposed on the redistribution structure 130 of the composite interposer 140. The first semiconductor die 160 may be electrically connected to the redistribution structure 130 by the connection pads 151 and the connection members 152 of the interconnect structure 150. For example, a bottom surface of the first semiconductor die 160 may contact the connection pads 151. In an embodiment, the first semiconductor die 160 may include a logic die. In an embodiment, the first semiconductor die 160 may include a system on chip (SoC). In an embodiment, the first semiconductor die 160 may include at least one of a central processing unit (CPU), a graphic processing unit (GPU), a memory, a controller, a codec, a sensor, and a communication unit.
The second semiconductor die 170 may be disposed on the redistribution structure 130 of the composite interposer 140. The second semiconductor die 170 may be electrically connected to the redistribution structure 130 by the connection pads 151 and the connection members 152 of the interconnect structure 150. For example, a bottom surface of the second semiconductor die 170 may contact the connection pads 151. The second semiconductor die 170 may be disposed side by side with the first semiconductor die 160. In an embodiment, the second semiconductor die 170 may include a high bandwidth memory (HBM). The high-bandwidth memory (HBM) is a high performance three-dimensional 3D stacked dynamic random access memory (DRAM). The high-bandwidth memory (HBM) may be manufactured by performing a hybrid bonding or by vertically stacking memory dies on a buffer chip by using micro bumps to form a single memory stack.
The interconnect structure 150 may be disposed between the first semiconductor die 160 and the redistribution structure 130 and between the second semiconductor die 170 and the redistribution structure 130. The interconnect structure 150 may include connection pads 151, connection members 152, and an insulating member 153. The connection pads 151 may be disposed between the first semiconductor die 160 and the connection members 152 and between the second semiconductor die 170 and the connection members 152. The connection pads 151 may electrically connect the first semiconductor die 160 and the connection members 152, and the second semiconductor die 170 and the connection members 152. The connection members 152 may be disposed between the connection pads 151 and the fourth redistribution lines 137 of the redistribution structure 130. The connection members 152 may electrically connect the connection pads 151 and the fourth redistribution lines 137 of the redistribution structure 130. In an embodiment, the connection members 152 may include micro bumps. The insulating member 153 may surround and protect the connection pads 151 and the connection members 152 between the first semiconductor die 160 and the second semiconductor die 170. In an embodiment, the insulating member 153 may include a non-conductive film (NCF).
The second molding material 180 may be disposed on the redistribution structure 130 and mold the insulating member 153, the first semiconductor die 160, and the second semiconductor die 170. The upper surface of the first semiconductor die 160 and the upper surface of the second semiconductor die 170 may be externally exposed from the second molding material 180. For example, upper surfaces of the second semiconductor die 170 and the first semiconductor die 160 may be coplanar.
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After forming the dielectric material layer 138, openings may be formed by selectively etching the dielectric material layer 138, and fourth redistribution lines 137 may be formed by filling the openings with a conducting material.
Then, a dielectric material layer 138 may be additionally deposited on the fourth redistribution lines 137 and the dielectric material layer 138, the additionally deposited dielectric material layer 138 may be selectively etched to form via holes, and the via holes may be filled with a conducting material to form third redistribution vias 136.
Then, a dielectric material layer 138 may be additionally deposited on the third redistribution vias 136 and the dielectric material layer 138, and the additionally deposited dielectric material layer 138 may be selectively etched to form openings, and third redistribution lines 135 may be formed by filling a conducting material in the openings.
Next, a dielectric material layer 138 may be additionally deposited on the third redistribution lines 135 and the dielectric material layer 138, the additionally deposited dielectric material layer 138 may be selectively etched to form via holes, and the via holes may be filled with a conducting material to form second redistribution vias 134.
Then, a dielectric material layer 138 may be additionally deposited on the second redistribution vias 134 and the dielectric material layer 138, and the additionally deposited dielectric material layer 138 may be selectively etched to form openings, and the openings may be filled with a conducting material to form second redistribution lines 133.
Then, a dielectric material layer 138 may be additionally deposited on the second redistribution lines 133 and the dielectric material layer 138, the additionally deposited dielectric material layer 138 may be selectively etched to form via holes, and the via holes may be filled with a conducting material to form first redistribution vias 132.
Then, a dielectric material layer 138 may be additionally deposited on the first redistribution vias 132 and dielectric material layer 138, and the additionally deposited dielectric material layer 138 may be selectively etched to form openings, and first redistribution lines 131 may be formed by filling a conducting material in the openings.
After the redistribution structure 130 is completed on the carrier 190, a surface of the redistribution structure 130 far from the carrier 190 may be defined as a first surface, and a surface of the redistribution structure 130 in contact with the carrier 190 may be defined as a second surface. The second face may be defined as the opposite surface to the first face.
The width of the uppermost portion of each of the redistribution vias in the first redistribution vias 132, the second redistribution vias 134, and the third redistribution vias 136 may be greater than that of the lowermost portion. In the subsequent process, since a composite interposer 140 in which the redistribution structure 130 is formed is turned over to produce a final product, the width of the uppermost portion of each redistribution via in the first redistribution vias 132, the second redistribution vias 134, and the third redistribution vias 136 in the final product may be smaller than the width of the lowermost portion.
In an embodiment, the first redistribution lines 131, the first redistribution vias 132, the second redistribution lines 133, the second redistribution vias 134, the third redistribution lines 135, the third redistribution vias 136, and the fourth redistribution lines 137 may be formed of or include at least one of copper, aluminum, tungsten, nickel, and gold, tin, titanium and their alloys, respectively. In an embodiment, the first redistribution lines 131, the first redistribution vias 132, the second redistribution lines 133, the second redistribution vias 134, the third redistribution lines 135, the third redistribution vias 136, and the fourth redistribution lines 137 may be formed by performing a sputtering process. In another embodiment, the first redistribution lines 131, the first redistribution vias 132, the second redistribution lines 133, the second redistribution vias 134, the third redistribution lines 135, the third redistribution vias 136, and the fourth redistribution lines 137 may be formed by performing an electrolytic plating process after forming a seed metal layer.
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While this inventive concept has been described in connection with what is presently considered to be example embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0091955 | Jul 2023 | KR | national |
