Claims
- 1. A semiconductor package comprising:
(a) a package base; (b) package terminals formed on the package base and adapted to connect the semiconductor package to an external device; (c) a wiring layer formed on the package base and electrically connected to the package terminals; (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer; (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold; and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer,
the low-elasticity resin layer having a lower elasticity modulus than the resin mold.
- 2. The semiconductor package of claim 1, wherein the low-elasticity resin layer is disposed only between the wiring layer and the resin mold.
- 3. The semiconductor package of claim 1, wherein the low-elasticity resin layer is disposed between the wiring layer and the resin mold above the package terminals.
- 4. The semiconductor package of claim 1, wherein the low-elasticity resin layer is disposed between the wiring layer and the resin mold above package terminals where maximum strain is experienced.
- 5. The semiconductor package of claim 1, wherein electric contacts between the wiring layer and the semiconductor chip are sealed with an underfill resin layer.
- 6. A method of manufacturing a semiconductor package, comprising:
(a) forming a wiring layer on a package base; (b) electrically connecting a semiconductor chip to the wiring layer; (c) forming a low-elasticity resin layer having a lower elasticity modulus than a resin mold, on the package base and the wiring layer; and (d) forming the resin mold on the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
- 7. The method of claim 6, wherein said forming the low-elasticity resin layer is configured such that the low-elasticity resin layer is selectively formed only between the wiring layer and the resin mold.
- 8. The method of claim 6, wherein said forming the low-elasticity resin layer is configured such that the low-elasticity resin layer is selectively formed between the wiring layer and the resin mold above package terminals.
- 9. The method of claim 6, wherein said forming the low-elasticity resin layer is configured such that the low-elasticity resin layer is selectively formed between the wiring layer and the resin mold above package terminals where maximum strain is experienced.
- 10. The method of claim 6, further comprising: sealing electric contacts between the wiring layer and the semiconductor chip with an underfill resin layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
P2001-101840 |
Mar 2001 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-101840 filed on Mar. 30, 2001, the entire contents of which are incorporated herein by reference.