1. Field of the Invention
The present invention relates to an insulated-gate semiconductor power device and to the manufacturing process thereof. More specifically, the invention relates to a power MOS device of the type comprising a trench used for insulating the gate region of the device (hereinafter indicated as power MOS device of the trench-gate type).
The invention relates, in particular, but not exclusively, to a power MOS device or a device of the IGBT (Insulated-Gate Bipolar Transistor) type, and the following description is made with reference to this application field, with the only purpose of simplifying its exposition.
2. Description of the Related Art
As is known, power MOS devices comprise a plurality of cells, each having a gate region adjacent to body and source regions. In the manufacturing process of trench-gate power MOS devices, the gate of the MOS structure is formed in each elementary cell of the device by making, in the silicon substrate, a trench, the walls whereof are coated with a thin oxide layer, referred to as gate oxide, and by then completely filling the trench with polysilicon. In this structure, the channel of the device is formed along the vertical walls of the trench.
This MOS structure, formed by stacking silicon, oxide, and polycrystalline silicon, has considerable advantages with respect to a device obtained with planar technology. In fact, the resistance associated to the JFET area, due to the opposed body wells of the device, is totally eliminated, thus improving the conduction characteristic of the device. Furthermore, the dimensions of the device are accordingly scaled, with consequent increase in the current-carrying capability.
On the other hand, this structure presents some problems. In fact, in the bottom area of the trench a densification of the lines of the electric field is created, which determines, given the same current-carrying capacity, a decrease in the breakdown voltage of the device.
Furthermore, as compared to a planar structure, there arises, given the same active area, a considerable increase in the area of the gate oxide, also in useless areas, where the channel is not formed, i.e., in those parts of the gate oxide that extend underneath the body region. The increase in area occupied by the gate oxide leads to an increase in the parasitic capacitances linked to the gate terminal of the device and, hence, of the gate charge, as compared to the planar structures.
The first problem (crowding of the electric-field lines) is currently solved by making the trench with a U-shaped profile, rounded at its bottom end. In this way, in fact, the resistance to breakdown of the device is improved.
The second problem (increase in the gate oxide area), instead, is solved either by depositing a thick oxide layer in the trench so as to coat only the bottom of the trench following its U-shaped profile and thus forming a double layer of gate oxide in the bottom part of the trench (see, for example, U.S. Pat. No. 6,528,355 B2), or by depositing a thick oxide layer in the trench to coat the bottom of the trench and fill it up to a certain height.
The advantages of the above two process solutions are numerous:
the breakdown voltage of the device increases because the thick oxide layer performs the function of “field ring”, i.e., that of preventing crowding of the electric field lines at the bottom of the trench;
the breakdown voltage of the gate oxide increases because the thin gate oxide no longer comprises the part of the wall where there is a variation of crystallographic orientation of the silicon; in this area, in fact, the thickness of the gate oxide is not controllable and could cause premature failure of the device;
the parasitic capacitance associated to the gate terminal of the device decreases.
In practice, a favorable compromise is created between the increase in the breakdown voltage and the reduction of the output resistance of the device.
In particular, the solution that envisages a U-shaped thick oxide on the bottom of the trench provides better performance as regards the improvement of the breakdown voltage (higher values are obtained), while the second solution (thick oxide that completely fills the bottom of the trench) behaves relatively better in regard to parasitic capacitance.
One embodiment of the present invention provides a power device of the type referred to above that yields a better compromise as to the two above aspects so as to present a substantially improved behavior as regards both breakdown and parasitic capacitance.
In practice, to reconcile both the static aspect and the dynamic aspect of the device, the polysilicon region that fills the trench is divided into two parts with different physical and electrical characteristics. According to one embodiment of the invention, the bottom part is formed by a lightly doped polysilicon of a type opposite to the polysilicon of the top part (which forms the gate region) so as to function as an electrode with reverse biasing. In this way, the device maintains the breakdown gain of the known solution described above with U-shaped thick oxide and has an improved dynamic behaviour in so far as the bottom part of polysilicon can undergo depletion during switching and thus provides a minor contribution to the capacitance of the polysilicon region.
For a better understanding of the invention, some preferred embodiments thereof are now described purely by way of non-limiting example and with reference to the attached drawings, wherein:
FIGS. 1 to 11 show cross-sections through a semiconductor wafer in successive manufacturing steps of the device, according to a first embodiment of the invention;
After manufacturing edge structures and opening the active area, body regions 7 of P-type are blanket-implanted, for example, by doping the silicon with B, BF2, Al, or In. In a way not shown, a deep enrichment of the body regions (deep body) is possibly effected in accordance with the prior art, by implanting dopants of P+ type using a resist mask; then, using another resist mask, source regions 8 of N+ type are implanted, for example, by doping silicon with As, Sb or P.
On the top surface 3 of the epitaxial layer 2 a dielectric layer is then formed, for example of deposited or thermally grown silicon oxide, or of deposited silicon nitride, or of a combination of the two materials, so as to obtain an overall thickness of 0.2-1 μm. The dielectric layer is then defined so as to form a trench mask 4 used for anisotropically dry etching the epitaxial layer 2 and forming a trench 5. The structure of
As is illustrated in
Then (
Next (
Then (
After carrying out a pad oxidation, which leads to the growth of a thin silicon oxide layer (for example of 5-25 nm, not illustrated) on the walls of the trench 5 and on the surface 3 of the epitaxial layer 2, a nitride layer 16 is deposited (
The nitride layer 16 and the thin silicon oxide layer are then wet etched, whereby the nitride layer 16 and the thin silicon oxide layer are completely removed, except for the filling portions 17. Then (
Finally, the process goes ahead with covering the structure of
In this way, the polysilicon region that fills the trench is formed by two portions (the conductive region 11 and the gate region 20) with different characteristics: the conductive region 11 is in fact of P or N type, lightly doped, and is able to withstand higher breakdown voltages with a reverse biasing; moreover, it does not contribute to the parasitic capacitance associated to the gate region, while the gate region 20 can operate properly.
Furthermore, if the modified-conductivity region 21 is obtained by implant after forming the trench 5, when the trench mask 4 is still present, no other photolithographic processes for defining the implant regions are necessary. The process is consequently self-aligned with the pre-existing geometries of the device and does not lead to a sensible increase in costs.
Thereby, since the surface 3 of the epitaxial layer 2 is coated with the gate insulating layer 18, the metal layer 22 is formed only on top of the surface of the gate region 20, in a self-aligned way, i.e., it does not involve the use of additional photolithographic techniques. This variant of the method thus enables a reduction in the gate resistance to be obtained, which gate is here formed by the parallel connection of the gate region 20, of polycrystalline silicon, and of the metal layer 22, without any sensible increase in the production costs.
Finally,
In this way, the masking step for selective formation of source regions 8 is eliminated.
Finally, it is evident that modifications and variations can be made to the device and to the manufacturing process described herein, without departing from the scope of the present invention.
For example, the described process for forming N-channel insulated-gate power devices can likewise be applied for forming P-channel insulated-gate power devices by reversing the conductivity of the silicon substrate 1, of the epitaxial layer 2, and of the dopant species implanted in the body regions 7 and source regions 8, 8′.
All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.
Number | Date | Country | Kind |
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TO2005A 000630 | Sep 2005 | IT | national |