Patent Application
20200006212
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic products, including for example digital cameras, digital music players, video game consoles, computer SSDs, PDAs and cellular telephones.
While many varied packaging configurations are known, flash memory semiconductor products may in general be fabricated as system-in-a-package (SIP) or multichip modules (MCM), where a plurality of semiconductor die are mounted and interconnected to an upper surface of a small footprint substrate. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Solder balls are often mounted on contact pads formed on a lower surface of the substrate to allow the substrate to be soldered to a host device such as a printed circuit board. Once mounted, signals may be transferred between the semiconductor die and the host device via the substrate.
In conventional board level semiconductor product, mechanical stresses often generate at the solder ball junction between substrate pad and PCB (printed circuit board) pad. For example, these stresses can be generated as a result of different coefficients of thermal expansion of the semiconductor package and PCB, for example during thermal cycling tests of the board level semiconductor product. These stresses can also be generated as a result of impact shock to the solder balls, for example during drop testing of the semiconductor product. Such stresses can result in cracks to the solder balls, separation of the solder balls from the contact pads and/or breakage of the trace at the connection point to the contact pad, all of which can result in board level reliability (BLR) failure.
The present technology will now be described with reference to the figures, which in embodiments, relate to a substrate having a stress relief layer. The stress relief layer may be applied to a dielectric core of the substrate, beneath a conductive layer in which electrical traces and contact pads are formed. The substrate including the stress relief layer may be incorporated into a semiconductor product which may, for example, be mounted on a host printed circuit board using solder balls on a surface of the substrate. The stress relief layer helps dissipate stresses within the substrate and improves the board level reliability.
It is understood that the present technology may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the technology to those skilled in the art. Indeed, the technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be clear to those of ordinary skill in the art that the present technology may be practiced without such specific details.
The terms “top” and “bottom,” “upper” and “lower” and “vertical” and “horizontal” as may be used herein are by way of example and illustrative purposes only, and are not meant to limit the description of the technology inasmuch as the referenced item can be exchanged in position and orientation. Also, as used herein, the terms “substantially,” “approximately” and/or “about” mean that the specified dimension or parameter may be varied within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±2.5% of a given dimension.
An embodiment of the present technology will now be explained with reference to the flowchart of
The substrate panel for the fabrication of semiconductor product 150 begins with a plurality of substrates 100 (again, one such substrate is shown in
In accordance with aspects of the present technology, a stress relief layer 103 may be formed on the dielectric core 102 in step 200, as shown in the edge and bottom views of
Further properties of the stress relief layer 103 may include a Poisson's ratio of 0.25 to 0.5 such as for example 0.33 to 0.35. It may have a coefficient of thermal expansion ranging between 20 PPM and 60 PPM, such as for example 30 PPM. The stress relief layer 103 may be applied to the dielectric core 102 by any of a variety of processes, including for example thin film deposition, vapor deposition, printing, spin coating, dry film lamination or other methods. In embodiments, the stress relief layer 103 may be applied to a single major planar surface of the dielectric core 102. However, the stress relief layer 103 may be applied to both major planar surfaces of the dielectric core 102 in further embodiments.
In step 204, conductive layers 104 and 105 may next be formed on the exposed planar surfaces of the substrate 100, as shown in the edge and top views of
The conductive layers 104, 105 may be formed of copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42Fe/58Ni), copper plated steel, or other metals and materials suitable for use on substrate panels. The conductive layers 104, 105 may have a thickness of about 8 μm to 40 μm, although the thickness of the layers may vary outside of that range in alternative embodiments.
In a step 210, a conductive pattern of vias, leads and/or pads are formed in and through the substrate 100. The substrate 100 may drilled to define through-hole vias 106, which are subsequently plated and/or filled with a conductive metal. A conductance pattern of electrical traces 108 and contact pads 110 may then be formed on the top and/or bottom major planar surfaces of substrate 100.
The pattern of vias, 106, traces 108 and contact pads 110 shown on surfaces 112 and 114 in the figures are by way of example, and the substrate 100 may include more or less vias, traces and/or contact pads in further embodiments, and they may be in different locations in further embodiments. The conductance pattern on the top and/or bottom surfaces of the substrate 100 may be formed by a variety of known processes, including for example various photolithographic processes.
Referring again to
Assuming the substrate 100 passes inspection, passive components 122 (
In embodiments, the present technology may relate to the substrate 100 described above and shown for example in
The above-described substrate 100 may have a thickness ranging between 0.05 mm and 0.3 mm, and more particularly 0.08 mm or 0.21 mm. It is understood that the substrate 100 may have other thicknesses in further embodiments. In embodiments described above, the substrate 100 is a two layer substrate (two conductive layers sandwiched on a dielectric layer). In further embodiments, the substrate 100 may include more layers, such as for example a four layer substrate (four conductive layers interspersed around three dielectric layers).
In further embodiments, the present technology may relate to a semiconductor product 150 formed using the substrate 100 described above. In particular, in step 230, one or more semiconductor die 124 may be mounted on the substrate 100, as shown in the edge view of
Where multiple semiconductor die 124 are included, the semiconductor die 124 may be stacked atop each other in an offset stepped configuration to form a die stack as shown for example in
In step 234, the semiconductor die 124 may be electrically interconnected to each other and to the substrate 100.
Following electrical connection of the die 124 to the substrate 100, the semiconductor product 150 may be encapsulated in a mold compound 130 in a step 238 and as shown in
In step 240, solder balls 132 may be affixed to the contact pads 110 on a lower surface 114 of substrate 100 as shown in
As noted above, the semiconductor product 150 may be formed on a panel of substrates. After formation and encapsulation of the substrates 100, the substrates 100 may be singulated from each other in step 242 to form a finished semiconductor product 150 as shown in
The stress relief layer 103 according to the present technology is described above as a solid layer applied continuously over the dielectric core 102. However, it need not be in further embodiments.
Inclusion of the stress relief layer 103 within the substrate 100 serves to improve board level reliability (BLR) which may otherwise degrade without layer 103 due to thermal mismatch, impact shocks or other stress-generating forces on the substrate 100 and within semiconductor product 150. The layer 103 is able to absorb and dissipate stresses at the junction between the contact pads 110 and solder balls 132, as well as elsewhere in the substrate 100.
Strain energy density (SED) is a good indicator to evaluate BLR performance in mechanical testing of substrates. Table 1 below indicates a comparison of the SED for solder balls during thermal cycle testing on two different groups of substrates. The first group of substrates were conventional substrates without the stress relief layer 103 (SRL). The second group of substrates were examples of substrate 100 including the SRL. For each substrate in the two groups, SED was calculated based on the visco-plastic behavior of solder balls. The first solder ball on each substrate is referred to as an Anchor Ball (in the position of solder ball 132A in
The tests were performed by cycling each substrate in the first and second groups between −40° C. and 85° C., with a ramp time 15° C./min, and with a dwell time 15 mins.
In Test 1, the two substrates were both two layer substrates, 130 μm thick, with 60% copper routing coverage and no vias. As shown, the Anchor Ball and Function Ball of the substrate having the stress relief layer both had a lower measured SED than the substrate without the stress relief layer.
In Test 2, the two substrates were both four layer substrates, 170 μm thick, with 60% copper routing coverage and no vias. As shown, the Anchor Ball and Function Ball of the substrate having the stress relief layer both had a lower measured SED than the substrate without the stress relief layer.
In Test 3, the two substrates were both two layer substrates, 130 μm thick, with 40% copper routing coverage this time and no vias. As shown, the Anchor Ball and Function Ball of the substrate having the stress relief layer both had a lower measured SED than the substrate without the stress relief layer.
In Test 4, the two substrates were both two layer substrates, 130 μm thick, with 40% copper routing coverage and both included vias in this test. As shown, the Anchor Ball and Function Ball of the substrate having the stress relief layer both had a lower measured SED than the substrate without the stress relief layer.
As seen from the above tests, the inclusion of the stress release layer 103 within a substrate was effective at reducing Strain Energy Density and improving Board Level Reliability. Mechanical stresses on a substrate can also result in the substrate and/or semiconductor product warping. Testing of substrates including the stress relief layer 103 showed a reduction of 1-2 μm in warping over conventional substrates that were the same but did not include the stress relief layer.
In summary, in one example, the present technology relates to a substrate for use in a semiconductor product, comprising: a dielectric core having first and second major planar surfaces; a stress relief layer applied onto the first major planar surface of the dielectric core, the stress relief layer having a modulus less than a modulus of the dielectric core; a first conductive layer applied onto the second major planar surface of the dielectric core, the first conductive layer formed into a first conductive pattern; and a second conductive layer applied onto the stress relief layer, the second conductive layer formed into a second conductive pattern.
In another example, the present technology relates to a semiconductor product, comprising: a substrate, comprising: a dielectric core having a first major planar surface, a stress relief layer applied onto the first major planar surface of the dielectric core, the stress relief layer having a modulus less than a modulus of the dielectric core, and a first conductive layer applied onto the stress relief layer, the first conductive layer formed into a first conductive pattern; and one or more semiconductor die mounted on the substrate and electrically interconnected to the substrate.
In a further example, the present technology relates to a method of fabricating a substrate for a semiconductor product, comprising: (a) applying a dielectric film onto a dielectric core, the dielectric film having a lower modulus than the dielectric core; (b) applying a first conductive layer onto the dielectric core; (c) forming the first conductive layer into a first conductive pattern; (d) applying a second conductive layer onto the stress relief layer; (e) forming the second conductive layer into a second conductive pattern; and (f) affixing solder balls to the substrate, the dielectric film dissipating stresses between the solder balls and the substrate.
In another example, the present technology relates to a substrate for use in a semiconductor product, comprising: a dielectric core having first and second major planar surfaces; stress relief means, applied onto the first major planar surface of the dielectric core, for reducing mechanical stresses within the substrate; a first conductive layer applied onto the second major planar surface of the dielectric core, the first conductive layer formed into a first conductive pattern; and a second conductive layer applied onto the stress relief means, the second conductive layer formed into a second conductive pattern.
The foregoing detailed description of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the technology be defined by the claims appended hereto.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201810690328.9 | Jun 2018 | CN | national |
