This application claims priority to Chinese Patent Application No. 2022109812610 entitled “semiconductor structure and method for manufacturing semiconductor structure” filed on Aug. 16, 2022, the entire content of which is incorporated herein by reference.
The present disclosure relates to the field of semiconductor technologies, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure.
With the development of technologies, semiconductor structures have attracted more and more attentions.
Schottky diode is an important semiconductor structure, which has advantages of good reliability and easy circuit design, and the Schottky diode is widely used in fields of power electronics, microwave radio frequency, etc. An important technical index of Schottky diodes is the diode reverse breakdown voltage, which limits a performance and a reliability of a device. When manufacturing vertical Schottky diodes, many factors will affect the reverse breakdown voltage. For example, when using an etching process, the interface may be damaged and interface impurities may be introduced.
A purpose of the present disclosure is providing a method for manufacturing a semiconductor structure to avoid introduction of interface impurities.
According to an aspect of the present disclosure, a semiconductor structure is provided, including:
According to an aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, including:
According to embodiments of the present disclosure, the semiconductor structure and the method for manufacturing the semiconductor structure are provided. The second semiconductor layer is on the first surface of the first semiconductor layer, and since the first protrusions are formed at the first surface, the second protrusions are formed at a surface of the second semiconductor layer away from the first semiconductor layer. Compared with a method of forming the second protrusion by etching, the second semiconductor layer is prevented from being damaged by etching, thereby preventing an interface between the second semiconductor layer and the third semiconductor layer from being damaged, such that introduction of impurities at the interface can be avoided.
The exemplary embodiments will be described herein in detail, examples of which are represented in the accompanying drawings. When the following descriptions involve the drawings, like numerals in different drawings refer to like or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are only examples of devices and methods that are consistent with some aspects of the present application, as detailed in the appended claims.
The terms used in the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have their ordinary meanings as understood by those of ordinary skills in the field to which the present disclosure belongs. The “first”, “second” and similar words used in the specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as “a” or “an” do not mean quantity limitation but mean that there is at least one. “Multiple” or “a plurality of” means two or more. Unless otherwise specified, similar words such as “front”, “rear”, “lower” and/or “upper” are only for convenience of explanation and are not limited to a position or a spatial orientation. Similar words such as “include” or “comprise” mean that the elements or objects appear before “include” or “comprise” cover the elements or objects listed after “include” or “comprise” and their equivalents, but do not exclude other elements or objects. Similar words such as “connect” or “couple” are not limited to physical or mechanical connection, but may include electrical connection, whether direct or indirect. Singular forms “a”, “the” and “said” used in the specification of the present disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates other meaning. It should also be understood that the term “and/or” as used herein refers to and includes any or all possible combinations of one or more associated listed items.
According to an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided.
At step S100, a first semiconductor layer 1 is provided, where the first semiconductor layer 1 includes a first surface and a second surface which are opposite to each other, and first protrusions 102 are formed at the first surface.
At step S110, a second semiconductor layer 2 covering the first surface is formed, where second protrusions 202 are formed at a surface of the second semiconductor layer 2 away from the first semiconductor layer 1, the second protrusions 202 correspond to the first protrusions 102 respectively in position, a second recess 201 is formed between two adjacent second protrusions 202; a conductivity type of the second semiconductor layer 2 is the same as a conductivity type of the first semiconductor layer 1, and a doping concentration of the second semiconductor layer 2 is lower than a doping concentration of the first semiconductor layer 1.
At step S120, a third semiconductor layer 3 covering the second semiconductor layer 2 is formed, where a conductivity type of the third semiconductor layer 3 is opposite to the conductivity type of the first semiconductor layer 1.
In the method for manufacturing the semiconductor structure according to an embodiment of the present disclosure, the second semiconductor layer 2 is formed at the first surface of the first semiconductor layer 1, and since the first protrusions 101 are formed at the first surface, the second protrusions 102 are formed at a surface of the second semiconductor layer 2 away from the first semiconductor layer 1. Compared with a method of forming the second protrusion 202 by etching, the second semiconductor layer 2 is prevented from being damaged by etching, such that a damage at an interface of the second semiconductor layer 2 and the third semiconductor layer 3 may be avoided, and the introduction of impurities at the interface can be avoided.
According to the embodiments of the present disclosure, each step of the method for manufacturing the semiconductor structure will be described in detail as follows.
At step S100, a first semiconductor layer 1 is provided. The first semiconductor layer 1 includes a first surface and a second surface which are opposite to each other, and first protrusions 102 are formed at the first surface.
As shown in
The number of the first protrusions 102 may be multiple, and the first protrusions 102 are disposed apart. The horizontal projection of the first protrusion 102 may be a circle, or certainly, the horizontal projection of the first protrusion 102 may be in other shapes such as a strip, a rectangle, etc. As shown in
At step S110, a second semiconductor layer 2 covering the first surface is formed, where second protrusions 202 are formed at a surface of the second semiconductor layer 2 away from the first semiconductor layer 1, the second protrusions 202 correspond to the first protrusions 102 respectively in position, and a second recess 201 is formed between two adjacent second protrusions 202. A conductivity type of the second semiconductor layer 2 is the same as a conductivity type of the first semiconductor layer 1, and a doping concentration of the second semiconductor layer 2 is lower than a doping concentration of the first semiconductor layer 1.
The material of the second semiconductor layer 2 may be a III-V group compound. Specifically, the material of the second semiconductor layer 2 may be at least one of Si, SiC, GaN, Ga2O3, AlGaN, InGaN, or AlInGaN. The conductivity type of the second semiconductor layer 2 is the same as the conductivity type of the first semiconductor layer 1. Taking the first semiconductor layer 1 as an N-type semiconductor layer as an example, the second semiconductor layer 2 is also an N-type semiconductor layer. Taking the first semiconductor layer 1 as a P-type semiconductor layer as an example, the second semiconductor layer 2 is also a P-type semiconductor layer. The doping concentration of the second semiconductor layer 2 is lower than the doping concentration of the first semiconductor layer 1. Taking the first semiconductor layer 1 as an N-type heavily doped layer as an example, the second semiconductor layer 2 may be an N-type lightly doped layer, and the doping concentration of impurity ions in the second semiconductor layer 2 may be less than 1018/cm3. The second semiconductor layer 2 may be a single layer structure, or a laminated layer structure, and the material of each layer may be GaN, AlGaN or AlInGaN, or other semiconductor materials including Ga atom and N atom, or a combination thereof.
The number of the first protrusions 202 may be multiple. Further, the number of the second protrusions 202 may be the same as the number of the first protrusions 102, but this is not particularly limited in the embodiment of the present disclosure. Taking a horizontal projection of the first protrusion 102 as a strip as an example, as shown in
At step S120, a third semiconductor layer 3 covering the second semiconductor layer 2 is formed.
As shown in
Third protrusions 302 are conformally formed at a surface of the third semiconductor layer 3 away from the second semiconductor layer 2, and the third protrusions 302 correspond to the second protrusions 202 respectively in position. Certainly, in other embodiments, the surface of the third semiconductor layer 3 away from the second semiconductor layer 2 may be a plane, and the second recess 201 may be filled up with the third semiconductor layer 3, but the present disclosure does not make any special limitation thereto.
The number of the third protrusions 302 may be multiple. Further, the number of the third protrusions 302 may be the same as the number of the second protrusions 202, but this is not particularly limited in the embodiment of the present disclosure. The horizontal projection of the third protrusion 302 may be in a shape of a strip. Taking the number of third protrusions 302 as multiple as an example, the strip-shaped third protrusions 302 may be disposed in parallel and distributed apart. The horizontal width of the strip-shaped second protrusion 202 may be greater than the horizontal width of the strip-shaped third protrusion 302, or certainly, the horizontal width of the strip-shaped second protrusion 202 may be smaller than the strip-shaped third protrusion 302. In addition, a third recess 301 is formed between two adjacent third protrusions 302.
The third semiconductor layer 3 may be formed by epitaxial growth, which is not limited in the embodiments of the present disclosure. The third protrusion 302 may be conformally formed during the epitaxial growth process of the third semiconductor layer 3.
According to an embodiment of the present disclosure, a method for manufacturing the semiconductor structure may further include steps as following.
At step S130, a portion of the third semiconductor layer 3 is etched to expose a top surface of the second protrusion 202.
Specifically, step S130 may include steps as following.
At step S1301, as shown in
The material of the mask layer 7 may be an insulating material, such as SiO2. The mask layer 7 may be manufactured by vapor deposition. The mask layer 7 may conformally cover the third semiconductor layer 3, but this is not particularly limited in the embodiments of the present disclosure.
At step S1302, an opening 701 is formed on the mask layer 7, where the opening 701 exposes a portion of the third semiconductor layer 3 located on the top surface of the second protrusion 202.
The opening 701 may be formed by etching. The area of the opening 701 may be smaller than the area of the top surface of the second protrusion 202, or certainly, the area of the opening 701 may be greater than or equal to the area of the top surface of the second protrusion 202. In the present disclosure, a portion of the third semiconductor layer 3 located on the top surface of the second protrusion 202 is exposed by etching, which has high efficiency and reduces the manufacturing time.
At step S1303, as shown in
Using the mask layer 7 with the opening 701 as a mask, the portion of the third semiconductor layer 3 located on the top surface of the second protrusion 202 is etched. In the embodiments of the present disclosure, the mask layer 7 may be removed, or certainly, the mask layer 7 may be retained.
According to an embodiment of the present disclosure, a semiconductor structure is provided which may be formed by the above-mentioned method for manufacturing the semiconductor structure. The semiconductor structure may include: a first semiconductor layer 1 including a first surface and a second surface which are opposite to each other, where the first surface has first protrusions 102; a second semiconductor layer 2 on the first semiconductor layer 1, where second protrusions 202 are conformally formed at a surface of the second semiconductor layer 2 away from the first semiconductor layer 1, the second protrusions 202 correspond to the first protrusions 102 respectively in position, a second recess 201 is formed between two adjacent second protrusions 202, a conductivity type of the second semiconductor layer 2 is the same as a conductivity type of the first semiconductor layer 1, and a doping concentration of the second semiconductor layer 2 is lower than a doping concentration of the first semiconductor layer 1; and a third semiconductor layer 3 on the second semiconductor layer 2, where the second protrusion is exposed by the third semiconductor layer 3.
According to the embodiment of the present disclosure, the method for manufacturing the semiconductor structure is belong to the same inventive concept as the semiconductor structure, and the descriptions of related details and beneficial effects can be referred to each other and will not be repeated here.
A conductivity type of the buffer layer 9 is the same as the conductivity type of the first semiconductor layer 1. For example, the buffer layer 9 is an N-type buffer layer. A material of the buffer layer 9 may be GaN, AlGaN or AlInGaN, or other semiconductor materials including Ga atoms and N atoms, or a combination thereof. A buffer-layer-recess 901 is formed at the surface of the buffer layer 9 away from the first semiconductor layer 1, and the buffer-layer-recess 901 corresponds to the first recess 101 in position. The buffer layer 9 may be formed by epitaxial growth, which is not limited in the embodiments of the present disclosure.
The buffer-layer-recess 901 may be conformally formed during the epitaxial growth process of the buffer layer 9.
A conductivity type of the buffer layer 9 is opposite to the conductivity type of the first semiconductor layer 1. For example, the buffer layer 9 is a P-type buffer layer, and electrons are supplemented between the first semiconductor layer 1 and the second semiconductor layer 2 to form a depletion layer. The buffer layer 9 may be an alloy layer or a superlattice structure layer, as a barrier layer for impurities and defects.
It should be pointed out that the buffer layer 9 may be a single layer structure or a laminated layer structure.
The source electrode 4 is formed on a side of the fourth semiconductor layer 8 away from the second protrusion 202. By providing the fourth semiconductor layer 8, a resistance of ohmic contact can be reduced.
The above are some embodiments of the present disclosure, and they do not limit the present disclosure in any form. Although the present disclosure has been disclosed in the preferred embodiments, they are not used to limit the present disclosure. Those skilled in the art can make some changes or modifies into an equivalent embodiment by using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. So long as the content does not depart from the technical solution of the present disclosure, any simple changes, equivalent changes or modifications made to the above embodiments according to the technical essence of the present disclosure shall all belong to the scope of the technical solution of the present disclosure.
Number | Date | Country | Kind |
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202210981261.0 | Aug 2022 | CN | national |