The disclosure relates to a semiconductor structure and a method for manufacturing the same. More particularly, the disclosure relates to a semiconductor structure comprising source/drain regions formed of an epitaxial material and a method for manufacturing the same.
Strain engineering has been used in the semiconductor devices for further improving the performance. For example, a PMOS device may have a better performance by applying a compressive strain to the channel. While for a NMOS device, a tensile strain is preferably applied to the channel. One method of applying the strain to the channel is to form a stress-applying film, such as a SiN film, over the structure. Another method is to introduce dopants into the source/drain areas. Still another method is to form epitaxial structures in the source/drain areas instead of the conventional source/drain regions.
This disclosure provides a semiconductor structure comprising epitaxial structures in the source/drain areas (i.e. source/drain regions formed of an epitaxial material) and a method for manufacturing the same. The semiconductor structure according to embodiments has improved electrical performance.
According to some embodiments, a semiconductor comprises a substrate, two source/drain regions, a gate structure and two salicide layers. The two source/drain regions are partially disposed in the substrate each with a substantially flat top surface higher than a top surface of the substrate, and the two source/drain regions are separated from each other. The two source/drain regions are formed of an epitaxial material. The gate structure is disposed on the substrate between the two source/drain regions. The two salicide layers are disposed on the substantially flat top surfaces of the two source/drain regions, respectively.
According to some embodiments, a method for manufacturing a semiconductor structure comprises the following steps. First, a preliminary structure is provided. The preliminary structure comprises a substrate and a gate structure. The substrate comprises two source/drain areas which are separated from each other. The gate structure is formed on the substrate between the two source/drain areas. Then, a disposable layer is formed on the preliminary structure. The disposable layer is thermally treated. Two sacrificial spacers are formed on two sidewalls of the gate structure. Two source/drain regions are formed partially in the substrate at the two source/drain areas, respectively. The two source/drain regions are formed of an epitaxial material. Thereafter, two salicide layers are formed on substantially flat top surfaces of the two source/drain regions, respectively, wherein the substantially flat top surfaces are higher than a top surface of the substrate.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
Various embodiments will be described more fully hereinafter with reference to accompanying drawings. For clarity, the elements in the figures may not reflect their real sizes. Further, in some figures, undiscussed components may be omitted. It is contemplated that elements and features of one embodiment may be beneficially incorporated in another embodiment without further recitation.
The two source/drain regions 104 and 105 are partially disposed in the substrate 102. The two source/drain regions 104 and 105 are separated from each other. The two source/drain regions 104 and 105 have substantially flat top surfaces 1042 and 1052, respectively. The substantially flat top surfaces 1042 and 1052 are higher than a top surface 1021 of the substrate 102. More specifically, the two source/drain regions 104 and 105 have top portions 1041 and 1051 with substantially trapezoidal cross-section, respectively, and the top portions 1041 and 1051 have the substantially flat top surfaces 1042 and 1052, respectively. The two source/drain regions 104 and 105 are formed of an epitaxial material, such as SiGe.
The gate structure 106 is disposed on the substrate 102 between the source/drain regions 104 and 105. The gate structure 106 may comprise a gate dielectric 1061 and a gate electrode 1062. The gate electrode 1062 is disposed on the gate dielectric 1061. The substantially flat top surfaces 1042 and 1052 of the source/drain regions 104 and 105 may be higher than a top surface 10611 of the gate dielectric 1061. In some embodiments, the gate electrode 1062 has a length L of 0.09 μm to 0.15 μm. The gate structure 106 may further comprise spacers 1063 and liner spacers 1064 on sidewalls of the gate electrode 1062.
The semiconductor structure further comprises two salicide layers 108 and 110. The two salicide layers 108 and 110 are disposed on the substantially flat top surfaces 1042 and 1052 of the two source/drain regions 104 and 105, respectively. The semiconductor structure may further comprise another salicide layer 112 on the gate electrode 1062.
The semiconductor structure may further comprise two contacts 114 and 116 connected to the two source/drain regions 104 and 105, respectively. The contacts 114 and 116 typically are disposed through a dielectric layer 118 of the semiconductor structure, which is disposed over the components (except the contacts 114 and 116) described above. The semiconductor structure may further comprise another contact 120 disposed in the dielectric layer 118 and connected to the gate structure 106.
The preliminary structure 202 comprises a substrate 204 comprising two source/drain areas 2041 and 2042 which are separated from each other, and a gate structure 214 formed on the substrate 204 between the two source/drain areas 2041 and 2042. In the case shown in
The preliminary structure 202 may comprise corresponding components in the NMOS area AN. More specifically, in the NMOS area AN, the preliminary structure 202 may comprise two implanted regions 216 and 218 formed in two other source/drain areas 2043 and 2044 of the substrate, respectively, a gate structure 220 formed on the substrate 204 between the two source/drain areas 2043 and 2044. The implanted regions 216 and 218 have opposite doping type to the implanted regions 206 and 208. The gate structure 220 may be substantially the same as the gate structure 214. Optionally, the preliminary structure 202 may further comprise two lightly-implanted regions (not shown) each of which is formed between the gate structure 220 and one of the implanted regions 216 and 218. Alternatively, the lightly-implanted regions may be formed in a later process.
Referring to
After the thermal treatment of the disposable layer 222, the modified disposable layer 222 is partially removed to form further components, such as two sacrificial spacers 226 on two sidewalls of the gate structure 214. Referring to
Thereafter, two source/drain regions 238 and 240 are formed partially in the substrate 204 at the two source/drain areas 2041 and 2042, respectively, wherein the two source/drain regions 238 and 240 are formed of an epitaxial material.
In the beginning, two recesses are formed at the two source/drain areas 2041 and 2042, respectively. Referring to
Then, referring to
Referring to
A comparative semiconductor structure is shown in
Referring to
Thereafter, other typical processes for the manufacturing of a semiconductor structure may be carried out. For example, as shown in
Now referring to
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.