SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND

The electronics industry is experiencing ever-increasing demand for smaller and faster electronic devices that are able to perform a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing OFF-state current, and reducing short-channel effects (SCEs). However, integration of fabrication of the multi-gate devices can be challenging.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A to 1Q illustrate diagrammatic perspective views of intermediate stages of manufacturing a semiconductor structure in accordance with some embodiments.

FIG. 2A shows a cross-sectional view of the semiconductor structure 100a of FIG. 1Q, in accordance with some embodiments.

FIGS. 2B-2M show cross-sectional representations of various stages of manufacturing the semiconductor structure after FIG. 2A, in accordance with some embodiments.

FIG. 3 shows a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

FIG. 4 shows a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

FIG. 5 shows a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

The gate all around (GAA) transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

Embodiments of semiconductor structures and methods for forming the same are provided. The semiconductor structures may include nanostructures formed over a substrate and a gate structure wraps around the nanostructures. A source/drain (S/D) structure is formed attached to the nanostructures. A front side S/D contact structure and a back side S/D contact structure are formed on opposite sides of the S/D structure. The back side S/D contact structure includes a conductive layer. The conductive layer of the back side S/D contact structure is in direct contact with a dielectric layer, and there is no glue layer or adhesion layer between the conductive layer and the dielectric layer. Since the dielectric layer is doped with germanium (Ge), the adhesion between the conductive layer and the dielectric layer is improved. Accordingly, the reliability of the semiconductor structure is improved. The source/drain (S/D) structure or region(s) may refer to a source or a drain, individually or collectively dependent upon the context

FIGS. 1A to 1Z illustrate diagrammatic perspective views of intermediate stages of manufacturing a semiconductor structure 100a in accordance with some embodiments. In addition, the figures may have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features may be added in the semiconductor structure 100a, and some of the features described below may be replaced, modified, or eliminated.

The semiconductor structure 100a may include multi-gate devices and may be included in a microprocessor, a memory, or other IC devices. For example, the semiconductor structure 100 may be a portion of an IC chip that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other applicable components, or a combination thereof.

First, as shown in FIG. 1A, a semiconductor stack, including first semiconductor material layers 106 and second semiconductor material layers 108, is formed over a substrate 102, in accordance with some embodiments. The substrate 102 may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate 102 may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are alternately stacked over the substrate 102 to form the semiconductor stack. In some embodiment, the first semiconductor material layers 106 and the second semiconductor material layers 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layers 106 are made of SiGe, and the second semiconductor material layers 108 are made of silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are shown in FIG. 1A, the semiconductor structure may include more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five of the first semiconductor material layers 106 and two to five of the second semiconductor material layers 108.

The first semiconductor material layers 106 and the second semiconductor material layers 108 may be formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

Afterwards, as shown in FIG. 1B, after the first semiconductor material layers 106 and the second semiconductor material layers 108 are formed as the semiconductor material stack over the substrate 102, the semiconductor material stack is patterned to form fin structures 104 extending in a first direction, in accordance with some embodiments.

In some embodiments, the fin structures 104 are protruding from the front side of the substrate 102. In some embodiments, the fin structures 104 include base fin structures 105 and the semiconductor material stacks, including the first semiconductor material layers 106 and the second semiconductor material layers 108, formed over the base fin structure 105.

In some embodiments, the patterning process includes forming mask structures over the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure. In some embodiments, the mask structures are a multilayer structure including a pad oxide layer and a nitride layer formed over the pad oxide layer. The pad oxide layer may be made of silicon oxide, which may be formed by thermal oxidation or CVD, and the nitride layer may be made of silicon nitride, which may be formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

Next, as shown in FIG. 1C, after the fin structures 104 are formed, an isolation structure 112 is formed to cover the lower sidewalls of the fin structures 104, in accordance with some embodiments. In some embodiments, the isolation liner (not shown) is formed on sidewalls of the fin structure 104, and it is made of a single or multiple dielectric materials. In some embodiments, the isolation liner includes an oxide layer and a nitride layer formed over the oxide layer. In some embodiments, the isolation structure 112 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), other applicable insulating materials, or a combination thereof.

The isolation structure 112 may be formed by conformally forming a liner layer covering the fin structures 104, forming an insulating material over the liner layer, and recessing the liner layer and the insulating material to form the isolation liner 110 and the isolation structure 112. The isolation structure 112 is configured to electrically isolate active regions (e.g. the fin structures 104) of the semiconductor structure and is also referred to as shallow trench isolation (STI) feature in accordance with some embodiments. In some embodiments, the isolation structure 112 is directly formed over the substrate 102 around the fin structures 104 without forming the isolation liner.

Afterwards, as shown in FIG. 1D, after the isolation structure 112 is formed, dummy gate structures 116 are formed across the fin structure 104, in accordance with some embodiments.

The dummy gate structures 116 may be used to define the source/drain regions and the channel regions of the resulting semiconductor structure 100. In some embodiments, the dummy gate structures 116 include a dummy gate dielectric layer 118 and a dummy gate electrode layer 120. In some embodiments, the dummy gate dielectric layer 118 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO₂, HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dummy gate dielectric layer 118 is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

In some embodiments, the dummy gate electrode layer 120 is made of conductive material includes polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), or a combination thereof. In some embodiments, the dummy gate electrode layer 120 is formed using CVD, PVD, or a combination thereof.

The formation of the dummy gate structures 116 may include conformally forming a dielectric material as the dummy gate dielectric layers 118. Afterwards, a conductive material may be formed over the dielectric material as the dummy gate electrode layers 120, and a hard mask layer 122 may be formed over the conductive material. Next, the dielectric material and the conductive material may be patterned through the hard mask layer 122 to form the dummy gate structures 116. In some embodiments, the hard mask layers 122 include multiple layers, such as an oxide layer 124 and a nitride layer 126. In some embodiments, the oxide layer 124 is silicon oxide, and the nitride layer 126 is silicon nitride.

Next, as shown in FIG. 1E, after the dummy gate structures 116 are formed, gate spacers 128 are formed along and covering opposite sidewalls of the dummy gate structures 116, in accordance with some embodiments. The gate spacers 128 may be configured to separate source/drain structures (formed afterwards) from the dummy gate structures 116. In some embodiments, the gate spacers 128 are made of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), and/or a combination thereof.

Next, as shown in FIG. 1F, after the gate spacers 128 are formed, source/drain (S/D) recesses 130 are formed adjacent to the gate spacers 128, in accordance with some embodiments. More specifically, the fin structures 104 not covered by the dummy gate structures 116 and the gate spacers 128 are recessed, in accordance with some embodiments. In addition, a portion of the isolation structure 112 is recessed.

In some embodiments, the fin structures 104 are recessed by performing an etching process. The etching process may be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 116 and the gate spacers 128 may be used as etching masks during the etching process.

Next, as shown in FIG. 1G, after the S/D recesses 130 are formed, the first semiconductor material layers 106 exposed by the S/D recesses 130 are laterally recessed to form notches 132, in accordance with some embodiments.

In some embodiments, an etching process is performed to laterally recess the first semiconductor material layers 106 of the fin structure 104 from the S/D recesses 130. In some embodiments, during the etching process, the first semiconductor material layers 106 have a greater etching rate (e.g. etching amount) than the second semiconductor material layers 108, thereby forming notches 132 between the adjacent second semiconductor material layers 108. In some embodiments, the etching process is an isotropic etching such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and/or a combination thereof.

Next, as shown in FIG. 1H, inner spacers 134 are formed in the notches 132 between the second semiconductor material layers 108, in accordance with some embodiments. The inner spacers 134 may be configured to separate the source/drain structures and the gate structures formed in subsequent manufacturing processes. In some embodiments, the inner spacers 134 have curved sidewalls. In some embodiments, the inner spacers 134 are made of a dielectric material, such as silicon oxide (SiO₂), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof.

Next, as shown in FIG. 1I, an epitaxial sacrificial structure 136 is formed and embedded in the fin structures 104, so they can be replaced in the formation of a back side S/D contact structure 187 (formed later, shown in FIG. 2M) in subsequent manufacturing processes. The epitaxial sacrificial structures 136 are configured to be removed and replaced by the back side S/D contact structure 187 afterwards.

In some embodiments, the epitaxial sacrificial structure 136 is mad of undoped SiGe, SiGeB, SiB, or another applicable material. In some embodiments, the epitaxial sacrificial structure 136 is formed using an epitaxial growth process, such as Molecular beam epitaxy (MBE), Metal organic CVD (MOCVD), vapor phase epitaxy (VPE), other applicable epitaxial growth process, or a combination thereof.

Next, as shown in FIG. 1J, an isolation layer 138 is formed over the epitaxial sacrificial structure 136, in accordance with some embodiments. The isolation layer 138 is configured to isolate the epitaxial sacrificial structure 136 from the S/D structures (140, as shown in FIG. 1K, formed later). The isolation layer 138 is in direct contact with the inner spacer 134. In addition, the isolation layer 138 is also formed on the gate spacer 128 and the hard mask layer 122. In some embodiments, the isolation layer 138 is formed on the top surface of the epitaxial sacrificial structure 136 and the top surface of the isolation structure 112. In some other embodiments, the isolation layer 138 has a vertical portion and horizontal portion, and the horizontal portion is thicker than the vertical portion.

In some embodiments, the isolation layer 138 is made of be SiO, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiN, SiOCN, SiCN, SiCO or another applicable material. In some embodiments, the isolation layer 138 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable processes. In some embodiments, the isolation layer 138 has a thickness in a range from about 1 nm to about 5 nm.

Afterwards, as shown in FIG. 1K, source/drain (S/D) structures 140 are formed over the isolation layer 138, in accordance with some embodiments. The isolation layer 138 is configured to reduce the leakage of the S/D structure 140. The S/D structures 140 are isolated from the epitaxial sacrificial structures 136 by the isolation layer 138. The source/drain (S/D) structures or region(s) may refer to a source or a drain, individually or collectively dependent upon the context.

In some embodiments, the S/D structures 140 are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, other applicable epitaxial growth process, or a combination thereof. In some embodiments, the S/D structures 140 are made of any applicable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the S/D structures 140 are in-situ doped during the epitaxial growth process. For example, the S/D structures 140 may be the epitaxially grown SiGe doped with boron (B). For example, the S/D structures 140 may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. In some embodiments, the source/drain structures 140 are doped in one or more implantation processes after the epitaxial growth process.

Afterwards, as shown in FIG. 1L, after the S/D structures 140 are formed, a contact etch stop layer (CESL) 142 is conformally formed to cover the source/drain structures 140 and dummy gate structures 116, and an interlayer dielectric (ILD) layer 144 is formed over the CESL 142, in accordance with some embodiments.

In some embodiments, the CESL 142 is made of a dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the CESL 142 may be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

The ILD layer 144 may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric materials. The ILD layer 144 may be formed by chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or other applicable processes.

Next, as shown in FIG. 1M, after the CESL 142 and the ILD layer 144 are deposited, a portion of the ILD layer 144 is removed by a planarization process, in accordance with some embodiments. In some embodiments, the planarization process such as CMP or an etch-back process is performed until the gate electrode layers 120 of the dummy gate structures 116 are exposed

Next, as shown in FIG. 1N, the dummy gate structures 116 and the first semiconductor material layers 106 of the fin structures 104 are removed to form gate trenches 146, in accordance with some embodiments. More specifically, the dummy gate structures 116 and the first semiconductor material layers 106 of the fin structures 104 are removed to form nanostructures 108′ with the second semiconductor material layers 108 of the fin structures 104, in accordance with some embodiments.

The removal process may include one or more etching processes. For example, when the dummy gate electrode layers 120 are polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layers 120. Afterwards, the dummy gate dielectric layers 118 may be removed using a plasma dry etching, a dry chemical etching, and/or a wet etching. The first semiconductor material layers 106 may be removed by performing a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. For example, the wet etching process uses etchants such as ammonium hydroxide (NH₄OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions.

Next, as shown in FIG. 1O, gate structures 148 are formed wrapping around the nanostructures 108′, in accordance with some embodiments. The gate structures 148 wrap around the nanostructures 108′ to form gate-all-around transistor structures, in accordance with some embodiments. In some embodiments, the gate structures 148 include conductive materials such as Ti, TiN, and/or W with dopants such as La, Zr, Hf, or the like.

In some other embodiments, a trimming process is performed before the formation of the gate structures 148, so that the nanostructures 108′ at the channel region wrapped by the gate structures 148 are narrower than the nanostructures under the gate spacers 128 and between the inner spacers 134.

In some embodiments, each of the gate structure 148 includes a gate dielectric layer 150 and a gate electrode layer 152. In some embodiments, an interfacial layer is formed before the gate dielectric layer 150 is formed, although not shown in FIG. 1O. In some embodiments, the interfacial layer is an oxide layer formed around the nanostructures 108′ and on the exposed portions of the base fin structures 105. In some embodiments, the interfacial layer is formed by performing a thermal process.

In some embodiments, the gate dielectric layer 150 is formed over the interfacial layer, so that the nanostructures 108′ are surrounded (e.g. wrapped) by the gate dielectric layer 150. In addition, the gate dielectric layer 150 also covers the sidewalls of the gate spacers 128, the inner spacers 134, and the nanostructures 108′ in accordance with some embodiments.

In some embodiments, the gate dielectric layers 150 are made of one or more layers of dielectric materials, such as HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, other applicable high-k dielectric materials, or a combination thereof. In some embodiments, the gate dielectric layers 150 are formed using CVD, ALD, other applicable methods, or a combination thereof.

In some embodiments, the gate electrode layers 152 are formed on the gate dielectric layers 150. In some embodiments, the gate electrode layers 152 are made of one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layers 152 are formed using CVD, ALD, electroplating, another applicable method, or a combination thereof. Other conductive layers, such as work function metal layers, may also be formed in the gate structures 148, although they are not shown in the figures.

Next, as shown in FIG. 1P, after the gate structures 148 are formed, an etch back process is performed to form recesses over the gate structures 148, and metal cap layers 154 and mask structures 156 are formed in the recesses, in accordance with some embodiments.

In some embodiments, an etching process is performed to form the recesses. In some embodiments, the etching process is an isotropic etching such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and/or a combination thereof. In some embodiments, the gate spacers 128 are partially removed during the etching process, so that the recesses have T shape in the cross-sectional views.

After the recesses are formed, the metal cap layers 154 are formed over the top surfaces of the gate structures 148 in accordance with some embodiments. In some embodiments, the metal cap layers 154 are made of metal such as W, Re, Ir, Co, Ni, Ru, Mo, Al, Ti, Ag, Al, other applicable metals, or multilayers thereof. In some embodiments, the metal cap layers 154 and the metal gate electrode layer 152 are made of different materials. In some embodiments, the metal cap layers 154 covers both the gate dielectric layers 150 and the gate electrode layers 152 and are in contact with the sidewalls of the gate spacers 128. In some embodiments, the top surfaces of the metal cap layers 154 are lower than the top portions of the gate spacers 128.

After the metal cap layers 154 are formed, the mask structures 156 are formed in the recesses over the metal cap layers 154 and over the gate spacers 128, in accordance with some embodiments. In some embodiments, the mask structures are bi-layered structure including a lining layer 158 and a bulk layer 160 over the lining layer 158. The mask structures 156 are configured to protect the gate spacer 128 and the gate structures 148 during the subsequent etching process for forming contact plugs.

In some embodiments, the mask structures 156 have narrower bottom portions and wider top portions. In some embodiments, the mask structures 156 have T-shapes in cross-sectional views. In some embodiments, the mask structures 156 are in direct contact with the contact etch stop layers 142.

In some embodiments, the lining layer 158 is made of dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), silicon oxide (SiO2), or a combination thereof. In some embodiments, the dielectric material for forming the lining layer 158 is conformally deposited using such as ALD, CVD (such as LPCVD, PECVD, HDP-CVD, or HARP), or the like.

In some embodiments, the bulk layer 160 is made of dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, the dielectric material for the bulk layer 160 is formed over the lining layer 158 to overfill the recesses using such as CVD (such as FCVD, LPCVD, PECVD, HDP-CVD or HARP), ALD, or the like. In some embodiments, the bulk layer 160 and the lining layer 158 are made of different materials. In some embodiments, the bulk layer 160 is made of an oxide (such as silicon oxide) and the lining layer 158 is made of a nitrogen-containing dielectric (such as silicon nitride or silicon oxynitride). Afterward, a planarization process is performed on the bulk layer 160 and the lining layer 158 until the ILD layer 144 is exposed. The planarization may be CMP, an etching back process, or a combination thereof.

After the mask structures 156 are formed, front side source/drain (S/D) contact structure 162 are formed through the ILD layer 144 and the CESL 142 over the S/D structures 140. In some embodiments, some of the front side source/drain (S/D) contact structure 162 overlap more than one of the fin structures 104. The formation of the front side S/D contact structure 162 may include patterning the ILD layer 144 and the CESL 142 to form contact openings partially exposing the S/D structures 140, forming a silicide layer (not shown), and forming a conductive material over the silicide layer. The patterning process may include forming a patterned mask layer using a photolithography process over the ILD layer 144 followed by an anisotropic etching process.

The silicide layers may be formed by forming metal layers over the top surface of the S/D structures 140 and annealing the metal layers so the metal layers react with the S/D structures 140 to form the silicide layers. The unreacted metal layers may be removed after the silicide layers are formed. The silicide layers may be made of WSi, NiSi, TiSi, TaSi, PtSi, WSi, CoSi, or the like.

After the silicide layer is formed, the conductive material may be formed in the contact openings to form the front side S/D contact structure 162. The conductive material may include ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), aluminum (Al) tungsten (W), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof.

In some embodiments, the conductive material for forming the front side S/D contact structure 162 is different from that for forming the gate structures. The conductive material may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes.

Liners and/or barrier layers (not shown) may be formed before the formation of the conductive materials of the front side S/D contact structure 162. The liners may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.

Next, as shown in FIG. 1P, after the front side S/D contact structure 162 are formed, a front end structure 164 is formed over the mask structures 156, the ILD layer 144, and the front side S/D contact structure 162, in accordance with some embodiments.

In some embodiments, the front end structure 164 includes an etch stop layer and various features (not shown), such as a multilayer interconnect structure (e.g., contacts to gate, vias, lines, inter metal dielectric layers, passivation layers, etc.), formed thereon.

Next, as shown in FIG. 1Q, after the front end structure 164 is formed, a carrier substrate (not shown) is attached to the front end structure 164, and then the substrate 102 is turned upside down, and a planarization is performed on the back side of the substrate 102, in accordance with some embodiments. More specifically, a planarization is performed on the substrate 102 until the isolation structure 112, the epitaxial sacrificial structures 136 and the CESL 142 are exposed. In some embodiments, a portion of the isolation layer 138 which is directly on the isolation structure 112 is removed.

The planarization process may be an etching process, a CMP process, a mechanical grinding process, a dry polishing process, or a combination thereof. The front end structure 164 is configured to support the semiconductor structure in subsequent manufacturing process.

It is appreciated that although the structures in FIG. 1Q is shown in upside down for better understanding the manufacturing processes, the spatial positions of the elements (e.g. top portions, bottom portions, topmost, bottommost, or the like) are described according to the original positions shown in FIGS. 1A to 1P so they can be in consistence with those described previously for clarity. For example, the front side surface of the S/D structure 140 refers to the surface that is in contact with the S/D contact structure 162, and the back side surface of the S/D structures 140 refers to the surface that is in contact with the substrate 102, since the structure shown in FIG. 1Q is upside down.

FIG. 2A shows a cross-sectional view of the semiconductor structure 100a of FIG. 1Q, in accordance with some embodiments. FIGS. 2B-2M show cross-sectional representations of various stages of manufacturing the semiconductor structure 100a after FIG. 2A, in accordance with some embodiments.

As shown in FIG. 2A, the substrate 102 is formed over the gate structure 148 and the nanostructures 108′, and the epitaxial sacrificial structures 136 is adjacent to the substrate 102. The isolation layer 138 is between the S/D structure 140 and the epitaxial sacrificial structures 136. In addition, the isolation layer 138 is in direct contact with the inner spacer 134.

Afterwards, as shown in FIG. 2B, a portion of the substrate 102 is removed to form a recess 167, in accordance with some embodiments. As a result, the gate dielectric layer 150 of the gate structure 148 and the inner spacer 134 are exposed by the recess 167. In some embodiments, the substrate 102 is removed by dry etching process. In some embodiments, the substrate 102 is made of Si, and the epitaxial sacrificial structures 136 are made of undoped SiGe. Since the epitaxial sacrificial structure 136 has a high etching selectivity with respect to the substrate 102, the substrate 102 is removed while the epitaxial sacrificial structures 136 are left.

Afterwards, as shown in FIG. 2C, after the recess 167 is formed, a liner layer 168 is formed in the recess 167 and over the epitaxial sacrificial structure 136, in accordance with some embodiments. In some embodiments, the liner layer 168 is not made of oxide. In some embodiments, the liner layer 168 is made of SiN, SiCN or another applicable material. In some embodiments, the liner layer 168 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable processes. In some embodiments, the liner layer 168 has a thickness in a range from about 1 nm to about 5 nm.

Next, as shown in FIG. 2D, and a filling layer 170 is formed in the recess 167 and over the liner layer 168, and a polishing process (e.g. CMP) is performed until the epitaxial sacrificial structures 136 are exposed, in accordance with some embodiments. The filling layer 170 is adjacent to the epitaxial sacrificial structure 136. The liner layer 168 is between the epitaxial sacrificial structure 136 and the filling layer 170.

In some embodiments, the filling layer 170 is made of SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiOCN, SiOCN, SiCN or another applicable material. In some embodiments, the filling layer 170 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable processes. In some embodiments, the filling layer 170 has a thickness in a range from about 5 nm to about 30 nm.

Afterwards, as shown in FIG. 2E, a dielectric layer 172 is formed over the liner layer 168, the filling layer 170 and the epitaxial sacrificial structures 136, in accordance with some embodiments.

In some embodiments, the dielectric layer 172 is made of SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiOCN, SiOCN, SiCN or another applicable material. In some embodiments, the dielectric layer 172 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable processes. In some embodiments, the dielectric layer 172 has a thickness in a range from about 5 nm to about 120 nm.

Afterwards, as shown in FIG. 2F, the dielectric layer 172 is patterned to form an opening 175 by using a mask layer 173 as a mask, in accordance with some embodiments. The top surface of the filling layer 170, the top surface of the liner layer 168 and the top surface of the epitaxial sacrificial structures 136 are exposed by the opening 175.

Next, as shown in FIG. 2G, a portion of the epitaxial sacrificial structures 136 is removed, in accordance with some embodiments. As a result, a trench 177 is formed. The S/D structure 140 and a portion of the inner spacer 134 is exposed by the trench 177. In addition, a portion of the liner layer 168 and a portion of the filling layer 170 are also removed. Therefore, the filling layer 170 has a step-like structure, and.

Next, as shown in FIG. 2H, a liner layer 178 is formed on a sidewall of the trench 177, and a conductive material 180 is formed in the trench 177 and on the liner layer 178, in accordance with some embodiments.

More specifically, the material of liner layer 178 is conformally formed in the trench 177, in the opening 175, on the liner layer 168, on the filling layer 170, and on the dielectric layer 172 and on the S/D structure 140. Next, a portion of the material of the liner layer 178 is removed by a dry etching process to form the liner layer 178 and to expose the S/D structure 140. The liner layer 178 is configured to increase the isolation between the conductive material 186 (formed later) and the gate structure 148. The liner layer 178 is in direct contact with the inner spacer 134, the S/D structure 140, and the liner layer 168.

In some embodiments, the liner layer 178 and the liner layer 168 are made of different materials. In some embodiments, the liner layer 178 is made of SiO, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, SiN, SiOCN, SiCN or another applicable material. In some embodiments, the liner layer 178 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable processes. In some embodiments, the liner layer 178 has a thickness in a range from about 1 nm to about 5 nm.

It should be noted that since the filling layer 170 has a high etching selectivity with respect to the epitaxial sacrificial structures 136, the epitaxial sacrificial structures 136 is removed while the filling layer 170 is not removed or removed slightly. The filling layer 170 has the self-aligned function, and it can called as a self-aligned filling layer 170.

In some embodiments, the conductive material 180 is made of W, Mo, Ru or another applicable material. In some embodiments, the conductive material 180 is formed by a deposition process using a precursor, such as Cl-based compound. In some embodiments, the precursor includes WCl₅, WCl₆, MoCl₅, or another applicable material.

Afterwards, a portion of the conductive material 180 is annealed to form a silicide layer 182 on the exposed S/D structure 140 by an annealing process. The silicide layer 182 is in direct contact with the S/D structure 140 and the liner layer 178. The silicide layer 182 is formed by annealing the conductive material 180 so the metal layers react with the S/D structures 140 to form the silicide layers. The silicide layer 182 may be made of TiSi, MoSi, NiSi, CoSi, WSi, RuSi, TaSi, PtSi, WSi, or the like. In some embodiments, the silicide layer 182 has a thickness in a range from about 2 nm to about 6 nm.

Next, as shown in FIG. 2I, an oxygen treatment process 10 is performed on the conductive material 180 after the annealing process to form an oxidized conductive material 180′, in accordance with some embodiments. The conductive material 180 is oxidized by the oxygen treatment process 10.

In some embodiments, after the oxygen treatment process 10, the conductive material 180 become the oxidized conductive material 180′. In some embodiments, the oxidized conductive material 180′ is an oxygen-containing compound or is made of oxide. In some embodiments, the oxidized conductive material 180′ is made of TiSiON.

In some embodiments, the oxygen treatment process 10 is performed under a temperature in a range from about 160 to 250 degrees Celsius (° C.). In some embodiments, the oxygen treatment process 10 is performed at flow rate in a rage from about 2000 sccm to about 6000 sccm oxygen (02) gas.

Next, as shown in FIG. 2J, the oxidized conductive material 180′ is removed to expose the sidewall of the dielectric layer 172, in accordance with some embodiments. The oxidized conductive material 180′ is removed by an etching process while the silicide layer 182 is remaining on the S/D structure 140.

In some embodiments, the etching process is performed by using gas including WCl₅, WCl₆, MoCl₅, or another applicable material. In some embodiments, the etching process is performed without adding bias voltage (plasma bias). It should be noted that the oxidized conductive material 180′ has a higher etching removal rate with respect to the silicide layer 182, and therefore the silicide layer 182 is remaining on the S/D structure 140 when the oxidized conductive material 180′ is removed. When the oxidized conductive material 180′ is removed, the liner layer 178, the liner layer 168, and the filling layer 170 are exposed, and there is no conductive layer formed on the sidewall of the dielectric layer 172. In some other embodiments, a portion of the silicide layer 182 is slightly removed while the oxidized conductive material 180′ is etched.

Next, as shown in FIG. 2K, a conductive layer 186 is formed in the opening 175 and the trench 177 and on the sidewall of the dielectric layer 172, in accordance with some embodiments.

In some embodiments, the conductive material 186 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni or another applicable material. The conductive layer 186 is formed by a bottom up deposition process, which is formed form bottom to top. The silicide layer 182 located at bottom to help the formation of the conductive material 186. Since no conductive material is formed on sidewalls of the dielectric layer 172, the conductive layer 186 is formed from the bottom (by the silicide layer 182).

In some embodiments, the conductive material 186 is formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), or another applicable processes. When the conductive material 186 is formed by a bottom up deposition process, such as chemical vapor deposition (CVD) process, there is no glue layer before forming the conductive material 186. A glue layer has a higher resistance than that of the conductive material 186. When the conductive material 186 is in direct contact with the dielectric layer 172 without forming the glue layer, the resistance of back side S/D contact structure 187 is decreased. Therefore, the reliability of the semiconductor structure 100a is improved.

Afterwards, as shown in FIG. 2L, an implantation process 20 is performed on the conductive layer 186, in accordance with some embodiments. The adhesion between the conductive layer 186 and the dielectric layer 172 is improved by the implantation process 20. The implantation process 20 includes using a germanium (Ge)-containing compound. In addition, the implantation process 20 further includes using a carbon (C)-containing compound or a fluorine (F)-containing compound.

In some embodiments, after the implantation process 20, the dielectric layer 172 is doped with germanium (Ge). In some embodiments, after the implantation process 20, the conductive layer 186 is doped with germanium (Ge). Furthermore, the liner layer 178, the liner layer 168, and the filling layer 170 are also doped with germanium (Ge). The epitaxial sacrificial structure 136 and the isolation layer 138 are also doped with germanium (Ge). In some embodiments, when the epitaxial sacrificial structure 136 is made of SiGe, the germanium (Ge) concentration of the epitaxial sacrificial structure 136 is increased after the implantation process 20.

It should be noted that the adhesion between the conductive layer 186 and the dielectric layer 172 is improved since the dielectric layer 172 is doped with germanium (Ge). The conductive layer 186 is in direct contact with the dielectric layer 172 which is doped with germanium (Ge), and there is no glue layer or adhesion layer between the conductive layer 186 and the dielectric layer 172.

In some other embodiments, in addition to germanium (Ge), the dielectric layer 172 is further doped with carbon (C) or fluorine (F). In some other embodiments, in addition to germanium (Ge), the conductive layer 186 is further doped with carbon (C) or fluorine (F). The carbon (C) or fluorine (F) can reduce the K value (dielectric constant) of the dielectric layer 172. Therefore, the unwanted coupling capacitor of the semiconductor structure 100a can be reduced. In some embodiments, the epitaxial sacrificial structure 136 and the isolation layer 138 are also doped with carbon (C) or fluorine (F). The liner layer 178, the liner layer 168 and the filling layer 170 are also doped with carbon (C) or fluorine (F).

In some embodiments, the implantation process 20 is performed by using a Ge-containing compound. In some embodiments, the implantation process 20 is performed by using a Ge-containing compound and a carbon (C)-containing compound. In some embodiments, the implantation process 20 is performed by using a Ge-containing compound and a fluorine (F)-containing compound. In some embodiments, the implantation process 20 is performed at an energy in a range from about 30 keV to about 50 keV. In some embodiments, the dosage of the Ge-containing compound is from about 1E13 (cm-3) to about 1E17 (cm-3). In some embodiments, the dosage of the carbon (C)-containing compound or fluorine (F)-containing compound is from about 1E13 (cm-3) to about 1E17 (cm-3). In some embodiments, the title angel of the implantation process 20 is in a range from about 20 degree to about 50 degree.

Next, as shown in in FIG. 2M, a polishing process (e.g. CMP) is performed on the conductive layer 186 until the dielectric layer 172 is exposed, in accordance with some embodiments. More specifically, the conductive layer 186 is formed on the S/D structure 140.

A back-side S/D contact structure 187 is constructed by the conductive layer 186, the liner layer 178 and the silicide layer 182. Note that the front side source/drain (S/D) contact structure 162 and the back-side S/D contact structure 187 are respectively formed on opposite sides of the S/D structure 140. The back-side S/D contact structure 187 is electrically connected to the front side S/D contact structure 162 by the S/D structure 140. The epitaxial sacrificial structure 136 is adjacent to the back-side S/D contact structure 187, and the isolation layer 138 is between the S/D structure 140 and the epitaxial sacrificial structure 136.

The liner layer 178 is adjacent to the liner layer 168, and the top surface of the liner layer 168 is higher than the top surface of the liner layer 178. The liner layer 178 doped with germanium (Ge) is between the inner spacer 134 and the conductive layer 186.

It should be noted that the portion of filling layer 170 is removed when forming the trench 177 (shown in FIG. 2G). Therefore, the filling layer 170 has a step-liked portion. In some embodiments, the filling layer 170 has a loss in a rage from about 1 to about 20 nm along a vertical direction.

A portion of the conductive layer 186 of the back-side S/D contact structure 187 overlaps or covers the filling layer 170. In addition, a portion of the conductive layer 186 covers the top surface of the liner layer 168 and the top surface of the liner layer 178.

The liner layer 178 is between the liner layer 168 and the conductive layer 186 of the back-side S/D contact structure 187. In some embodiments, the topmost surface of the liner layer 178 is lower than the topmost surface of the epitaxial sacrificial structure 136. In some embodiments, the topmost surface of the liner layer 168 is higher than the topmost surface of the liner layer 178 and lower than the topmost surface of the dielectric layer 172. The liner layer 178 is between the conductive layer 186 and the nanostructures 108. In some embodiments, the liner layer 178 has a sloped top surface. In some embodiments, the liner layer 178 has a tapered width from bottom to top.

The conductive layer 186 of the back-side S/D contact structure 187 has a T-shaped structure, and has a top portion and a bottom portion. The width of the top portion is greater than the width of the bottom portion. The sidewall of the top portion of the conductive layer 186 of the back-side S/D contact structure 187 is in direct contact with the dielectric layer 172, and there is no glue layer or adhesion layer between the dielectric layer 172 and the top portion of the conductive layer 186 of the back-side S/D contact structure 187. The bottom portion of the conductive layer 186 of the back-side S/D contact structure 187 is in direct contact with the liner layer 178. In addition, the top portion of the conductive layer 186 of the back-side S/D contact structure 187 is in direct contact with the filling layer 170 and the liner layer 168.

The top portion of the conductive layer 186 of the back-side S/D contact structure 187 has a first height H₁, the bottom portion of the conductive layer 186 of the back-side S/D contact structure 187 has a second height H₂. The conductive layer 186 of the back-side S/D contact structure 187 has a third height H₃. In some embodiments, the first height H₁is in a range from about 10 nm to about 30 nm. In some embodiments, the second height H₂is in a range from about 10 nm to about 30 nm. In some embodiments, the third height H₃is in a range from about 20 nm to about 60 nm.

FIG. 3 shows a cross-sectional view of a semiconductor device structure 100b, in accordance with some embodiments. The semiconductor device structure 100b of FIG. 3 includes elements that are similar to, or the same as, elements of the semiconductor device structure 100a of FIG. 2M, the difference between FIG. 3 and FIG. 2M is that, no liner layer is between the silicide layer 182 and the inner spacer 134.

FIG. 4 shows a cross-sectional view of a semiconductor device structure 100c, in accordance with some embodiments. The semiconductor device structure 100c of FIG. 4 includes elements that are similar to, or the same as, elements of the semiconductor device structure 100a of FIG. 2M, the difference between FIG. 4 and FIG. 2M is that, no liner layer is between the epitaxial sacrificial structure 136 and the filling layer 170.

FIG. 5 shows a cross-sectional view of a semiconductor device structure 100d, in accordance with some embodiments. The semiconductor device structure 100d of FIG. 5 includes elements that are similar to, or the same as, elements of the semiconductor device structure 100a of FIG. 2M, the difference between FIG. 5 and FIG. 2M is that there is no liner layer between the silicide layer 182 and the inner spacer 134, and there is no liner layer between the epitaxial sacrificial structure 136 and the filling layer 170.

In addition, it should be noted that same elements in FIGS. 1A to 1Q and FIGS. 2A to 2M may be designated by the same numerals and may include materials that are the same or similar and may be formed by processes that are the same or similar; therefore such redundant details are omitted in the interests of brevity. In addition, although FIGS. 1A to 1Q and FIGS. 2A to 2M are described in relation to the method, it will be appreciated that the structures disclosed in FIGS. 1A to 1Q and FIGS. 2A to 2M are not limited to the method but may stand alone as structures independent of the method. Similarly, the methods shown in FIGS. 1A to 1Z and FIGS. 2A to 2M are not limited to the disclosed structures but may stand alone independent of the structures. Furthermore, the nanostructures described above may include nanowires, nanosheets, or other applicable nanostructures in accordance with some embodiments.

Also, while the disclosed methods are illustrated and described below as a series of acts or events, it should be appreciated that the illustrated ordering of such acts or events may be altered in some other embodiments. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described above. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description above. Further, one or more of the acts depicted above may be carried out in one or more separate acts and/or phases.

Furthermore, the terms “approximately,” “substantially,” “substantial” and “about” describe above account for small variations and may be varied in different technologies and be in the deviation range understood by the skilled in the art. For example, when used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.

Embodiments for forming semiconductor structures may be provided. The semiconductor structure may include nanostructures and a gate structure wrapping around the first nanostructures. An S/D structure is between the first nanostructures and the second nanostructures. A front side S/D contact structure and a back side S/D contact structure are on opposite sides of the S/D structure. The back side S/D contact structure includes a conductive layer. The conductive layer of the back side S/D contact structure is in direct contact with a dielectric layer, and there is no glue layer or adhesion layer between the conductive layer and the dielectric layer. Since the dielectric layer is doped with germanium (Ge), the adhesion between the conductive layer and the dielectric layer is improved. Therefore, the reliability and the performance of the semiconductor structure are improved.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures surrounded by a gate structure, and a source/drain (S/D) structure adjacent to the gate structure. The semiconductor structure includes a first S/D contact structure formed over a first side of the S/D structure, and a second S/D contact structure formed over the second side of the S/D structure. The second S/D contact structure includes a conductive layer. The semiconductor structure includes a dielectric layer adjacent to the second contact structure, and the dielectric layer is doped with germanium (Ge), and the dielectric layer is in direct contact with the conductive layer.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures surrounded by a gate structure, and an inner spacer adjacent to the nanostructures. The semiconductor structure also includes a source/drain (S/D) structure adjacent to the gate structure, and a first S/D contact structure formed over a first side of the first S/D structure. The semiconductor structure also includes a second S/D contact structure formed over the second side of the S/D structure, and the second S/D contact structure includes a conductive layer and a first liner layer. The first liner layer is doped germanium (Ge), and the liner layer is between the inner spacer and the conductive layer.

In some embodiments, a method for manufacturing a semiconductor structure is provided. The method includes forming a first fin structure protruding from a front side of a substrate, and the first fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming an epitaxial sacrificial structure over the first fin structure, and forming an isolation layer over the epitaxial structure. The method further includes forming an S/D structure over the isolation layer, and forming a first S/D contact structure over a first side of the S/D structure. The method includes forming a dielectric layer over the second side of the S/D structure, and removing the epitaxial sacrificial structure from the second side of the S/D structure to form a trench exposing the S/D structure. The method includes forming a first conductive material in the trench and over the dielectric layer, and performing an implantation process on the first conductive material and the dielectric layer. The first dielectric layer is doped with germanium (Ge), and the dielectric layer is in direct contact with the first conductive material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

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