BACKGROUND
Integrated circuits (ICs) have become increasingly important. Applications using ICs are used by millions of people. These applications include cell phones, smartphones, tablets, laptops, notebook computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly include powerful and efficient on-board data storage and logic circuitry for signal control and processing.
The recent trend in miniaturizing ICs has resulted in smaller devices which consume less power, yet provide more functionality at higher speeds than before. The miniaturization process has also resulted in various developments in IC designs and/or manufacturing processes to ensure the desired production yield and the intended performance.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 is a simplified diagram of a hybrid cell array of an IC, in accordance with some embodiments of the disclosure.
FIG. 2 is a simplified diagram of a regular cell array of an IC, in accordance with some embodiments of the disclosure.
FIG. 3 shows a perspective view of an exemplary GAA transistor, in accordance with some embodiments of the disclosure.
FIG. 4A illustrates the adjacent logic cells in the regular cell array of FIG. 2, in accordance with some embodiments of the disclosure.
FIG. 4B illustrates the adjacent logic cells in the regular cell array of FIG. 2, in accordance with some embodiments of the disclosure.
FIG. 5A illustrates a hybrid unit cell in the hybrid cell array of FIG. 1, in accordance with some embodiments of the disclosure.
FIG. 5B illustrates a hybrid unit cell in the hybrid cell array of FIG. 1, in accordance with some embodiments of the disclosure.
FIG. 5C illustrates a hybrid unit cell in the hybrid cell array of FIG. 1, in accordance with some embodiments of the disclosure.
FIG. 6A illustrates the hybrid unit cells in the hybrid cell array of FIG. 1, in accordance with some embodiments of the disclosure.
FIG. 6B illustrates the hybrid unit cells in the hybrid cell array of FIG. 1, in accordance with some embodiments of the disclosure.
FIG. 6C illustrates the hybrid unit cells in the hybrid cell array of FIG. 1, in accordance with some embodiments of the disclosure.
FIG. 7A is a simplified diagram of a hybrid cell array of an IC, in accordance with some embodiments of the disclosure.
FIG. 7B is a simplified diagram of a hybrid cell array of an IC, in accordance with some embodiments of the disclosure.
FIG. 8A is a simplified diagram of a hybrid cell array of an IC, in accordance with some embodiments of the disclosure.
FIG. 8B is a simplified diagram of a hybrid cell array of an IC, in accordance with some embodiments of the disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Various semiconductor structures of integrated circuits (ICs) are provided in accordance with various exemplary embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
The disclosure is generally related to semiconductor devices, and more particularly to circuit cells having three-dimensional gate-all-around (GAA) transistors, in an integrated circuit (IC) structure. Generally, a GAA transistor may include a plurality of vertically stacked sheets (e.g., nanosheets), wires (e.g., nanowires), or rods (e.g., nanorods) in a channel region of the transistor, thereby allowing better gate control, lowered leakage current, and improved scaling capability for various IC applications.
The nanostructure transistor (e.g. nanosheet transistor, nanowire transistor, multi-bridge channel, nano-ribbon FET, gate all around (GAA) transistor structures) described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
FIG. 1 is a simplified diagram of a hybrid cell array 100 of an IC, in accordance with some embodiments of the disclosure. The hybrid cell array 100 includes multiple hybrid unit cells 15, and each hybrid cell includes a first sub-cell 10 and a second sub-cell 20. In some embodiments, the hybrid unit cells 15 are the standard cells (e.g., INV (inverter), AND, OR, NAND, NOR, Flip-Flop, SCAN, etc.), a combination thereof or specific functional cells. Furthermore, the logic functions of the first sub-cells 10 and the second sub-cells 20 may be the same or different. Furthermore, each of the first sub-cells 10 and the second sub-cells 20 includes multiple transistors. In some embodiments, the first sub-cells 10 and the second sub-cells 20 corresponding to the same function or operation may have the same circuit configuration with different semiconductor structures and/or different layouts.
In FIG. 1, the first sub-cells 10 have the same cell height HT along the Y-direction in the layout, and the second sub-cells 20 have the same cell height HS along the Y-direction in the layout. A cell height of the hybrid unit cell 15 is equal to a sum of the cell heights HT and HS. The cell height HT of the first sub-cells 10 is higher than the cell height HS of the second sub-cells 20, i.e., HS<HT. In each hybrid unit cell 15, the first sub-cells 10 and the second sub-cells 20 have the same cell widths along the X-direction in the layout. Furthermore, the hybrid unit cells 15 in the hybrid cell array 100 may have the same or different cell widths along the X-direction in the layout. It should be noted that the number and the configuration of the first sub-cells 10 and the second sub-cells 20 are used as an example, and not to limit the disclosure.
In FIG. 1, the sub-rows corresponding to the first sub-cells 10 and the sub-rows corresponding to the second sub-cells 20 are staggered in the hybrid cell array 100. It should be noted that the first sub-cell 10 and the second sub-cell 20 are not arranged in the same sub-row.
In some embodiments, the transistors in the first sub-cells 10 and the second sub-cells 20 are selected from a group consisting of vertical gate all around (GAA), horizontal GAA, nano wire, nano sheet, or a combination thereof. In some embodiments, the first sub-cells 10 (or the second sub-cells 20) in the same sub-row are electrically isolated from each other by the isolation region, e.g., the shallow trench isolation (STI). In some embodiments, the first sub-cells 10 (or the second sub-cells 20) in the same sub-row are electrically isolated by the transistors.
FIG. 2 is a simplified diagram of a regular cell array 200 of an IC, in accordance with some embodiments of the disclosure. The regular cell array 200 includes multiple logic cells 30. In some embodiments, the logic cells 30 are the standard cells (e.g., INV (inverter), AND, OR, NAND, NOR, Flip-Flop, SCAN, etc.), a combination thereof or specific functional cells. Furthermore, the logic functions of the logic cells 30 may be the same or different. Each logic cell 30 includes multiple transistors. In some embodiments, the logic cells 30 corresponding to the same function or operation may have the same circuit configuration with different semiconductor structures and/or different layouts.
In FIG. 2, the regular cell array 100 has an array height HA along the Y-direction in the layout, and the logic cells 30 have the same cell height HH (e.g., along the Y-direction) in the layout. Furthermore, the logic cells 30 may have the same or different cell widths (e.g., along the X-direction) in the layout. It should be noted that the number and the configuration of the logic cells 30 are used as an example, and not to limit the disclosure.
In some embodiments, the transistors in the logic cells 30 are selected from a group consisting of vertical gate all around (GAA), horizontal GAA, nano wire, nano sheet, or a combination thereof. In some embodiments, the logic cells 30 in the same row are electrically isolated from each other by the isolation region, e.g., the shallow trench isolation (STI). In some embodiments, the logic cells 30 in the same row are electrically isolated by the transistors.
In some embodiments, the regular cell array 200 of FIG. 2 and the hybrid cell array 100 of FIG. 1 are implemented in the same IC. Furthermore, the cell height HT of the first sub-cells 10 is higher than the cell height HH of the logic cells 30, and the cell height HH of the logic cells 30 is higher than the cell height HS of the second sub-cells 20, i.e., HS<HH<HT. In some embodiments, the regular cell array 200 of FIG. 2 and the hybrid cell array 100 of FIG. 1 have the same array height HA along the Y-direction in the layout. In some embodiments, the sum of the cell height HT of the first sub-cell 10 and the cell height HS of the second sub-cell 20 is equal to twice the cell height HH of the logic cell 30 (i.e., HT+HS=2×HH), and the number of rows in the hybrid cell array 100 of FIG. 1 is equal to the number of rows in the regular cell array 200 of FIG. 2.
FIG. 3 shows a perspective view of an exemplary GAA transistor, in accordance with some embodiments of the disclosure. The GAA transistor includes a substrate 110. The substrate 110 may contains a semiconductor material, such as bulk silicon (Si). In some other embodiments, the substrate 110 may include other semiconductors such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 110 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GOI) structure. In some embodiments, after the resultant GAA transistor is formed, the substrate 110 may be removed by a suitable process (e.g., a chemical mechanical polishing (CMP) process) for forming back-side interconnections.
A well region 120 is formed over the substrate 110. In some embodiments, the well region 120 is a P-type well region for a P-type transistor, and the material of the P-type well region includes Si with Boron (B) doping. In some embodiments, the well region 110 is an N-type well region for an N-type transistor, and the material of the N-type well region includes Si with Phosphorus (P) doping. In some embodiments, the well region 120 can be omitted.
The GAA transistor also includes one or more nanostructures 150 (dash lines) extending in the X-direction and vertically arranged (or stacked) in a Z-direction. The nanostructures 150 form the active regions (or oxide definition (OD) region) over the well region 120. More specifically, the nanostructures 150 are spaced from each other in the Z-direction. In some embodiments, the nanostructures 150 may also be referred to as channels, channel layers, nanosheets, or nanowires. The nanostructures 150 may include a semiconductor material, such as silicon, germanium, silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, silicon germanium (SiGe), SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. In some embodiments, the nanostructures 150 include silicon for N-type GAA transistors. In other embodiments, the nanostructures 150 include silicon germanium for P-type GAA transistors. In some embodiments, the nanostructures 150 are all made of silicon, and the type of GAA transistors depend on work function metal layer wrapping around the nanostructures 150.
The GAA transistor further includes a gate structure 145 extending in the Y-direction and includes a gate electrode 140 and a gate dielectric layer 142. The gate dielectric layer 142 wraps around the nanostructures 150 and the gate electrode 140 wraps around the gate dielectric layer 142 (not shown). The gate electrode 140 may include polysilicon or work function metal. The work function metal includes TiN, TaN, TiAl, TiAlN, TaAl, TaAlN, TaAlC, TaCN, WNC, Co, Ni, Pt, W, combinations thereof, or other suitable material.
In some embodiments, the gate electrode 140 may include a capping layer, a barrier layer, an n-type work function metal layer, a p-type work function metal layer, and a fill material (not shown). In some embodiments, the P-type transistors and the N-type transistors are formed by the same work function material. In some embodiments, the P-type transistors and the N-type transistors are made of different work function materials.
The gate dielectric layer 142 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, dielectric material(s) with high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material.
The gate spacers 144 are on sidewalls of the gate dielectric layer 142 and over the nanostructures 150 (not shown). The gate spacers 144 may include multiple dielectric materials and be selected from a group consisting of silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon doped oxide, nitrogen doped oxide, porous oxide, air gap, or a combination thereof. In some embodiments, the gate spacers 144 may include a single layer or a multi-layer structure.
The gate top dielectric layer 146 is over the gate dielectric layer 142, the gate electrode 140, and the nanostructures 150. The gate top dielectric layer 146 is used for contact etch protection layer. The material of gate top dielectric layer 146 is selected from a group consisting of oxide, SiOC, SiON, SiOCN, nitride base dielectric, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), Y oxide (Y2O3), combinations thereof, or other suitable material.
The GAA transistor further includes epitaxially-grown materials 160. As shown in FIG. 3, two epitaxially-grown materials 160 are on opposite sides of the gate structure 145. The epitaxially-grown materials 160 serve as the source/drain features of the GAA transistor. Therefore, the epitaxially-grown materials 160 may also be referred to as source/drain, source/drain features, or source/drain nodes. Source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. In some embodiments, for an N-type GAA transistor, the epitaxially-grown materials 160 may include SiP, SiC, SiPC, SiAs, Si, or a combination thereof. In some embodiments, for a P-type GAA transistor, the epitaxially-grown materials 160 may include SiGe, SiGeC, Ge, Si, a boron-doped SiGe, boron and carbon doped SiGe, or a combination thereof.
The nanostructures 150 (dash lines) extends in the X-direction to connect two epitaxially-grown materials 160. Such the nanostructures 150 and the epitaxially-grown materials 160 connected continuously with each other may be collectively referred to as an active area.
Isolation feature 130 is over the substrate 110 and under the gate dielectric layer 142, the gate electrode 140, and the gate spacers 144. The isolation feature 130 is used for isolating the GAA transistor from other devices. In some embodiments, the isolation feature 130 may include different structures, such as shallow trench isolation (STI) structure, deep trench isolation (DTI) structure. Therefore, the isolation feature 130 is also referred as to as a STI feature or DTI feature.
FIG. 4A illustrates the adjacent logic cells 30 in the regular cell array 200 of FIG. 2, in accordance with some embodiments of the disclosure. In FIG. 4A, the logic cells 30_1a and 30_2a are formed in the adjacent rows of the regular cell array 200. For example, the logic cell 30_1a is arranged in the upper row of the regular cell array 200, and the logic cell 30_2a is arranged in the lower row of the regular cell array 200. Furthermore, the outer boundary of each of the logic cells 30_1a and 30_2a is example, and is not intended to limit the disclosure. As described above, the logic cells 30_1a and 30_2a have the same cell height HH in the Y-direction.
In the logic cell 30_1a, one or more P-type GAA nanosheet transistors (e.g., GAA transistor of FIG. 3) are formed over the P-type well region 120P_1 (or a P-type device region), and one or more N-type GAA nanosheet transistors (e.g., GAA transistor of FIG. 3) are formed over the N-type well region 120N_1 (or an N-type device region). In order to simplify the description, only the nanosheet structures 150 of the P-type and N-type GAA nanosheet transistors are shown in the logic cell 30. In the logic cell 30_2a, one or more P-type GAA nanosheet transistors are formed over the P-type well region 120P_2 (or a P-type device region), and one or more N-type GAA nanosheet transistors are formed over the N-type well region 120N_2 (or an N-type device region). The N-type well region 120N_1 is adjacent to and in contact with the N-type well region 120N_2, i.e., the N-type well regions 120N_1 and 120N_2 are merged into single N-type well region. The P-type well region 120P_1 is separated from the P-type well region 120P_2 by the N-type well regions 120N_1 and 120N_2. In FIG. 4A, the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors of the logic cells 30 in each row of the regular cell array 200 have the nanosheet structures 150 with the same nanosheet width W1. Therefore, the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have symmetry nanosheet structures in the logic cells 30_1a and 30_2b.
FIG. 4B illustrates the adjacent logic cells 30 in the regular cell array 200 of FIG. 2, in accordance with some embodiments of the disclosure. In FIG. 4B, the logic cells 30_1b and 30_2b are formed in the adjacent rows of the regular cell array 200. The configuration of the logic cells 30_1b and 30_2b in FIG. 4B is similar to the configuration of the logic cells 30_1a and 30_2a in FIG. 4A, and the difference between the logic cells 30_1b and 30_2b in FIG. 4B and the logic cells 30_1a and 30_2a in FIG. 4A is that the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have different nanosheet widths in the logic cells 30_1b and 30_2b. Therefore, the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have asymmetry nanosheet structures in the logic cells 30_1b and 30_2b.
In FIG. 4B, the P-type GAA nanosheet transistors of the logic cells 30 have the same nanosheet width and the N-type GAA nanosheet transistors of the logic cells 30 have the same nanosheet width in the same row of the regular cell array 200. The nanosheet width W1_a of the P-type GAA nanosheet transistors is greater than the nanosheet width W1_b of the N-type GAA nanosheet transistors in the logic cell 30_1b (i.e., W1_a>W1_b), and the nanosheet width W1_d of the P-type GAA nanosheet transistors is greater than the nanosheet width W1_c of the N-type GAA nanosheet transistors in the logic cell 30_2b (i.e., W1_d>W1_c). In some embodiments, the nanosheet width W1_b is less than the nanosheet width W1_c, the nanosheet width W1_c is less than the nanosheet width W1_a, and the nanosheet width W1_a is less than the nanosheet width W1_d, i.e., W1_b<W1_c<W1_a<W1_d.
FIG. 5A illustrates a hybrid unit cell 15_a in the hybrid cell array 100 of FIG. 1, in accordance with some embodiments of the disclosure. In FIG. 5A, the hybrid unit cell 15_a includes the first sub-cell 10_a and the second sub-cell 20_a. Furthermore, the outer boundary of each of the sub-cells 10_a and 20_a is example, and is not intended to limit the disclosure. As described above, the cell height HT of the first sub-cell 10_a is greater than the cell height HS of the second sub-cell 20_a in the Y-direction.
In the first sub-cell 10_a, one or more P-type GAA nanosheet transistors (e.g., GAA transistor of FIG. 3) are formed over the P-type well region 120P_3 (or a P-type device region), and one or more N-type GAA nanosheet transistors (e.g., GAA transistor of FIG. 3) are formed over the N-type well region 120N_3 (or an N-type device region). In the second sub-cell 20_a, one or more P-type GAA nanosheet transistors (e.g., GAA transistor of FIG. 3) are formed over the P-type well region 120P_4 (or a P-type device region), and one or more N-type GAA nanosheet transistors (e.g., GAA transistor of FIG. 3) are formed over the N-type well region 120N_4 (or an N-type device region). In order to simplify the description, only the nanosheet structures 150 of the P-type and N-type GAA nanosheet transistors are shown in the sub-cells 10 and 20. The N-type well region 120N_3 is adjacent to and in contact with the N-type well region 120N_4, i.e., the N-type well regions 120N_3 and 120N_4 are merged into single N-type well region. The P-type well region 120P_3 is separated from the P-type well region 120P_4 by the N-type well regions 120N_3 and 120N_4.
In FIG. 5A, the P-type GAA nanosheet transistors of the same type of sub-cells (not shown) have the same nanosheet width and the N-type GAA nanosheet transistors of the same type of sub-cells (not shown) have the same nanosheet width in the same row of the hybrid cell array 100. The P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors in the first sub-cell 10_a have the nanosheet structures 150 with the same nanosheet width W2, and the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors in the second sub-cell 20_a have the nanosheet structures 150 with the same nanosheet width W3. Therefore, the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have symmetry nanosheet structures in the first sub-cell 10_a, and the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have symmetry nanosheet structures in the second sub-cell 20_a. It should be noted that the nanosheet width W2 is greater than the nanosheet width W3, i.e., W2>W3. Therefore, the first sub-cell 10_a is used for higher operation speed and the second sub-cell 20_a is used for lower power.
FIG. 5B illustrates a hybrid unit cell 15_b in the hybrid cell array 100 of FIG. 1, in accordance with some embodiments of the disclosure. In FIG. 5B, the hybrid unit cell 15_a includes the first sub-cell 10_b and the second sub-cell 20_b. The configuration of the hybrid unit cell 15_b in FIG. 5B is similar to the configuration of the hybrid unit cell 15_a in FIG. 5A, and the difference between the hybrid unit cell 15_b of FIG. 5B and the hybrid unit cell 15_a of FIG. 5A is that the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have different nanosheet widths in the first sub-cell 10_b and the second sub-cell 20_b of the hybrid unit cell 15_b. Therefore, the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have asymmetry nanosheet structures in the first sub-cell 10_b and the second sub-cell 20_b. Furthermore, the different nanosheet widths allows further speed and power partitioning within each of the sub-cells 10 and 20.
In FIG. 5B, the P-type GAA nanosheet transistors of the same type of sub-cells (not shown) have the same nanosheet width and the N-type GAA nanosheet transistors of the same type of sub-cells (not shown) have the same nanosheet width in the same row of the hybrid cell array 100. In the first sub-cell 10_b, the nanosheet width W2_a of the P-type GAA nanosheet transistors is greater than the nanosheet width W2_b of the N-type GAA nanosheet transistors (i.e., W2_a>W2_b). In the second sub-cell 20_b, the nanosheet width W3_a of the P-type GAA nanosheet transistors is greater than the nanosheet width W3_b of the N-type GAA nanosheet transistors (i.e., W3_a>W3_b). In some embodiments, the nanosheet width W3_a is less than the nanosheet width W2_b, i.e., W3_a<W2_b. Therefore, all of the nanosheet widths (e.g., W2_a and W2_b) of the first sub-cell 10_b are greater than all of the nanosheet widths (e.g., W3_a and W3_b) of the second sub-cell 20_b.
FIG. 5C illustrates a hybrid unit cell 15_c in the hybrid cell array 100 of FIG. 1, in accordance with some embodiments of the disclosure. In FIG. 5C, the hybrid unit cell 15_c includes the first sub-cell 10_c and the second sub-cell 20_c. The configuration of the hybrid unit cell 15_c in FIG. 5C is similar to the configuration of the hybrid unit cell 15_a in FIG. 5A, and the difference between the hybrid unit cell 15_c of FIG. 5C and the hybrid unit cell 15_a of FIG. 5A is that the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have different nanosheet widths in the first sub-cell 10_c and the second sub-cell 20_c of the hybrid unit cell 15_c. Therefore, the P-type GAA nanosheet transistors and the N-type GAA nanosheet transistors have asymmetry nanosheet structures in the first sub-cell 10_c and the second sub-cell 20_c.
In FIG. 5C, the P-type GAA nanosheet transistors of the same type of sub-cells (not shown) have the same nanosheet width and the N-type GAA nanosheet transistors of the same type of sub-cells (not shown) have the same nanosheet width in the same row of the hybrid cell array 100. In the first sub-cell 10_c, the nanosheet width W2_a of the P-type GAA nanosheet transistors is greater than the nanosheet width W2_b of the N-type GAA nanosheet transistors (i.e., W2_a>W2_b). In the second sub-cell 20_c, the nanosheet width W3_a of the P-type GAA nanosheet transistors is greater than the nanosheet width W3_b of the N-type GAA nanosheet transistors (i.e., W3_a>W3_b). In some embodiments, the nanosheet width W3_b is less than the nanosheet width W2_b, the nanosheet width W2_b is less than the nanosheet width W3_a, and the nanosheet width W3_a is less than the nanosheet width W2_a, i.e., W3_b<W2_b<W3_a<W2_a. Therefore, the maximum nanosheet width (e.g., W2_a) of the first sub-cell 10_c is greater than the maximum nanosheet width (e.g., W3_a) of the second sub-cell 20_c, and the minimum nanosheet width (e.g., W2_b) of the first sub-cell 10_c is greater than the minimum nanosheet width (e.g., W3_b) of the second sub-cell 20_c. Moreover, the minimum nanosheet width (e.g., W2_b) of the first sub-cell 10_c is less than the maximum nanosheet width (e.g., W3_a) of the second sub-cell 20_c.
FIG. 6A illustrates the hybrid unit cells 15_1 through 154 in the hybrid cell array 100 of FIG. 1, in accordance with some embodiments of the disclosure. In FIG. 6A, the hybrid unit cell 15_1 includes the first sub-cell 10_1 and the second sub-cell 201. The hybrid unit cell 15_2 includes the first sub-cell 10_2 and the second sub-cell 20_2. The hybrid unit cell 15_3 includes the first sub-cell 10_3 and the second sub-cell 20_3. The hybrid unit cell 15_4 includes the first sub-cell 10_4 and the second sub-cell 20_4. The hybrid unit cells 15_1 through 15_4 are formed in the same row of the hybrid cell array 100. Furthermore, the outer boundary of each of the first sub-cells 10_1 through 104 and the second sub-cells 20_1 through 204 is example, and is not intended to limit the disclosure. As described above, the cell height HT of the first sub-cells 10_1 through 104 is greater than the cell height HS of the second sub-cells 20_1 through 204 in the Y-direction. In some embodiments, the hybrid unit cells 15_1 through 154 have the same cell width in the X-direction. In some embodiments, the hybrid unit cells 15_1 through 15_4 have the different cell widths in the X-direction.
In FIG. 6A, the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. For example, the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 103 have the nanosheet width W2_a1. The P-type GAA nanosheet transistors of the first sub-cell 10_4 has the nanosheet width W2_a2 that is less than the nanosheet width W2_a1 (i.e., W2_a1>W2_a2). In such embodiment, the nanosheet structures 150 of the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 are aligned on the same edges (labeled 610) that are away from the interface between the N-type well region 120N_3 and the P-type well region 120P_3 (e.g., they are away from the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4). In some embodiments, the nanosheet structures with different nanosheet widths are formed by removing part of the nanosheet structures using lithography/etching steps.
The N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. For example, the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 103 have the nanosheet widths W2_b1, W2_b2, W2_b3 and W2_b4, respectively. In some embodiments, the nanosheet width W2_b1 is greater than the nanosheet width W2_b2, the nanosheet width W2_b2 is greater than the nanosheet width W2_b4, and the nanosheet width W2_b4 is greater than the nanosheet width W2_b3, i.e., W2_b1>W2_b2>W2_b4>W2_b3. In such embodiment, the nanosheet structures 150 of the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 are aligned on the same edges (labeled 620) that are away from the interface between the N-type well region 120N_3 and the P-type well region 120P_3 (e.g., they are away from the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4). Moreover, the P-type and N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 form the jogs at the interface between the N-type well region 120N_3 and the P-type well region 120P_3.
In FIG. 6A, the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. For example, the P-type GAA nanosheet transistors of the second sub-cell 20_1 has the nanosheet width W3_a1. The P-type GAA nanosheet transistors of the second sub-cells 20_2 and 20_3 have the nanosheet width W3_a2 that is less than the nanosheet width W3_a1 (i.e., W3_a1>W3_a2). The P-type GAA nanosheet transistors of the second sub-cell 20_4 has the nanosheet width W3_a3 that is greater than the nanosheet width W3_a1 (i.e., W3_a3>W3_a1). In such embodiment, the nanosheet structures 150 of the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 are aligned on the same edge (labeled 615) that is away from an interface between the N-type well region 120N_4 and the P-type well region 120P_4 (e.g., it is away from the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4).
The N-type GAA nanosheet transistors of the second sub-cells 20 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. For example, the N-type GAA nanosheet transistors of the second sub-cells 20_1 and 20_2 have the nanosheet width W3_b1. The N-type GAA nanosheet transistors of the second sub-cell 20_3 has the nanosheet width W3_b2 that is greater than the nanosheet width W3_b1 (i.e., W3_b2>W3_b1). The N-type GAA nanosheet transistors of the second sub-cell 20_4 has the nanosheet width W3_b3 that is greater than the nanosheet width W3_b1 and less than the nanosheet width W3_b2 (i.e., W3_b2>W3_b3>W3_b1). In such embodiment, the nanosheet structures 150 of the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 are aligned on the same edge (labeled 625) that is away from the interface between the N-type well region 120N_4 and the P-type well region 120P_4 (e.g., it is away from the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4). Moreover, the P-type and N-type GAA nanosheet transistors of the second sub-cells 201 through 20_4 form the jogs at the interface between the N-type well region 120N_4 and the P-type well region 120P_4.
In some embodiments, the maximum nanosheet width of the P-type GAA nanosheet transistors in the first sub-cells 10_1 through 104 is greater than the maximum nanosheet width of the P-type GAA nanosheet transistors in the second sub-cells 20_1 through 204, e.g., W2_a1>W3_a3. The maximum nanosheet width of the N-type GAA nanosheet transistors in the first sub-cells 10_1 through 10_4 is greater than the maximum nanosheet width of the N-type GAA nanosheet transistors in the second sub-cells 20_1 through 20_4, e.g., W2_b1>W3_b3.
In some embodiments, the minimum nanosheet width of the P-type (or N-type) GAA nanosheet transistors in the first sub-cells 10_1 through 104 is greater than the maximum nanosheet width of the P-type (or N-type) GAA nanosheet transistors in the second sub-cells 20_1 through 20_4.
In some embodiments, the maximum nanosheet width of the P-type (or N-type) GAA nanosheet transistors in the second sub-cells 20_1 through 204 is greater than the minimum nanosheet width of the P-type (or N-type)GAA nanosheet transistors in the first sub-cells 10_1 through 10_4, and less than the maximum nanosheet width of the P-type (or N-type)GAA nanosheet transistors in the first sub-cells 10_1 through 10_4.
In some embodiments, the average of the maximum nanosheet widths of the GAA nanosheet transistors in the second sub-cells 20 of the whole-row is equal to or less than the average of the minimum nanosheet widths of the GAA nanosheet transistors in the first sub-cells 10 of the whole-row. For example, the average AVG1 of the maximum nanosheet width W3_a1 in the second sub-cell 201, the maximum nanosheet width W3_b1 in the second sub-cell 20_2, the maximum nanosheet width W3_b2 in the second sub-cell 20_3 and the maximum nanosheet width W3_b2 in the second sub-cell 20_4 is less than or equal to the average AVG2 of the minimum nanosheet width W2_a1 in the first sub-cell 10_1, the minimum nanosheet width W2_b2 in the first sub-cell 102, the minimum nanosheet width W2_b3 in the first sub-cell 10_3 and the minimum nanosheet width W2_a2 in the first sub-cell 104, i.e., AVG1<AVG2, where AVG1=(W3_a1+W3_b1+W3_b2+W3_b2)/4 and AVG2=(W2_a1+W2_b2+W2_b3+W2_a2)/4.
In the hybrid cell array 100, the power lines (e.g., VDD line or VSS line) of the sub-cells 10 and 20 extend in the X-direction and disposed over the boundary between the first sub-cell 10 and the second sub-cell 20. For example, a VSS line (not shown) extends in the X-direction and disposed over the boundary between the N-type well regions 120N_3 and 120N_4. In such embodiment, the aligned edges of the nanosheet structures 150 of the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 are equidistant from the VSS line. Similarly, the aligned edges of the nanosheet structures 150 of the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 are equidistant from the VSS line.
FIG. 6B illustrates the hybrid unit cells 15_1 through 154 in the hybrid cell array 100 of FIG. 1, in accordance with some embodiments of the disclosure. In FIG. 6B, the hybrid unit cells 15_1 through 15_4 are formed in the same row of the hybrid cell array 100
In FIG. 6B, the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4 are aligned on the same edges (labeled 612) that face the interface between the N-type well region 120N_3 and the P-type well region 120P_3 (e.g., they are close to the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4).
The N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 are aligned on the same edges (labeled 622) that face the interface between the N-type well region 120N_3 and the P-type well region 120P_3 (e.g., they are close to the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4). Moreover, the P-type and N-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4 form the jogs at the N-type well region 120N_3 and the P-type well region 120P_3.
In FIG. 6B, the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 are aligned on the same edges (labeled 617) that face the interface between the N-type well region 120N_4 and the P-type well region 120P_4 (e.g., they are close to the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4).
The N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 are aligned on the same edges (labeled 627) that face the interface between the N-type well region 120N_4 and the P-type well region 120P_4 (e.g., they are close to the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4). Moreover, the P-type and N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 form the jogs at the N-type well region 120N_4 and the P-type well region 120P_4.
In FIG. 6B, a VSS line (not shown) extends in the X-direction and disposed over the boundary between the N-type well regions 120N_3 and 120N_4. In such embodiment, the aligned edges of the nanosheet structures 150 of the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4 are not equidistant from the VSS line. Similarly, the aligned edges of the nanosheet structures 150 of the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 are not equidistant from the VSS line. In some embodiments, the metal layer over a gap between the nanosheet structure 150 and the VSS line is used for routing.
FIG. 6C illustrates the hybrid unit cells 15_1 through 154 in the hybrid cell array 100 of FIG. 1, in accordance with some embodiments of the disclosure. In FIG. 6C, the hybrid unit cells 15_1 through 15_4 are formed in the same row of the hybrid cell array 100.
In FIG. 6C, the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the P-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4 are aligned along the centerline (labeled 614) in the X-direction. The N-type GAA nanosheet transistors of the first sub-cells 10_1 through 10_4 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 are aligned the centerline (labeled 624) in the X-direction. Moreover, the P-type and N-type GAA nanosheet transistors of the first sub-cells 10_1 through 104 form the jogs at two sided facing two different boundaries between the N-type and P-type well regions.
In FIG. 6C, the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the P-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 are aligned the centerline (labeled 619) in the X-direction. The N-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 arranged in the same sub-row of the hybrid cell array 100 have different nanosheet widths. In such embodiment, the nanosheet structures 150 of the N-type GAA nanosheet transistors of the second sub-cells 20_1 through 204 are aligned the centerline (labeled 629) in the X-direction. Moreover, the P-type and N-type GAA nanosheet transistors of the second sub-cells 20_1 through 20_4 form the jogs at two sided facing two different boundaries between the N-type and P-type well regions.
FIG. 7A is a simplified diagram of a hybrid cell array 100A of an IC, in accordance with some embodiments of the disclosure. The hybrid cell array 100A includes multiple hybrid unit cells 15A arranged in rows. Each hybrid unit cell 15A includes more than two types of sub-cells, and each type of sub-cell has an individual cell height. For example, the hybrid unit cell 15A includes the first sub-cell 10, the second sub-cell 20 and fourth sub-cell 40. The first sub-cell 10 has the cell height HT along the Y-direction in the layout, the second sub-cell 20 has the cell height HS along the Y-direction in the layout, and the fourth sub-cell 40 has the cell height HM along the Y-direction in the layout. The cell height HT of the first sub-cell 10 is higher than the cell height HM of the fourth sub-cell 40, and the cell height HM of the fourth sub-cell 40 is higher than the cell height of the second sub-cell 20, i.e., HS<HM<HT. In some embodiments, the cell height HM of the fourth sub-cell 40 is equal to the cell height HH of the third sub-cell 30.
In FIG. 7A, the rows of the hybrid unit cells 15A are arranged repeatedly in the hybrid cell array 100A. In each hybrid unit cell 15A, the fourth sub-cell 40 is disposed between the first sub-cell 10 and the second sub-cell 20, i.e., the fourth sub-cell 40 is sandwiched by the first sub-cell 10 and the second sub-cell 20 in the Y-direction.
In some embodiments, the second sub-cell 20 is disposed between the first sub-cell 10 and the fourth sub-cell 40. In some embodiments, the first sub-cell 10 is disposed between the second sub-cell 20 and the fourth sub-cell 40. In some embodiments, the regular cell array 100A of FIG. 7A and the hybrid cell array 100 of FIG. 1 have the same array height HA along the Y-direction in the layout. In some embodiments, the number of rows corresponding to the sub cells in the hybrid cell array 100A of FIG. 7A is equal to the number of rows corresponding to the sub cells in the hybrid cell array 100 of FIG. 1.
FIG. 7B is a simplified diagram of a hybrid cell array 100B of an IC, in accordance with some embodiments of the disclosure. The hybrid cell array 100B includes multiple hybrid unit cells 15B arranged in rows. Each hybrid unit cell 15B includes four types of sub-cells, and each type of sub-cell has an individual cell height. For example, the sub-cells 10, 20, 40 and 41 respectively have cell heights of HT, HS, HM and HM1 along the Y-direction in the layout. In some embodiments, the cell height HM is equal to the cell height HM1, i.e., HM=HM1. In some embodiments, the cell height HM is greater than the cell height HM1, i.e., HM>HM1. In some embodiments, the regular cell array 100B of FIG. 7B and the hybrid cell array 100 of FIG. 1 have the same array height HA along the Y-direction in the layout. In some embodiments, the number of rows corresponding to the sub cells in the hybrid cell array 100B of FIG. 7B is equal to the number of rows corresponding to the sub cells in the hybrid cell array 100 of FIG. 1.
FIG. 8A is a simplified diagram of a hybrid cell array 100C of an IC, in accordance with some embodiments of the disclosure. The hybrid cell array 100C includes multiple hybrid unit cells 15C arranged in rows. Each hybrid unit cell 15C includes two types of sub-cells, and each type of sub-cell has an individual cell height. For example, the first sub-cell 10 has the cell height HT along the Y-direction in the layout, and the second sub-cell 20 has the same cell height HS along the Y-direction in the layout.
Each hybrid unit cell 15C is divided into two groups GP_T and GP_S. Each of the groups GP_T and GP_S includes the same type of sub-cells in two adjacent rows. For example, the group GP_T includes the first sub-cells 10 in two adjacent rows, and the sub-group GP_S includes the second sub-cells 20 in two adjacent rows. In some embodiments, each hybrid unit cell 15C is divided into more than two groups.
FIG. 8B is a simplified diagram of a hybrid cell array 100D of an IC, in accordance with some embodiments of the disclosure. The hybrid cell array 100D includes multiple hybrid unit cells 15D arranged in rows. Each hybrid unit cell 15D includes two types of sub-cells, and each type of sub-cell has an individual cell height. For example, the first sub-cell 10 has the cell height HT along the Y-direction in the layout, and the second sub-cell 20 has the same cell height HS along the Y-direction in the layout.
Each hybrid unit cell 15D is divided into two groups GP_T and GP_S, The group GP_T includes the first sub-cells 10 in three adjacent rows, and the group GP_S includes the second sub-cells 20 in two adjacent rows. Therefore, the sub-groups GP_T and GP_S have different numbers of rows corresponding to the sub-cells.
Embodiments of semiconductor devices are provided. A hybrid cell array is formed by the hybrid unit cells arranged in rows. Each hybrid unit cell includes the first sub-cell 10 with the cell height HT and the second sub-cell 20 with the cell height HS. The GAA nanosheet transistors of the first sub-cell 10 have wider nanosheet widths than the GAA nanosheet transistors of the second sub-cell 20. Furthermore, the different nanosheet widths allows further speed and power partitioning within each of the sub-cells 10 and 20.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a hybrid unit cell. The hybrid unit cell includes at least one first sub-cell having a first cell height and at least one second sub-cell having a second cell height. The first sub-cell includes a plurality of first gate-all-around (GAA) nanosheet transistors. The second sub-cell includes a plurality of second GAA nanosheet transistors. The first cell height is higher than the second cell height, and the first GAA nanosheet transistor has a wider nanosheet width than the second GAA nanosheet transistor.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a hybrid cell array. The hybrid cell array includes a plurality of hybrid unit cells in a row. Each of the hybrid unit cells includes a first sub-cell having a first cell height and arranged in a first sub-row of the row, and a second sub-cell having a second cell height and arranged in a second sub-row of the row. The first cell height is higher than the second cell height. The plurality of first gate-all-around (GAA) nanosheet transistors of the first sub-cells in the first sub-row have different nanosheet widths, and a plurality of second GAA nanosheet transistors of the second sub-cells in the second sub-row have different nanosheet widths.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a hybrid cell array and a regular cell array. The hybrid cell array includes a plurality of hybrid unit cells. Each of the hybrid unit cells includes a first sub-cell having a first cell height and a second sub-cell having a second cell height. The cell height of the hybrid unit cell is equal to the sum of the first and second cell heights. The regular cell array includes a plurality of logic cells having a third cell height. The third cell height is greater than the second cell height and less than the first cell height. The first gate-all-around (GAA) nanosheet transistors in the first sub-cells have wider nanosheet widths than the second GAA nanosheet transistors in the second sub-cells.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Patent Application
20240312988
