Patent Application
20250014897
The present disclosure relates to a semiconductor substrate, a manufacturing method thereof and a manufacturing apparatus.
In recent years, compared with Si semiconductors and GaAs semiconductors, silicon carbide (SiC) semiconductors that can achieve wider bandgap energy, high electric field withstand voltage performance, high withstand voltage, high current, low on-resistance, high efficiency, low power consumption, and high-speed switching are attracting attention. The development of SiC power devices used for power control, such as Schottky barrier diode (SBD), metal oxide semiconductor field effect transistor (MOSFET), insulated gate bipolar transistor (IGBT), etc., is advancing. The SiC semiconductor substrate forming such a SiC power device is sometimes produced by bonding a monocrystalline SiC semiconductor substrate to a polycrystalline SiC semiconductor substrate by room temperature bonding or diffusion bonding in order to reduce manufacturing costs or provide required physical properties. (For example, referring to Patent Document 1).
Next, embodiments will be described with reference to the drawings. In the illustration of the drawings described below, the same or similar reference numerals are assigned to the same or similar parts. The drawings are schematic. In addition, the embodiments shown below are illustrative of devices and methods for embodying technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of components. Various modifications can be made to the embodiments.
A method of manufacturing a semiconductor substrate according to an embodiment will be described.
A schematic perspective view structure of a unit group of a 4H—SiC crystal applicable to the embodiment is shown in
As shown in
The [0001] axis and the [000-1] axis are along the axial direction of the hexagonal prism, and the plane with the [0001] axis as the normal line (the top surface of the hexagonal prism) is the (0001) plane (Si plane). On the other hand, the plane with the [000-1] axis as the normal line (the lower surface of the hexagonal prism) is the (000-1) plane (C plane). In addition, the directions perpendicular to the [0001] axis and passing through the non-adjacent vertices of the hexagonal prism when viewed from directly above the (0001) plane are respectively the a1 axis [2-1-10], the a2 axis [−12-10] and the a3 axis [−1-120].
As shown in
Next, as shown in
The graphene layer 12 applicable to the embodiment is shown as shown in
The furnace chamber 211 can be heated from 1500° C. to 1800° C. In addition, in the furnace chamber 211, at least one of inert gases such as fluorine gas and argon gas, hydrocarbon gas, fluorocarbon gas, nitrogen gas, and hydrogen gas can be flowed at a constant flow rate, while the pressure of the internal space can be made independent and controlled to between 50 Pa and 50 kPa. Further, under the condition of no flowing gas, a turbine pump and a dry vacuum pump can be used to evacuate a high vacuum up to 1×10−5 Pa. In addition, there is a vacuum preload chamber that can store all the supports in the lower part of the furnace chamber 211 and is made of a material with high heat resistance at high temperature, that is, a preparation chamber that can be evacuated and a lifting mechanism for the supports. It has a structure that infinitely cuts off the intrusion of external air through these structures, and has an infrared heating heater in the vacuum preload chamber, so that the support and the film-forming substrate 200 mounted on the support can be heated to 100° C. or higher while a high vacuum up to 1×10−5 Pa can be created by using a turbine pump and a dry vacuum pump.
The SiC monocrystalline substrate 11 that becomes the film-forming substrate 200 in the reaction furnace 210 is cleaned in advance and then dried and stored in the furnace chamber 211. To clean the SiC monocrystalline substrate 11, a modified RCA method commonly used in semiconductor cleaning can be used. The furnace chamber 211 storing the SiC monocrystalline substrate 11 is evacuated to 1×10−5 Pa or less.
Referring to the flow chart of
Description will be given sequentially according to the flowchart of
After the temperature of the furnace chamber 211 reaches 1400° C. from 1200° C., the process proceeds to step S13 and silicon fluoride gas is introduced into the furnace chamber 211. In step S14, silicon (Si) in the Si plane of the SiC monocrystalline substrate 11 is selectively etched with silicon fluoride gas to form a carbon (C) layer.
Here, from the viewpoint of reaction Gibbs energy, active species suitable for selectively etching Si in the Si plane of the SiC monocrystalline substrate 11 to form a C layer are studied. First, the reactivity of graphene (C) with various active species is studied. Tables 1 to 4 show the reaction Gibbs energy Gr based on the reaction formulas between graphene and chlorine (Cl2), hydrogen chloride (HCl), hydrogen (H2), and silicon tetrafluoride (SiF4) respectively. In each table, the standard enthalpy of formation AH, the standard entropy S, and the standard Gibbs energy of formation Gf corresponding to each substance in the reaction formula are also shown. The values of the standard Gibbs energy of formation Gf and the reaction Gibbs energy Gr at 25° C. and 1500° C. are shown.
H(kJ/mol)
H(kJ/mol)
H (kJ/mol)
H (kJ/mol)
Referring to Tables 1 to 4, it is observed that the reaction Gibbs energies Gr at 1500° C. are all positive and increase in order according to H2, HCl, Cl2 and SiF4, with the values with respect to H2 and HCl being relatively close. Based on these results, it is estimated that their reactivity with graphene (C) is ranked in the following order.
Similarly, for silicon (Si), the reactivity with various active species is also studied based on the reaction Gibbs energy. Tables 5 to 8 show the reaction Gibbs energy Gr based on the reaction formulas between silicon and chlorine (Cl2), hydrogen chloride (HCl), hydrogen (H2), and silicon tetrafluoride (SiF4) respectively.
H (kJ/mol)
H (kJ/mol)
H (kJ/mol)
H(kJ/mol)
Referring to Tables 5 to 8, it is observed that the reaction Gibbs energy Gr at 1500° C. is positive in H2, but negative in HCl, Cl2, and SiF4, and increases in order according to SiF4, Cl2, HCl, and H2. Based on these results, it is estimated that their reactivity with Si is ranked in the following order.
Substances that easily cause graphene etching are also studied from the viewpoint of reaction Gibbs energy. Tables 9 to 14 below show the reaction Gibbs energy Gr for graphene, based on the reaction formulas with water (H2O), hydroxyl radical (OH), oxygen (O2), nitrogen (N2), hydrogen fluoride (HF), dichlorosilane (SiH2Cl2), chlorine (Cl2), hydrogen chloride (HCl), hydrogen (H2), silicon tetrafluoride (SiF4), methane (CH4) and monosilane (SiH4) respectively.
H (kJ/mol)
H (kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
Referring to Table 9 to Table 12, it is observed that the reaction Gibbs energy Gr at 1500° C. is negative in O2, OH, H2O, SiH4 and SiH2Cl2 and increases in order, is positive in H2, N2, CH4, HF, HCl, Cl2 and SiF4 and increase in order, among which the values for H2, N2, CH4 and HF are relatively close, and the values for HF and HCl are almost the same. Therefore, it is estimated that the reactivity of each of the above substances with graphene is ranked in the following order.
In order to selectively etch the silicon (Si) in the Si plane of the SiC monocrystalline substrate 11 and form the carbon (C) layer, a substance with high reactivity with Si and low reactivity with graphene is suitable. After studying chemical reactivity from the perspective of the reaction Gibbs energy Gr, it is determined that silicon tetrafluoride (SiF4) is fit for such a substance. It is contemplated that not only silicon tetrafluoride, but other silicon fluorides such as disilicon hexafluoride (Si2F6) with similar chemical properties can also be used.
In addition, higher-order silicon fluoride gases with order higher than trisilicon octafluoride (Si3F8) have the properties that the higher the order of compound, the lower the thermal decomposition temperature, and the easier it is to release Si atoms and fluorine atoms. For the formation of carbon layer, though a mechanism that selectively etches Si from the surface of the SiC substrate with fluorine atoms to leave carbon is used, the high-order silicon fluoride gas excessively increases the Si partial pressure or vapor pressure in the gas phase, so it is easy to cause a reaction called Si vapor pressure etching, that is, the remaining carbon reacts with Si to cause a secondary reaction, which makes Si2C or SiC2 become sublimating compounds. As a result, carbon is easily etched away and disappears, and is difficult to be controlled. For this reason, in the embodiment, it is limited to use of low-order silicon fluoride gases up to disilicon hexafluoride gas in view of practicality.
In addition, although chlorine (Cl2) has properties close to silicon tetrafluoride (SiF4), when being used to form a carbon layer, the reaction Gibbs energy of Cl2 for carbon etching is 624 KJ/mol. In contrast, it is 2149 KJ/mol for SiF4. Because the carbon layer needs to be controlled at the atomic level, Cl2 is difficult to be used and is considered unsuitable.
Returning to step S13 in
In step S14, the silicon fluoride gas introduced into the furnace chamber 211 in step S13 thermally etches the Si plane of the SiC monocrystalline substrate 11 to form the carbon layer. The etched amount of the Si plane is controlled by the introduction time and temperature of silicon fluoride, and the temperature and gas exposure time conditions are set according to the target number of graphene layers formed. When the desired etched amount and the number of graphene layers are reached, the supply of silicon fluoride gas to the furnace chamber 211 is stopped in step S15.
After the Si plane of the SiC monocrystalline substrate 11 is etched to form the carbon layer through the procedure of the surface thermal etching A including step S12 to step S15, the carbon remained from the sublimation of silicon in the Si plane of the SiC monocrystalline substrate 11 is crystallized to form the graphene layer 12 through the procedure of the surface thermal decomposition B including step S16 to step S20.
In step S16, the pressure of the Ar gas atmosphere supplied to the furnace chamber 211 is readjusted to 700 Torr, that is, 93,000 Pa, and the temperature of the furnace chamber 211 is heated from 1650° C. to 1700° C. Similar to step S12, a rapid thermally-sensitive processor can also be used to rapidly raise the temperature at a speed of 100° C./second or more. In addition, similar to step S12, the furnace chamber 211 can be heated by the resistance heating heater 216 provided in the reaction furnace 210, and can be heated by infrared irradiation simultaneously. Further, high-frequency induction heating and infrared irradiation heating can also be used. Alternatively, rapid heating may be performed by transporting the SiC monocrystalline substrate 11 in the furnace chamber 211 that has been heated to a high temperature.
In this way, step-bunching of the SiC monocrystalline substrate 11 toward the Si layer surface is suppressed to a minimum by rapidly heating the SiC monocrystalline substrate 11 in step S16. By quickly forming a low-defect layer 0 (a buffer layer) at this stage, it is possible to suppress the sublimation of silicon (Si) to a minimum and maintain a smooth surface with little progress in bunching.
After the temperature of the furnace chamber 211 reaches 1700° C. from 1650° C., the process proceeds to step S17, where silicon fluoride gas is introduced into the furnace chamber 211. As mentioned above, in the reaction furnace 210 called the batch-type vertical tubular furnace, since the uniform heating length in the furnace chamber 211 is relatively long, it is contemplated that SiF4 is gradually thermally decomposed in the furnace chamber 211. For the silicon fluoride, it may use the Si2F6 monomer alone or a mixed gas of SiF4 and Si2F6 with an adjusted mixing ratio.
In step S18, the Si plane of the SiC monocrystalline substrate 11 is thermally decomposed by silicon fluoride gas to sublime silicon (Si), and the remaining carbon layer is crystallized and converted into a graphene layer. In this way, the first composite 81 in which the graphene layer is laminated on the Si plane of the SiC monocrystalline substrate 11 is formed. When the grapheneization of the carbon layer is completed, the process proceeds to step S17 and the supply of silicon fluoride gas is stopped. In addition, the temperature of the furnace chamber 211 is lowered in step S20, and the supply of Ar gas is stopped in step S21. Afterwards, the first composite 81 is taken out from the furnace chamber 211.
In this way, after the Si plane of the SiC monocrystalline substrate 11 is etched through the surface thermal etching A including steps S12 to step S15 to form the carbon layer, the procedure of surface thermal decomposition B including steps S16 to S20, during which the carbon remaining from the sublimation of silicon in the Si plane of the SiC monocrystalline substrate 11 is crystallized to form the graphene layer 12, is performed, thereby forming the first composite 81, in which the graphene layer is laminated on the Si plane of the SiC monocrystalline substrate 11.
The process will be explained sequentially according to the flowchart of
After the temperature of the furnace chamber 211 reaches 1700° C. from 1650° C., the process proceeds to step S17, where silicon fluoride gas is introduced into the furnace chamber 211. For the silicon fluoride, it may use the Si2F6 monomer alone or a mixed gas of SiF4 and Si2F6 with an adjusted mixing ratio. In step S18, the Si plane of the SiC monocrystalline substrate 11 is thermally decomposed by silicon fluoride gas to sublime silicon (Si), and the remaining carbon layer is crystallized and converted into a graphene layer. The graphene layer may be a single layer or a layer 0 (a buffer layer). Proceeding to step S19, the supply of silicon fluoride gas is stopped, and the temperature of the furnace chamber 211 is lowered in step S20. In step S21, the supply of Ar gas is stopped, and then the first composite 81 with the graphene layer laminated on the Si plane of the SiC monocrystalline substrate 11 is taken out from the furnace chamber 211.
Next, as shown in
The film-forming substrate 200 in the reaction furnace 210 is the first composite 81 in which the graphene layer 12 is laminated on the Si plane of the SiC monocrystalline substrate 11. The graphene layer 12 may be a single layer or a layer 0 (a buffer layer). The furnace chamber 211 storing the first composite 81 is evacuated to 1×10−5 Pa or less.
In the first step S21, Ar gas serving as a carrier gas is supplied to the furnace chamber 211 of the reaction furnace 210. In step S22, the atmosphere pressure of the furnace chamber 211 is adjusted to about 800 Torr, that is, about 110,000 Pa, and the atmosphere is heated from 1,500° C. to 1,600° C. The temperature is determined based on the desired growth rate and film quality. In the first composite 81, the Si plane of the SiC monocrystalline substrate 11 is covered by the graphene layer 12, and the graphene layer 12 suppresses the sublimation of Si without step-bunching. Therefore, rapid heating is not needed, and the resistance heating heater 216 provided in the reaction furnace can also be used for heating.
After the temperature of the furnace chamber 211 reaches 1,600° C. from 1,500° C., silicon fluoride gas together with hydrocarbon gas or carbon fluoride gas are introduced into the furnace chamber 211 in step S23, serving as the material gases for forming the SiC epitaxial growth layer 13. In step S24, the SiC epitaxial growth layer 13 is formed on the Si plane of the SiC monocrystalline substrate 11 using these material gases through van der Waals growth with the graphene layer 12 interposed therebetween.
Here, from the viewpoint of reaction Gibbs energy, types of material gases suitable for forming a SiC epitaxial growth layer are studied. First, the reactivity of silicon tetrafluoride (SiF4) with various fluorocarbons is studied. Tables 21 to 25 show the reaction Gibbs energies Gr based on the reaction formulas of SiF4 with tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), tetrafluoroethylene (C2F4) and fluorinated acetylene (C2HF) respectively.
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
As shown in Tables 21 to 25, all the reaction Gibbs energies at 1500° C. based on the reaction formulas of SiF4 and CF4, C2F6, C3F8, C2F4, and C2HF are positive. From this, it is inferred that the reaction in which SiF4 reacts with any of these fluorocarbons to form the silicon carbide on the right is unlikely to occur.
The reactivity of silicon tetrafluoride (SiF4) with various hydrocarbons has also been studied. Tables 26 to 30 show the reaction Gibbs energies Gr based on the reaction formulas of SiF4 with methane (CH4), ethane (C2H6), propane (C3H8), ethylene (C2H4), and acetylene (C2H2) respectively.
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
As shown in Tables 26 to 30, the reaction Gibbs energies Gr at 1500° C. based on the reaction formulas of SiF4 and CH4, C2H6, C3H8, C2H4, and C2H2 are all positive. From this, it is inferred that the reaction in which SiF4 reacts with any of these hydrocarbons to form the silicon carbide on the right is unlikely to occur.
Next, the reactivity of disilicon hexafluoride (Si2F6) with various fluorocarbons is studied. Tables 31 to 35 show the reaction Gibbs energies Gr based on the reaction formulas of Si2F6 with tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), tetrafluoroethylene (C2F4) and fluorinated acetylene (C2HF) respectively.
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
As shown in Tables 31 to 35, the reaction Gibbs energies Gr at 1,500° C. based on the reaction formulas of Si2F6 with CF4, C2F6, C3F8, C2F4, and C2HF are all positive. From this, it is inferred that the reaction in which SiF4 reacts with any of these hydrocarbons to form the silicon carbide on the right is unlikely to occur.
The reactivity of Si2F6 with various hydrocarbons is also studied. Tables 36 to 40 show the reaction Gibbs energies Gr based on the reaction formulas of Si2F6 with methane (CH4), ethane (C2H6), propane (C3H8), ethylene (C2H4), and acetylene (C2H2), respectively.
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
H(kJ/mol)
As shown in Tables 36 to 40, if CH4 is excluded, the reaction Gibbs energies Gr at 1,500° C. based on the reaction formulas of Si2F6 with C2H6, C3H8, C2H4 and C2H2 are all positive. From this, it is believed that the reaction in which Si2F6 reacts with any of these hydrocarbons to generate the silicon carbide on the right is unlikely to occur. In the case of CH4, since the reaction Gibbs energy with Si2F6 at 1,500° C. is negative, the reaction to generate silicon carbide on the right side of the reaction formula may proceed. Therefore, it is necessary to conduct research when using a combination of Si2F6 and CH4 as the material gas.
In this way, when studying chemical reactivity based on the reaction Gibbs energy, it is clarified that the reaction Gibbs energy of silicon tetrafluoride (SiF4) and silicon hexafluoride (Si2F6) with various fluorocarbons or hydrocarbons is approximately positive at a temperature of about 1,500° C. for forming the epitaxial growth layer 13, and the reaction to form silicon carbide does not proceed spontaneously. Therefore, in the furnace chamber 211 of the reaction furnace 210, even if SiF4 and Si2F6 and various fluorocarbons or hydrocarbons are used as material gases in an atmosphere of about 1,500° C., the reaction to form silicon carbide will not occur. It is believed that the single crystal gradually grows epitaxially on the Si plane of the SiC monocrystalline substrate 11 at the interface adjacent the graphene layer 12.
Returning to step S23 in
Although a combination of silicon fluoride and hydrocarbon has been shown as the material gas, a combination of silicon fluoride and fluorocarbon may be used instead of or together with the combination of silicon fluoride and hydrocarbon. Tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), tetrafluoroethylene (C2F4), fluoroacetylene (C2HF), etc. can also be used for fluorocarbons. In addition, silicon fluoride is not limited to silicon tetrafluoride (SiF4), and other silicon fluorides such as disilicon hexafluoride (Si2F6) can also be used.
In addition, as mentioned above, high-order silicon fluoride gases, such as trisilicon octafluoride (Si3F8) or those having higher order have the property that the higher the order of the compound, the lower the thermal decomposition temperature, and the easier it is to release Si atoms and fluorine atoms. When used for SiC epitaxial growth, Si precursor gas (silicon fluoride gas) and carbon precursor gas (carbon fluoride gas) are used together to adjust the composition ratio of the grown SiC single crystal to Si:C=1:1 (Stoichiometric composition ratio=stoichiometry). However, high-order silicon fluoride gases, such as trisilicon octafluoride (Si3F8) gas or those having higher order are easily decomposed at relatively low temperatures. In contrast, it is necessary to balance the supply amount of carbon from the fluorocarbon gas, and it is necessary for silicon carbon gases to use even higher order compounds. In this case, the decomposition process of each gas in the furnace becomes easy to proceed, and it becomes difficult to optimize the batch-to-batch and in-plane uniformity of the stoichiometry. Under such circumstance, if the growth temperature is lowered, then the optimal adjustment will become easier, but on the contrary, the crystal quality of SiC is likely to decrease due to polymorphous blending, which is equal to an increase in inclusions, etc. For this reason, in the embodiment, in view of practicality, it is limited to use low-order silicon fluoride gases not higher than disilicon hexafluoride gas only.
In addition, as mentioned above, although chlorine gas (Cl2) has properties close to silicon tetrafluoride (SiF4), when used for SiC epitaxial growth, Cl2 is a compound that does not contain Si or C and cannot be used as a stacking gas. Although it is also contemplated to be used as an additive gas, it is considered that there is almost no advantage in adding Cl2 because stacking gases such as SiF4 or C2F6 are less likely to etch carbon than Cl2 and are easy to preserve.
After the SiC epitaxial growth layer 13 grown on the graphene layer 12 reaches a required thickness and the second composite 82, in which the SiC epitaxial growth layer 13 is stacked on the SiC monocrystalline substrate 11 with the graphene layer 12 interposed therebetween, is formed in step S24, the supply of the material gas is stopped immediately in step S25. Further, the temperature of the furnace chamber 211 is lowered in step S26, the supply of Ar gas is stopped in step S27, and then the second composite 82 is taken out from the furnace chamber 211. In addition, the Ar gas serving as the carrier gas may be switched to hydrogen gas in the middle of forming the SiC epitaxial growth layer 13. This can almost completely suppress unnecessary deposits on the inner wall of the furnace chamber 211 and the like, so that the maintenance cycle and the life of the furnace fixtures can be extended.
In the furnace chamber 221 of the reaction furnace 220 of the modified example, a workbench 225 on which a plurality of film-forming substrates 200 can be placed and a mask 226 facing the workbench 225 with a predetermined gap therebetween are supported by pillars extending from a bottom plate 223 and a top plate 224 of the furnace chamber 221. A gas supply hole for supplying the gas 201 is provided substantially in the center of the bottom surface of the mask 226. In addition, the bottom plate 223 of the furnace chamber 221 is provided with an exhaust port for discharging exhaust gas 202 from the furnace chamber 221. The workbench 225 and the mask 226 each have a resistance heating heater 227. The surfaces of the workbench 225 and the mask 226 and the furnace wall 222 are formed by the SiC base 231 and are further surrounded by a heat insulating material 232 and a water cooling chamber 233. The surfaces of the workbench 225 and the mask 226 are also covered by the SiC base. The reaction furnace 220 of the modified example is also called a semi-batch reactor.
In the reaction furnace 220 of the modified example, like the reaction furnace 210 of the embodiment, the first composite 81 can also be formed through a series of steps shown in
As shown in
The stress layer 14 of the embodiment is composed of a carbon film. The carbon film is composed of polycrystalline diamond film or diamond-like carbon film. When the carbon film is a polycrystalline diamond film, it can be obtained by a microwave chemical vapor deposition (CVD) apparatus, etc., and when it is a diamond-like carbon film, it can be obtained by a radio frequency (RF) plasma chemical vapor deposition (CVD) apparatus etc. When forming the carbon film, the required film adhesion can be obtained by forming the film while applying a negative potential to the film-forming substrate side for applying ion impact in the initial stage of film formation.
As shown in
In the embodiment, a carbon adhesive is used for the adhesive layer 16. The carbon adhesive is an adhesive that contains phenolic resin, a thermosetting resin, as the main component and is blended with solid carbon components, etc., so it can maintain bonding strength through self-carbonization even at high temperatures.
The graphite substrate 19 may have a glassy carbon film on its surface. Since the adhesive force between the glassy carbon film and the carbon adhesive is strong, the SiC epitaxial growth layer 13 can be easily peeled off from the graphene layer 12 and the SiC monocrystalline substrate 11, thereby improving the yield.
The graphite substrate 19 is a temporary substrate with a slightly larger outline size. For example, if the SiC monocrystalline substrate 11 has a diameter of about 10 cm, then a graphite substrate 19 with a diameter of about 11 cm that is about 10 mm larger is used. For example, if the SiC monocrystalline substrate 11 is about 15 cm in diameter, then a graphite substrate 19 with an outline size of about 16 cm in diameter is used. When the temporary substrate (the graphite substrate 19) that is larger than the SiC monocrystalline substrate 11 in size is inserted and neatly arranged in the wafer boat tank of the batch-type vertical CVD furnace, it has the advantage of keeping the boat support mark outside the substrate active area.
As shown in
As shown in
The graphene layer 12 is removed from the laminate of the SiC monocrystalline substrate 11 and the graphene layer 12 removed from the fifth composite 85 by etching or polishing. In the process of etching the graphene layer 12, plasma ashing using oxygen plasma can be applied, for example. Since the surface is oxidized in the Si plane of the SiC monocrystalline substrate 11 during the etching of the graphene layer 12 by oxygen plasma, wet etching using hydrogen fluoride (HF) is performed. In addition, in the step of polishing the graphene layer 12, the graphene layer 12 is removed by, for example, chemical mechanical polishing (CMP). Here, in the Si plane of the SiC monocrystalline substrate 11, the average roughness Ra of the surface in the wet etching process is, for example, about 1 nm or less. As a result, the SiC monocrystalline substrate 11 can be reused.
As shown in
The SiC polycrystalline growth layer 17 is deposited and stacked to a thickness that can obtain mechanical strength required as a substrate for a SiC-based semiconductor element, thereby forming a seventh composite 87. The film thickness of the SiC polycrystalline growth layer 17 is expected to be between about 150 μm and about 500 μm. The plate thickness of the completed SiC composite substrate (the SiC polycrystalline growth layer 17+the SiC epitaxial growth layer 13) is adjusted to between about 150 μm and about 500 μm as needed. By thinning the film thickness of the SiC polycrystalline growth layer 17, the thermal conductivity is improved. In addition, it is desirable that the deposition temperature of the SiC polycrystalline growth layer 17 is in the range of about 1300° C. to about 1600° C.
As shown in
As shown in
In addition, as shown in
The highly doped layer 13a can be formed using, for example, high-dose ion implantation technology. For example, in the case of an n-type semiconductor, phosphorus (P) ions are implanted at a high dose to form the highly doped layer 13a. When formed by P ion implantation, although there is an influence on the crystallinity of the C plane of the SiC epitaxial growth layer 13 into which P ions are implanted, the Si plane that becomes the device plane is already formed, and the crystallinity of the Si plane is preserved.
When forming the SiC epitaxial growth layer (SiC-epi) 13 shown in
In the embodiment, the stress layer 14 is composed of the carbon film such as the polycrystalline diamond film or the diamond-like carbon film. However, in a modified example, a silicon nitride film is used as a stress layer 15 of the modified example.
As shown in
As shown in
As shown in
Regardless of the case where the tenth composite 90 is bonded to one side of the graphite substrate 19 of the temporary substrate to form the eleventh composite 91, or the case where the tenth composites 90 are bonded to both sides of the graphite substrate 19 respectively to form the twelfth composite 92, the following is the same as in the embodiment. That is, the carbon adhesive is used for the adhesive layer 16, the graphite substrate 19 can have a glassy carbon film on the surface, and the outline size of the graphite substrate 19 of the temporary substrate is greater than the SiC monocrystalline substrate 11, so when the graphite substrate 19 is inserted and neatly arranged in the wafer boat tank of the batch-type vertical CVD furnace, there is the advantage of keeping the boat support mark outside the substrate active area. In the following description, the twelfth composite 92 in which the tenth composite 90 is bonded to both sides of the graphite substrate 19 is used. However, same goes for the eleventh composite 91 in which the tenth composite 90 is bonded to only one side of the graphite substrate 19.
The thirteenth composite 93 shown in
The stress layer 15 of the modified example made of silicon nitride in the thirteenth composite 93 is removed by an appropriate method such as etching and grinding. For etching, dry etching using fluorocarbon-based gas plasma or wet etching using hot phosphoric acid can be used. After the stress layer 15 is removed, like the ninth composite 89 of the embodiment shown in
The semiconductor substrate of the embodiment is shown as the third composite 83 in
In the semiconductor substrate of this embodiment, the SiC epitaxial growth layer 13 is formed in an atmosphere containing fluorine such as silicon fluoride or carbon fluoride, and the SiC epitaxial growth layer 13 contains fluorine. In the SiC epitaxial growth of the previous technology, atmospheric nitrogen mainly enters the C site (C is replaced with N) of the SiC crystal structure, usually at an impurity concentration of 1015 to 1018 levels per cubic centimeter. However, in the semiconductor substrate of the embodiment, since fluorine has a higher reactivity with Si than nitrogen, it becomes a state in which part of the nitrogen impurity concentration is replaced by fluorine. The fluorine concentration is about 1015 levels per cubic centimeter or less. From the semiconductor substrate of this embodiment, the SiC composite substrate 10 shown in
Specifically, as shown in
Taking the fifth composite 85 as an example, after the adhesive layer 16 is cured, as shown in
The SiC composite substrate 10 produced by the manufacturing method of the semiconductor substrate according to the embodiment or the SiC composite substrate 10 produced from the semiconductor substrate of the embodiment can be used for the production of various SiC-based semiconductor elements, for example. Hereinafter, as the examples thereof, SiC-SBD, SiC trench gate type TMOSFET, and SiC planar gate type MOSFET will be described.
As a semiconductor element produced using the SiC composite substrate, a SiC-SBD 20 has the SiC composite substrate 10 including the SiC polycrystalline growth layer (SiC-poly) 17 and the SiC epitaxial growth layer (SiC-epi) 13, as shown in
The SiC polycrystalline growth layer 17 is doped to n+ type (the impurity density is, for example, between about 1×1018 cm−3 and about 1×1021 cm−3), and the SiC epitaxial growth layer 13 is doped to n−-type (the impurity density is, for example, between about 5×1014 cm−3 and about 5×1016 cm−3). The highly doped layer 13a is doped to a concentration higher than that of the SiC epitaxial growth layer 13.
In addition, the SiC epitaxial growth layer 13 may have any crystal structure of 4H—SiC, 6H—SiC, or 2H—SiC.
As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.
As the p-type doping impurity, for example, B (boron), Al (aluminum), etc. can be used.
The back surface ((000-1) C plane) of the SiC polycrystalline growth layer 17 is provided with a cathode electrode 21 covering the entire area thereof, and the cathode electrode 21 is connected to a cathode terminal K.
In addition, the front surface 13b (for example, the (0001) Si plane) of the SiC epitaxial growth layer 13 is provided with a contact hole 23 that exposes a portion of the SiC epitaxial growth layer 13 as an active region 22, and a field insulating film 25 is formed in a field region 24 surrounding the active region 22.
The field insulating film 25 contains SiO2 (silicon dioxide), but may also contain other insulators such as silicon nitride (SiN). An anode electrode 26 is formed on the field insulating film 25 and is connected to an anode terminal A.
A p-type Junction Termination Extension (JTE) structure 27 is formed in contact with the anode electrode 26 near the front surface 13b (surface layer portion) of the SiC epitaxial growth layer 13. The JTE structure 27 is formed along the contour of the contact hole 23 so as to span the inside and outside of the contact hole 23 of the field insulating film 25.
As a semiconductor element produced using the SiC composite substrate 10 of the embodiment, a trench gate TMOSFET 30 has the SiC composite substrate 10 including the SiC polycrystalline growth layer 17 and the SiC epitaxial growth layer 13, as shown in
The SiC polycrystalline growth layer 17 is doped to n+ type (the impurity density is, for example, between about 1×1018 cm−3 and about 1×1021 cm−3), and the SiC epitaxial growth layer 13 is doped to n-type (the impurity density is, for example, between about 5×1014 cm−3 and about 5×1016 cm−3). The highly doped layer 13a is doped to a concentration higher than that of the SiC epitaxial growth layer 13.
In addition, the SiC epitaxial growth layer 13 may have any crystal structure of 4H—SiC, 6H—SiC, or 2H—SiC.
As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.
As the p-type doping impurity, for example, B (boron), Al (aluminum), etc. can be used.
The back surface ((000-1) C plane) of the SiC polycrystalline growth layer 17 is provided with a drain electrode 31 covering the entire area thereof, and the drain electrode 31 is connected to a drain terminal D.
A p-type (the impurity density is, for example, between about 1×1016 cm−3 and about 1×1019 cm−3) main body region 32 is formed near the front surface 13b ((0001) Si plane) of the SiC epitaxial growth layer 13 (the surface layer portion). In the SiC epitaxial growth layer 13, the portion on the SiC polycrystalline growth layer 17 side with respect to the main body region 32 is an n-type drain region 33 (13) that maintains the state of the SiC epitaxial growth layer 13.
A gate trench 34 is formed in the SiC epitaxial growth layer 13. The gate trench 34 penetrates the main body region 32 from the surface 13b of the SiC epitaxial growth layer 13, and its deepest portion reaches the drain region 33 (13).
A gate insulating film 35 is formed on the inner surface of gate trench 34 and surface 13b of the SiC epitaxial growth layer 13 so as to cover the entire inner surface of the gate trench 34. Also, a gate electrode 36 is buried in the gate trench 34 by filling the inside of the gate insulating film 35 with, for example, polysilicon. The gate electrode 36 is connected to a gate terminal G.
An n+-type source region 37 forming a part of the side surface of the gate trench 34 is formed on the surface layer portion of the main body region 32.
In addition, a p+-type (the impurity density is, for example, between about 1×1018 cm−3 and about 1×1021 cm−3) body contact area 38 connected to the main body region 32 is formed in the SiC epitaxial growth layer 13 from its surface 13b to penetrate the source region 37.
An interlayer insulating film 41 containing SiO2 is formed on the SiC epitaxial growth layer 13. A source electrode 43 is connected to a source region 37 and a body contact region 38 via the contact hole 42 formed in the interlayer insulating film 41. The source electrode 43 is connected to a source terminal S.
In a state where a predetermined potential difference is generated between the source electrode 43 and the drain electrode 31 (between the source and the drain), a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) is applied to the gate electrode 36 so that a channel can be formed in the main body region 32 near the interface with the gate insulating film 35 by the electric field from the gate electrode 36. Thereby, a current can flow between the source electrode 43 and the drain electrode 31, and the SiC-TMOSPET 30 can be brought into an on state.
As a semiconductor element produced using the SiC composite substrate 10, a planar gate type MOSFET 50 has the SiC composite substrate 10 including the SiC polycrystalline growth layer 17 and the SiC epitaxial growth layer 13, as shown in
The SiC polycrystalline growth layer 17 is doped to n+ type (the impurity density is, for example, between about 1×1018 cm−3 and about 1×1021 cm−3), and the SiC epitaxial growth layer 13 is doped to n−-type (the impurity density is, for example, between about 5×1014 cm−3 and about 5×1016 cm−3).
In addition, the SiC epitaxial growth layer 13 may have any crystal structure of 4H—SiC, 6H—SiC, or 2H—SiC.
As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used.
As the p-type doping impurity, for example, B (boron), Al (aluminum), etc. can be used.
The back surface ((000-1) C plane) of the SiC composite substrate 10 is provided with a drain electrode 51 covering the entire area thereof, and the drain electrode 51 is connected to a drain terminal D.
In the vicinity (surface layer portion) of the front surface 13b ((0001) Si plane) of the SiC epitaxial growth layer 13, a p-type (impurity density, for example, between about 1×1016 cm−3 and about 1×1019 cm−3) main body region 52 is formed as well shaped. In the SiC epitaxial growth layer 13, the portion on the SiC composite substrate 10 side with respect to the main body region 52 is the n-type drain region 53 (13) that maintains the state after epitaxial growth.
An n+-type source region 54 is formed at the surface layer portion of the main body region 52 at a distance from the periphery of the main body region 52.
Inside the source region 54, a p+-type (impurity density, for example, between about 1×1018 cm−3 and about 1×1021 cm−3) body contact region 55 is formed. The body contact region 55 penetrates the source region 54 in the depth direction and is connected to the main body region 52.
A gate insulating film 56 is formed on the surface 13b of the SiC epitaxial growth layer 13. The gate insulating film 56 covers the portion of the main body region 52 surrounding the source region 54 (the peripheral portion of the main body region 52) and the outer periphery of the source region 54.
A gate electrode 57 made of, for example, polysilicon is formed on the gate insulating film 56. The gate electrode 57 faces the peripheral portion of the main body region 52 via the gate insulating film 56. The gate electrode 57 is connected to a gate terminal G.
An interlayer insulating film 58 containing SiO2 is formed on the SiC epitaxial growth layer 13. The source electrode 62 is connected to the source region 54 and the body contact region 55 via the contact hole 61 formed in the interlayer insulating film 58. A source terminal S is connected to the source electrode 62.
In a state where a predetermined potential difference is generated between the source electrode 62 and the drain electrode 51 (between the source and the drain), a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) is applied to the gate electrode 57 so that a channel can be formed in the main body region 52 near the interface with the gate insulating film 56 by the electric field from the gate electrode 57. Thereby, a current can flow between the source electrode 62 and the drain electrode 51, and the planar gate type MOSFET 50 can be brought into an on state.
As described above, according to the embodiment, in the step of surface thermal etching A (see
In this way, according to the embodiment, the graphene layer 12 with low defects can be formed. Therefore, when the SiC epitaxial growth layer 13 is formed by the van der Waals epitaxial growth method in the next step, it is possible to improve the resistance of the residual air components and Si precursor decomposition products existing in the furnace chamber 211 to graphene etching.
Instead of performing the procedure of surface thermal etching A, the procedure of surface thermal decomposition B may be performed from the beginning, and the silicon fluoride gas may be used to form graphene in the procedure of surface thermal decomposition B (referring
In the embodiment, since the inert gas Ar gas is used as the carrier gas when forming the SiC epitaxial growth layer 13 by using the van der Waals epitaxial growth method, parasitic accumulation is occurred on the furnace wall 211 of the reaction furnace 210, or the formation of gas phase nuclei and particles increases. Therefore, there is a concern that the crystal quality of the SiC epitaxial growth layer 13 will decrease. However, in the embodiment, since the silicon fluoride gas used as the material gas of silicon (Si) in the van der Waals epitaxial growth method has the property of strongly reacting with and removing Si, parasitic accumulation and the increase in formation of gas phase nuclei and particles can be strongly suppressed.
In the embodiment, silicon fluoride gas is used as the Si material gas of the SiC epitaxial growth layer 13 using the van der Waals epitaxial growth method, and hydrocarbon gas is used as the C material gas. Among them, silicon fluoride gas hardly reacts with C, but when silicon fluoride gas coexists, there is a reaction path that produces hydrogen fluoride (HF) which reacts weakly with graphene as a secondary reaction of their decomposition products. However, since the fluorine (F, F2) freed from the decomposition of silicon fluoride gas has strong reactivity with Si, in general, compared with the case where silane (SiH4) or dichlorosilane (Si2H2Cl2) is used as the material gas of Si, the use of silicon fluoride gas can better suppress the etching of graphene. In addition, as the material gas of C, fluorocarbon gas may be used together with the hydrocarbon gas or instead of the hydrocarbon gas. However, in this case, the etching of graphene can also be suppressed.
According to the embodiment, by separating the SiC monocrystalline substrate 11 and replacing it with a temporary substrate of the highly heat-resistant graphite substrate 19 before forming the SiC polycrystalline growth layer 17 by CVD, it is possible to prevent unnecessary adhesion of polycrystalline SiC to the SiC monocrystalline substrate 11, maximize the reusability of the SiC monocrystalline substrate 11 and enable further cost reduction.
In the embodiment, the stress layer 14 is formed of a carbon-based film (polycrystalline diamond film or diamond-like carbon film). In the modified example, the stress layer 15 is formed of a silicon nitride film, and utilizing internal stress and thermal stress in the film, it is assumed that the SiC epitaxial growth layer 13 can be easily peeled off from the graphene layer 12. Furthermore, thereby, metal contamination which becomes a problem when using a metal stress film can be avoided. The formation of the carbon-based film or the silicon nitride film has the characteristics of good adhesion to the substrate, excellent high heat resistance, and the ability to obtain large stress.
According to the embodiment, by making the graphite substrate 19 larger than the SiC monocrystalline substrate 11, it is possible to use a batch type vertical tubular furnace or other epitaxial growth device to perform single-sided or double-sided epitaxial growth, reasonably increasing the growth rate and achieving high output and low-cost production. In addition, the graphite substrate 19 and the carbonized adhesive layer 16 can be removed at low cost by simply performing combustion in an oxidation furnace or the like.
According to the embodiment, since van der Waals epitaxial growth of SiC is performed with the interposed graphene formed on the SiC monocrystalline substrate, and the SiC polycrystalline growth layer is formed thereon by the direct CVD method, substrate bonding is not required and defects caused by substrate bonding can be eliminated. In addition, since the epitaxial growth layer is formed with graphene interposed therebetween, the separation of the SiC monocrystalline substrate and the epitaxial growth layer becomes easy, and the process steps become simple. In addition, expensive processes such as ion implantation peeling method are not required.
According to the embodiment, after the SiC monocrystalline substrate is removed, each highly heat-resistant handling substrate is placed in a high-temperature LP-CVD apparatus, so that the SiC polycrystalline growth layer is directly grown on the epitaxial growth layer, thereby eliminating the need for the process of transporting an epitaxial growth layer with a film thickness of several μm from the handling substrate to the support substrate and the process of bonding to the support substrate as well as avoiding defects such as wrinkles, crystal transfer, and bubbles caused by film transport and bonding.
According to the embodiment, the graphene layer formed on the SiC monocrystalline substrate 11 is not transfer-printed, but epitaxial growth is performed directly thereon. This can avoid defects such as wrinkles and cracks caused by the transfer printing of graphene.
According to the embodiment, since the SiC monocrystalline substrate 11 is used as the substrate, hexagonal SiC with less deterioration in crystallinity can be obtained. In addition, although the SiC monocrystalline substrate 11 is difficult to remove by grinding or etching and is expensive, the obtained high-performance single crystal, that is, the SiC epitaxial growth layer 13, can be easily separated due to the van der Waals epitaxial growth using the interposed graphene layer 12 without removal by grinding or etching. Since the expensive SiC monocrystalline substrate 11 can be reused after separation, great advantages can be obtained in terms of cost.
Although the embodiments have been described above, they can also be implemented in other ways. For example, although illustration is omitted, a MOS capacitor can be manufactured using the SiC composite substrate 10. In the MOS capacitor, it can improve yield and reliability.
In addition, although illustration is omitted, a bipolar transistor can also be manufactured using the SiC composite substrate 10. In addition, the SiC composite substrate 10 of the embodiment can also be used for manufacturing SiC-pn diodes, SiCIGBTs, SiC complementary MOSFETs, and the like. The SiC composite substrate 10 can also be applied to other types of devices, such as light emitting diodes (LEDs), semiconductor optical amplifiers (SOAs) and the like.
The SiC epitaxial growth layer 13 may include at least one or more selected from the group consisting of Group IV element semiconductors, Group III-V compound semiconductors, and Group II-VI compound semiconductors.
In addition, the SiC composite substrate 10 and the SiC epitaxial growth layer 13 may be made of any material of 4H—SiC, 6H—SiC or 2H—SiC.
In addition, the SiC monocrystalline substrate 11 and the SiC epitaxial growth layer 13 may include at least one material selected from the group consisting of GaN, BN, AlN, Al2O3, Ga2O3, diamond, carbon, and graphite as a material system other than SiC.
The semiconductor element including the SiC composite substrate 10 may include any of GaN-based, AlN-based, and gallium oxide-based IGBTs, diodes, MOSFETs, and thyristors, in addition to the SiC-based.
The semiconductor device including the SiC composite substrate 10 may also have any structure of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.
According to the SiC composite substrate 10, as a substrate material, for example, a low-cost SiC polycrystalline growth layer 17 can be used instead of the high-cost SiC monocrystalline substrate 11.
A method of manufacturing a semiconductor substrate, comprising: forming a graphene layer 12 on a Si plane of a SiC monocrystalline substrate 11; forming a SiC epitaxial growth layer 13 on the graphene layer 12; forming a stress layer 14 on the SiC epitaxial growth layer 13; attaching a graphite substrate 19 as a temporary substrate onto the stress layer 14; peeling off the graphene layer 12 from the SiC epitaxial growth layer 13; forming a SiC polycrystalline growth layer 17 on a C plane of the SiC epitaxial growth layer 13 from which the graphene layer 12 has been peeled off, and removing the graphite substrate 19. At least one of the forming of the graphene layer 12 and the forming of the SiC epitaxial growth layer 13 is under an atmosphere including fluorine. By subjecting the SiC monocrystalline substrate 11 to thermal surface etching and thermal surface decomposition in the atmosphere containing fluorine, the graphene layer 12 having a high quality can be formed. In addition, since silicon carbide production is less likely to progress in an atmosphere containing fluorine, the SiC epitaxial growth layer 13 having a high quality can be formed.
In the method of manufacturing the semiconductor substrate according to Note 1, the forming of the graphene layer 12 on the Si plane of the SiC monocrystalline substrate includes forming the graphene layer 12 by a surface thermal decomposition of the Si plane of the SiC monocrystalline substrate 11 under the atmosphere including a silicon fluoride gas. The high-quality graphene layer 12 can be formed by surface thermal decomposing the Si plane, sublimating the silicon and crystallizing the carbon.
In the method of manufacturing the semiconductor substrate according to Note 2, the silicon fluoride gas includes at least one of silicon tetrafluoride, disilicon hexafluoride and trisilicon octafluoride. The silicon fluoride gas has high reactivity with silicon but low reactivity with graphene.
In the method of manufacturing the semiconductor substrate according to Note 2 or Note 3, prior to the forming of the graphene layer 12 by the surface thermal decomposition of the Si plane of the SiC monocrystalline substrate, further comprising a surface thermal etching of the Si plane of the SiC monocrystalline substrate 11 under the atmosphere including the silicon fluoride gas. By etching the silicon on the Si plane to produce a carbon-rich surface, the quality of the graphene layer 12 can be improved.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 4, upon the forming of the SiC epitaxial growth layer 13, the atmosphere includes a silicon fluoride gas and at least one of a hydrocarbon gas and a fluorocarbon gas, and the SiC epitaxial growth layer 13 is grown under the atmosphere. A material gas is supplied to the SiC epitaxial growth layer 13.
In the method of manufacturing the semiconductor substrate according to Note 5, the silicon fluoride gas includes at least one of silicon tetrafluoride, disilicon hexafluoride and trisilicon octafluoride. This can be set according to a uniform heating length of reactors 210 and 220, etc.
In the method of manufacturing the semiconductor substrate according to Note 5 or Note 6, the hydrocarbon gas includes at least one of methane, ethane, propane, ethylene and acetylene. Carbon can be supplied to the SiC epitaxial growth layer 13.
In the method of manufacturing the semiconductor substrate according to any one of Notes 5 to 7, the fluorocarbon gas includes at least one of tetrafluoromethane, hexafluoroethane, octafluoride propane, fluoroethylene and fluoroacetylene. Carbon can be supplied to the SiC epitaxial growth layer 13.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 8, the atmosphere including fluorine further includes an inert gas. The inert gas can be used as a carrier gas.
In the method of manufacturing the semiconductor substrate according to Note 9, the inert gas is an argon gas, which is easily available.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 10, the forming of the graphene layer 12 includes forming a graphene buffer layer or a single graphene layer 12, which is suitable for van der Waals epitaxial growth.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 11, the stress layer 14 includes a carbon film or a silicon nitride film. The stress layer 14 does not include metal, so that metal contamination does not occur.
In the method of manufacturing the semiconductor substrate according to Note 12, the carbon film includes a polycrystalline diamond film or a diamond-like carbon film, and is suitable for generating stress.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 13, the graphite substrate 19 of the temporary substrate includes graphite. The graphite substrate 19 can be removed by burning.
In the method of manufacturing the semiconductor substrate according to Note 14, the graphite substrate 19 of the temporary substrate has an outline size greater than that of the SiC monocrystalline substrate 11. When inserted into a wafer boat groove of a batch-type vertical CVD furnace and aligned, the wafer boat support marks can be positioned outside an effective substrate area.
In the method of manufacturing the semiconductor substrate according to Note 14 or Note 15, the graphite substrate 19 of the temporary substrate includes a glassy carbon film formed on a surface. The glassy carbon film has strong adhesion to the carbon adhesive of the adhesive layer 16.
In the method of manufacturing the semiconductor substrate according to any one of Notes 14 to 16, the removing of the graphite substrate 19 of the temporary substrate includes removing the graphite substrate 19 by burning in an air atmosphere or the like.
In the method of manufacturing the semiconductor substrate according to Note 14, the attaching of the graphite substrate 19, which is the temporary substrate, onto the stress layer 14 includes attaching the stress layer 14 to the graphite substrate 19 via an adhesive layer 16 made of a carbon adhesive. The carbon adhesive has strong adhesive ability, and by carbonizing it, it is possible to maintain its bonding power even at high temperatures.
In the method of manufacturing the semiconductor substrate according to Note 18, further comprising burning and removing the adhesive layer 16. For example, the adhesive layer 16 can be burned and removed together with the graphite substrate 19 in an air atmosphere.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 19, prior to the removing of the graphite substrate 19 of the temporary substrate, further comprising: grinding and removing the SiC polycrystalline growth layer 17 and the graphite substrate 19 protruded from an outer periphery of a composite including the graphite substrate 19, the stress layer 14 and the SiC epitaxial growth layer 13 during the forming of the SiC polycrystalline growth layer 17, thereby exposing an outer periphery of the graphite substrate 19. By exposing the graphite substrate 19, it becomes possible to burn it.
In the method of manufacturing the semiconductor substrate according to any one of Notes 1 to 20, further comprising forming a highly doped layer 13a having an impurity concentration greater than that of the SiC epitaxial growth layer 13 on the C plane of the SiC epitaxial growth layer 13 contacting the SiC polycrystalline growth layer 17. The highly doped layer 13a suppresses spread of the depletion layer in the SiC epitaxial growth layer 13, and also makes it possible to easily form an ohmic contact with the SiC polycrystalline growth layer 7 formed on the C plane of the SiC epitaxial growth layer 13.
A semiconductor manufacturing apparatus, comprising reaction furnaces 210, 220, configured for forming the graphene layer 12 on the SiC monocrystalline substrate 11 according to the method of manufacturing the semiconductor substrate according to any one of Notes 2 to 4. The graphene layer 12 can be formed in an atmosphere containing fluorine.
A semiconductor manufacturing apparatus, comprising reaction furnaces 210, 220, configured for forming the SiC epitaxial growth layer on the SiC monocrystalline substrate 11 via the graphene layer 12 according to the method of manufacturing the semiconductor substrate according to any one of Notes 5 to 8. The SiC epitaxial growth layer 13 can be formed in an atmosphere containing fluorine.
In the semiconductor manufacturing apparatus of Note 22 or 23, a plurality of the SiC monocrystalline substrates 11 are stackedly supported and storable in the reaction furnace 210. The SiC monocrystalline substrates 11 can be processed in a batch manner.
In the semiconductor manufacturing apparatus of Note 22 or 23, a plurality of the SiC monocrystalline substrates 11 can be placed on the table 225 of the reaction furnace 220 according to the modified example. The SiC monocrystalline substrates 11 can be processed in a semi-batch manner.
A semiconductor substrate, comprising: a SiC monocrystalline substrate 11; a graphene layer 12 disposed on a Si plane of the SiC monocrystalline substrate 11; an SiC epitaxial growth layer 13 disposed above the SiC monocrystalline substrate 11 by the graphene layer 12; and a stress layer 14 disposed on the Si plane of the SiC epitaxial growth layer 13, wherein the SiC epitaxial growth layer 13 includes fluorine. The SiC epitaxial growth layer 13 is formed with high quality in an atmosphere containing fluorine.
In the semiconductor substrate of Note 26, the stress layer 14 includes a carbon film or a silicon nitride film. Since the stress layer 14 does not include metal, it does not cause metal contamination.
The semiconductor device is a SiC composite substrate formed from the semiconductor substrate of Note 26 or Note 27, in which the SiC polycrystalline growth layer is formed on the Si plane of the SiC epitaxial growth layer, and a semiconductor element structure is formed on the C plane of the SiC epitaxial growth surface of the SiC composite substrate. By using the low-cost, high-quality SiC composite substrate 10, a low-cost, high-quality semiconductor device can be provided.
In the semiconductor device of Note 28, the semiconductor element includes at least one of a SiC Schottky barrier diode, a SiC-MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor and a SiC insulated gate bipolar transistor. Various useful SiC-based semiconductor elements can be provided.
As described above, several embodiments have been described, but the descriptions and drawings that form part of the disclosure are illustrative and should not be understood as limiting. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure. Thus, the embodiments include various embodiments not described here.
This disclosure can be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of applications, such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert power generated by solar cells, wind power generators, and other power generation devices (especially private power generation devices) into commercial power sources.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-111051 | Jul 2023 | JP | national |
