Patent Application
20240222184
The present disclosure generally relates to semiconductor device assemblies, and more particularly relates to a semiconductor substrate with a sacrificial annulus.
Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry with a high density of very small components. Typically, dies include an array of very small bond pads electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. After dies are formed, they are “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines, and ground lines. Conventional processes for packaging dies include electrically coupling the bond pads on the dies to an array of leads, ball pads, or other types of electrical terminals and encapsulating the dies to protect them from environmental factors (e.g., moisture, particulates, static electricity, and physical impact).
Semiconductor devices are integrated into many devices to implement memory cells, processor circuits, imager devices, and other functional features. As more applications for semiconductor devices are discovered, designers are tasked with creating improved devices that can perform a greater number of operations per second, store greater amounts of data, or operate with a higher level of security. To accomplish this task, designers continue to develop new techniques to increase the number of circuit elements on a semiconductor device without simultaneously increasing the size of the device. This development, however, may not be sustainable due to various challenges that arise from designing semiconductor devices with high circuit density. Thus, additional techniques may be required to continue the growth in capability of semiconductor devices.
One such technique is the implementation of multiple circuit components within a single package. For example, stacked semiconductor devices enable multiple semiconductor dies to be stacked on top of one another to increase the number of circuit elements within a package without increasing its footprint. To reduce the thickness of packaged semiconductor devices, material is removed at the back side of the semiconductor dies to thin the dies. Due to curvature at the edge of the die substrate, die thinning may produce a sharp knife edge around the die. This sharp knife edge may be increasingly susceptible to cracks, which can cause failure in the semiconductor die and reduce yield. Various techniques have been developed to reduce the presence of a sharp knife edge after die thinning. One such technique is shown by way of example in
As illustrated in
While the mechanical edge trimming of the edge 110 may reduce the presence of a sharp knife edge after die trimming, trimming the edge 110 of the substrate 102 may cause particulates from the substrate 102 to fall onto the front side of the semiconductor dies 104 at which circuitry is disposed. Many of these particulates may be difficult to remove even with scanning electron microscope (SEM) level cleaning. Thus, these particulates may remain at the front side of the semiconductor dies 104 even after packaging. In some cases, these particulates may cause failures in operation of the semiconductor dies 104. Moreover, particulates at the front side of the semiconductor dies 104 may limit the robustness of connections formed thereat, for example, interconnects between semiconductor dies in a stacked die package. Accordingly, utilizing mechanical edge trimming to limit the presence of sharp knife edges on a die substrate may inhibit the performance of the semiconductor dies.
To address these drawbacks and others, various embodiments of the present application provide semiconductor device assemblies that implement a semiconductor substrate with an annulus of sacrificial material. The semiconductor substrate includes a center portion and a peripheral portion. The annulus of sacrificial material is disposed at a front side of the semiconductor substrate, and it extends at least partially through the semiconductor substrate. The annulus of sacrificial material separates the center portion of the substrate from the peripheral portion of the substrate at the front side. The semiconductor substrate can be thinned to expose the annulus of sacrificial material and disconnect the peripheral portion from the center portion. In doing so, the thinned substrate may have a planar substrate edge void of sharp edges, thereby increasing its mechanical robustness. An example semiconductor device assembly is shown in
Once the circuitry and the annulus of sacrificial material 208 have been disposed on the substrate 202, the substrate 202 may be adhered (e.g., through an adhesive 212) to a carrier substrate 214 (e.g., wafer) to support the semiconductor dies 204 during processing. The substrate 202 may be adhered to the carrier substrate 214 in a face-down position such that the front side of the substrate 202 at which circuitry is disposed is adhered to the carrier substrate 214 and a back side of the substrate 202 is exposed. In this way, the substrate 202 may be thinned at the back side. The resulting semiconductor device assembly is shown by way of example in
As illustrated in
As illustrated in
Given that the annulus of sacrificial material 208 separates the center portion 206 and the peripheral portion 210 of the substrate 202, removing the annulus of sacrificial material 208 may disconnect the peripheral portion 210 of the substrate 202 from the center portion 206 of the substrate 202. Given that, in the illustrated example, the center portion 206 is adhered to the carrier substrate 214 and the peripheral portion 210 is not, the peripheral portion 210 may be removed from the semiconductor device assembly when the annulus of sacrificial material 208 is removed. As illustrated in
In contrast to the semiconductor device assembly illustrated in
In some implementations, the annulus of sacrificial material 208 may extend only partially through the substrate 202. For example, the annulus of sacrificial material 208 may extend far enough into the substrate such that it is exposed when the substrate 202 is thinned at the back side (e.g., the annulus of sacrificial material may extend less than 25 microns, 30 microns, 35 microns, 40 microns, 50 microns, 75 microns, 100 microns, or the like). In other implementations, the annulus of sacrificial material 208 may extend entirely through the substrate 202 to the back side. The annulus of sacrificial material 208 or the two or more portions of sacrificial material 302 may have any thickness. The annulus of sacrificial material 208 or the two or more portions of sacrificial material 302 may have a thickness based on the depth to which the sacrificial material is deposited. For example, the sacrificial material may be deposited with an aspect ratio of 2, 5, 10, 15, or the like. Accordingly, the thickness of the annulus of sacrificial material 208 or the two or more portions of sacrificial material 302 may have a thickness of less than 2 microns, less than 5 microns, less than 10 microns, less than 20 microns, less than 25 microns, or the like.
In aspects, the substrate 202 may include two or more portions of sacrificial material 302 that extend from the annulus of sacrificial material 208 to the periphery of the substrate 202. The two or more portions of sacrificial material 302 may be disposed at the front side of the substrate 202 to a same or different depth than the annulus of sacrificial material 208. The two or more portions of sacrificial material 302 may include a sacrificial material that is the same as or different from the annulus of sacrificial material 208. The two or more portions of sacrificial material 302 may partition the peripheral portion 210 at the front side. In some implementations, the two or more portions of sacrificial material 302 may be distributed equally about the periphery of the substrate 202 to create equally sized partitions. For example, as illustrated, the two or more portions of sacrificial material 302 are placed at opposite sides of the substrate 202 to divide the peripheral portion 210 into two equally sized partitions. In other implementations, any number of portions (e.g., three, four, five, ten, or the like) of sacrificial material may be disposed at the front surface of the substrate 202.
When the substrate 202 is thinned, the two or more portions of sacrificial material 208 may be exposed at the back side of the substrate 202. In this way, the two or more portions of sacrificial material 208 may be removed through any of the techniques discussed with respect to the annulus of sacrificial material 208. In some cases, the two or more portions of sacrificial material 302 may be removed in conjunction with removing the annulus of sacrificial material 208. Given that the two or more portions of sacrificial material 302 may partition the peripheral portion 210, removing the two or more portions of sacrificial material 302 may disconnect the partitions of the peripheral portion 210 from one another. As a result, the various partitions of the peripheral portion 210 may be disconnected from the center portion 206 of the substrate 202 and removed individually.
As used herein, the annulus of sacrificial material may refer to the annulus of sacrificial material 208 alone or to the annulus of sacrificial material 208 and the two or more portions of sacrificial material 302 in combination. Thus, although described separately with respect to
This disclosure now turns to a series of steps for fabricating semiconductor device assemblies in accordance with an embodiment of the present technology. Specifically,
Beginning with
The substrate 202 may further include circuitry to implement one or more semiconductor dies 204 at the substrate 202 (e.g., at the center portion 206). The circuitry may be disposed on the substrate 202 through one or more steps of removing and depositing material. Materials can be deposited and removed through any of the processes discussed above with respect to the annulus of sacrificial material 208. In some implementations, the annulus of sacrificial material 208 and the circuitry may be disposed at the substrate 202 in conjunction with one another (e.g., in a same process step). In this way, creating the annulus of sacrificial material 208 may not add process steps to semiconductor device fabrication. As illustrated, the annulus of sacrificial material 208 may surround the semiconductor dies 204 at the center portion 206 of the substrate 202.
Turning to
Turning next to
Turning next to
While the steps illustrated in
Turning next to
Turning next to
Interconnects 1106 may be formed between contact pads at the semiconductor dies 1102 and contact pads at the substrate 1104 to enable electrical signals to pass between the semiconductor dies 1102 and the substrate 1104. The semiconductor dies 1102 may include traces, lines, vias, or other electrical connection structures that connect circuitry at the semiconductor dies 1102 to the contact pads. As illustrated, multiple semiconductor dies 1102 may be stacked in a single package, and interconnects 1106 may be formed between the stacked semiconductor dies 1102. The semiconductor dies 1102 may include one or more through-silicon vias (TSVs) to enable electrical signals to be passed between the stacked semiconductor dies 1102 exclusive of the substrate 1104 or other circuitry.
The substrate 1104 can further include package-level contact pads that provide external connectivity (e.g., via solder balls) to the semiconductor dies 1102 (e.g., power, ground, and I/O signals) through traces, lines, vias, and other electrical connection structures in the substrate 1104 that electrically connect the package-level contact pads to contact pads at an upper surface of the substrate 1104. An underfill material 1108 (e.g., capillary underfill) can be provided between the semiconductor dies 1102 and the substrate 1104 to provide electrical insulation to the interconnects 1106 and structurally support the semiconductor dies 1102. The assembly 1100 can further include an encapsulant material 1110 (e.g., mold resin compound or the like) that at least partially encapsulates the semiconductor dies 1102 and the substrate 1104 to prevent electrical contact therewith and provide mechanical strength and protection to the assembly.
Although in the foregoing example embodiment semiconductor device assemblies have been illustrated and described as including a particular configuration of semiconductor dies, in other embodiments, assemblies can be provided with different configurations of semiconductor dies. For example, the semiconductor device assemblies illustrated in any of the foregoing examples could be implemented with, e.g., a vertical stack of semiconductor dies, a plurality of semiconductor dies, a single semiconductor die, mutatis mutandis.
In accordance with one aspect of the present disclosure, the semiconductor devices illustrated in the assemblies of
Any one of the semiconductor devices and semiconductor device assemblies described above with reference to
At 1302, a semiconductor substrate 202 (e.g., wafer) is provided that includes an annulus of sacrificial material 208 disposed at a front side of the semiconductor substrate 202 and extending at least partially into the semiconductor substrate 202. In some implementations, the annulus of sacrificial material 208 may be pinched off such that a vacancy 802 extends through the annulus of sacrificial material 208. The annulus of sacrificial material 208 may be implemented by removing (e.g., etching) material from the front side of the substrate 202 to create an opening and disposing sacrificial material at the opening. At 1304, circuitry is disposed at the front side of the semiconductor substrate 202 to implement a plurality of semiconductor dies 204. In some implementations, the circuitry may be disposed in conjunction with disposing the annulus of sacrificial material 208 at the front side. In doing so, the annulus of sacrificial material 208 may be created without additional processing steps to fabricate a semiconductor device.
At 1306, the semiconductor substrate 202 is thinned at a back side opposite the front side effective to expose the annulus of sacrificial material 208 and separate a center portion 206 of the semiconductor substrate 202 from a peripheral portion 210 of the semiconductor substrate 202 with the annulus of sacrificial material 208. At 1308, the peripheral portion 210 is disconnected from the center portion 206 effective to remove the peripheral portion 210. In some implementations, removing the peripheral portion may include dissolving the annulus of sacrificial material 208 that separates the center portion 206 and the peripheral portion 210 using a solvent. In aspects, the solvent may include a solvent or slurry used for CMP and dissolving the annulus of sacrificial material 208 may be performed in conjunction with planarizing the back side of the substrate 202 (e.g., using CMP). In some implementations, the annulus of sacrificial material 208 includes a vacancy 802 and disconnecting the peripheral portion 210 from the center portion 206 effective to remove the peripheral portion 210 includes thinning the semiconductor substrate 202 at the back side to the vacancy 802 such that a portion of the sacrificial material 902 remains at an edge of the center portion 206 of the substrate 202. In some cases, dicing the plurality of semiconductor dies 204 is effective to remove the portion of the sacrificial material 902 from the plurality of semiconductor dies 204. In aspects, the method 1300 may limit the occurrence of sharp knife edges on a substrate 202 without mechanically trimming the edge of the substrate 202 at the front side.
Specific details of several embodiments of semiconductor devices, and associated systems and methods, are described above. Depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated, die-level substrate. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.
The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a printed circuit board (PCB) or wafer-level substrate, a die-level substrate, or another die for die-stacking or three-dimensional interconnect (3DI) applications.
The devices discussed herein, including a memory device, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.
The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”
As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “above,” and “below” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, and left/right can be interchanged depending on the orientation.
From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
The present application claims priority to U.S. Provisional Patent Application No. 63/435,772, filed Dec. 28, 2022, the disclosure of which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63435772 | Dec 2022 | US |
