Patent Application
20240178163
Semiconductor devices including active and/or passive components may be manufactured into round wafers sliced from elongated cylinder-shaped single crystals of semiconductor elements or compounds. The diameter of these solid-state wafers may reach up 12 inches or more. Individual semiconductor dies are typically singulated from a round wafer by sawing streets in X- and Y-directions through the wafer in order to create rectangularly shaped discrete pieces from the wafers.
Each semiconductor die includes at least one active or passive component and die pads serving to facilitate electric connections to the component(s) of the semiconductor die. Semiconductor dies include many large families of electronic components; examples include active devices such as diodes and transistors like field-effeet transistors, passive devices such as resistors and capacitors, and integrated circuits, which can include far more than a million active and passive components.
After singulation, one or more semiconductor dies are attached to a discrete supporting substrate such as a metal leadframe or a rigid multi-level substrate laminated from a plurality of metallic and insulating layers. The conductive traces of the lead frames and substrates are connected to the die pads, typically using bonding wires or metal bumps such as solder bumps.
The assembled semiconductor dies, lead frames and/or substrates may be encapsulated to form discrete robust packages, which frequently employ hardened polymeric compounds and are formed by techniques such as transfer molding. The assembly and packaging processes are performed either on an individual basis or as part of batch processes including a strip or array of semiconductor dies on a corresponding strip or array of lead frames and/or through a single loading of a mold press.
Semiconductor technology continues trends towards miniaturization, integration, and speed. Integration of antennas and functional circuitry within a common package are sometimes referred to as antenna-on-package (AOP) or antenna-in-package (AIP). Radio frequency (RF) integrated circuits can be packaged so that rather than transmitting RF signals through contacts, such as balls or pins, to an antenna module, an antenna is provided on the top surface of package itself. This is referred as an AOP configuration. The AOP device can include a number of antennas coupled to a semiconductor or integrated circuit (IC) die, such as one or more transmitter antennas and/or receiver antennas. An AIP device is a semiconductor package arrangement wherein the antenna is integrated into the package along with a semiconductor or IC die, such as an RF IC die, to provide a wireless device. In this configuration, the antenna is not a separate component placed within the wireless device but is instead directly integrated into the package along with IC die. This approach is sometimes referred to as a discrete antenna approach. Other typical AIP components include RF/millimeter (mm) wave building blocks, an analog baseband signal chain for transmitters and receivers, as well as a customer-programmable microcontroller unit (MCU) and a digital signal processor (DSP). Packages with integrated antennas may be scaled to incorporate a variety of different wireless sensing and/or transmission standards. However, advantages of packages with integrated antennas are most apparent for applications requiring relatively small antennas, such as Wi-Fi, near-field communication (NFC), and millimeter wave (mmWave) applications.
Traditionally, mmWave antennas have been designed on a printed circuit board (PCB) using substrates with advanced materials that support efficiency at high-frequencies, such as polytetrafluoroethylene based-substrates, to deliver high-accuracy sensing. Although effective, such system designs require RF expertise to design and manufacture an antenna to work alongside the sensor. Packages with integrated antennas may reduce system complexity and manufacturing costs by eliminating the need for standalone antennas. Such sensing systems may be utilized for robotics, industrial 3D sensing, and automotive applications including driver-assist and self-driving systems.
mmWave systems generally operate in the spectrum between 24 GHz-300 GHz. In different applications, mmWave systems may be utilized for data transmission, such as with cellular networks, or in radar sensing technology for detection of objects. Due to short wavelengths of mmWave signals, system components, such as antennas, may be of relatively small size.
In an arrangement, a semiconductor package comprises a semiconductor die having a top surface, a passivation layer over the top surface, a first metal layer on the first passivation layer, an antenna formed in the first metal layer and offset from the semiconductor die, the antenna having a slot bow-tie configuration, a transmission line formed in the first metal layer, the transmission line coupling the semiconductor die to the antenna, and an insulating material separating the first metal layer from a second metal layer, the second metal layer configured to function as a ground reflector for the antenna. The second metal layer extends below the antenna and the semiconductor die.
The semiconductor package may further comprise a conductive pad on the top surface of the semiconductor die, and an opening in the passivation layer to expose the conductive pad, wherein the transmission line in the first metal layer in contact with the conductive pad through the first opening.
The transmission line may be a conductor-backed coplanar waveguide. The transmission line may comprise three parallel strips in the first metal layer, wherein the three parallel strips have a ground-signal-ground configuration.
The semiconductor package may further comprise an impedance transformer formed in the first metal layer, wherein the impedance transformer is coupled between an antenna feed and the transmission line. The transmission line may have a 50Ω impedance, and the impedance transformer may have a 75Ω impedance.
The antenna may be configured to operate in a frequency band having a millimeter wavelength. The antenna may be configured in the first metal layer to provide direct air radiation.
The antenna may comprise a metal plane having two triangular openings, the openings each having a vertex positioned near an antenna feed and a base side opposite the vertex, and wherein the distance between the base sides determines a resonant frequency of the antenna.
The semiconductor package may further comprise additional layers. A first dielectric layer may cover the first metal layer, a third metal layer may cover the first dielectric layer, and a first via in the first dielectric layer may couple the first metal layer to the third metal layer. A second dielectric layer may cover the second metal layer, a fourth metal layer may cover the second dielectric layer, and a second via in the second dielectric layer may couple the second metal layer to the fourth metal layer.
The semiconductor package may further comprise a first solder mask layer above the first metal layer, and a second solder mask layer below the second metal layer.
In another arrangement, an integrated circuit (IC), comprises an embedded die structure, including an organic panel frame, including an opening, a semiconductor die positioned within the opening, and a filling material that embeds the semiconductor die in the opening of the organic panel frame. A first redistribution layer (RDL) structure is positioned above the semiconductor die and has a conductive structure electrically connected to a contact on the semiconductor die. An antenna is formed in the first RDL structure and is offset from the semiconductor die. The antenna has a slot bow-tie configuration. A second RDL structure is positioned below the semiconductor die as a ground reflector for the antenna.
The IC may further comprise a transmission line formed in the first RDL structure. The transmission line couples the semiconductor die to the antenna. The transmission line may be a waveguide in the first RDL structure. The waveguide may have three parallel strips in the first metal layer, wherein the three parallel strips have a ground-signal-ground configuration.
The second RDL structure may extend below the antenna and the semiconductor die. The antenna may be configured to operate in a frequency band having a millimeter wavelength, and the antenna may be configured in the first RDL structure to provide direct air radiation.
The IC may further comprise an impedance transformer formed in the first RDL structure, wherein the impedance transformer is coupled between an antenna feed and the transmission line. The transmission line may have a 50Ω impedance, and the impedance transformer may have a 75Ω impedance.
The IC may further comprise a first dielectric layer covering the first RDL structure, a third RDL structure covering the first dielectric layer, and a first via in the first dielectric layer, the first via coupling the first RDL structure to the third RDL structure. A second dielectric layer may cover the second RDL structure, a fourth RDL structure may cover the second RDL structure, and a second via in the second dielectric layer may couple the second RDL structure to the fourth RDL structure.
Having thus described the invention in general terms, reference will now be made to the accompanying drawings, wherein:
The present disclosure is described with reference to the attached figures. The figures are not drawn to scale, and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts, unless otherwise indicated. The figures are not necessarily drawn to scale. In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including,” “includes,” “having,” “has,” “with,” or variants thereof are intended to be inclusive in a manner similar to the term “comprising,” and thus should be interpreted to mean “including, but not limited to . . . ” Also, the terms “coupled,” “couple,” and/or or “couples” is/are intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is electrically coupled with a second device that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and/or connections. Elements that are electrically connected with intervening wires or other conductors are considered to be coupled. Terms such as “top,” “bottom,” “front,” “back,” “over,” “above,” “under,” “below,” and such, may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element but should be used to provide spatial relationship between structures or elements.
The term “semiconductor die” is used herein. A semiconductor device can be a discrete semiconductor device such as a bipolar transistor, a few discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die can be an integrated circuit with multiple semiconductor devices such as the multiple capacitors in an A/D converter. The semiconductor device can include passive devices such as resistors, inductors, filters, sensors, or active devices such as transistors. The semiconductor device can be an integrated circuit with hundreds or thousands of transistors coupled to form a functional circuit, for example a microprocessor or memory device. The semiconductor device may also be referred to herein as a semiconductor device or an integrated circuit (IC) die.
The term “semiconductor package” is used herein. A semiconductor package has at least one semiconductor die electrically coupled to terminals and has a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies can be packaged together. For example, a power metal oxide semiconductor (MOS) field effeet transistor (FET) semiconductor device and a second semiconductor device (such as a gate driver die, or a controller die) can be packaged together to from a single packaged electronic device. Additional components such as passive components, such as capacitors, resistors, and inductors or coils, can be included in the packaged electronic device. The semiconductor die is mounted with a package substrate that provides conductive leads. A portion of the conductive leads form the terminals for the packaged device. In wire bonded integrated circuit packages, bond wires couple conductive leads of a package substrate to bond pads on the semiconductor die. The semiconductor die can be mounted to the package substrate with a device side surface facing away from the substrate and a backside surface facing and mounted to a die pad of the package substrate. The semiconductor package can have a package body formed by a thermoset epoxy resin mold compound in a molding process, or by the use of epoxy, plastics, or resins that are liquid at room temperature and are subsequently cured. The package body may provide a hermetic package for the packaged device. The package body may be formed in a mold using an encapsulation process, however, a portion of the leads of the package substrate are not covered during encapsulation, these exposed lead portions form the terminals for the semiconductor package. The semiconductor package may also be referred to as a “integrated circuit package,” a “microelectronic device package,” or a “semiconductor device package.”
The term “redistribution layer (RDL)” is used herein. The RDL structure is a conductive structure that may be electrically connected to a semiconductor die or other components. A packaged electronic device may include elements, such as antennas, transmission lines, waveguides, and/or impedance transformers, that are formed in the RDL structure. In one example, a packaged electronic device includes a slot bow-tie antenna formed in an RDL layer. The slot bow-tie antenna is coupled to a semiconductor die circuit by a transmission line and impedance transformer that are also formed in the RDL structure.
The term “slot bow-tie antenna” is sued herein. A slot antenna consists of a metal surface, such as flat metal plate, with one or more holes cut out of the surface. When the metal plate is driven by an RF current, the slot radiates electromagnetic waves. The radiation pattern of the slot antenna is omni-directional similar to a dipole antenna. A slot bow-tie antenna, such as the ones described herein, is a slot antenna that has slots formed in the shape of a bow tie, which generally has two mirror-image triangle shapes. In some arrangements, the bow-tie shape may also be referred to as a butterfly-shaped antenna.
The term “ground reflector” is used herein. A ground reflector is a device that reflects electromagnetic waves from an antenna. The ground reflector can be a standalone device for redirecting RF energy or can be integrated as part of an antenna assembly. The ground reflector described herein serves to modify the radiation pattern of the slot bow-tie antenna and to increase gain in the direction opposite the ground plane.
The term “coplanar waveguide” is used herein. A coplanar waveguide is a type of electrical planar transmission line that can be used to convey microwave-frequency signals. Coplanar waveguide transmission lines are built into monolithic microwave integrated circuits. The coplanar waveguide consists of a single conducting track or strip on a dielectric substrate and a pair of return conducting tracks or strips, one to either side of the conducting track. All three conductors are on the same side of the substrate and, therefore, are coplanar. The return conductors are separated from the central conducting track by a small gap, which has an unvarying width along the length of the line. On the sides away from the central conductor, the return conductors can extend to an indefinite distance so that each is notionally a semi-infinite plane. In some arrangements, the coplanar waveguide is a conductor-backed coplanar waveguide, which may also be known as coplanar waveguide with ground. The conductor-backed coplanar waveguide variant has a ground plane covering the entire back-face of the substrate. The ground-plane serves as a third return conductor.
Semiconductor package 101 provides system-in-package (SiP) embedded die technology with antenna-on-package integration, which enables unique package-top-radiated AOP structure with direct air radiation patterns. Arrangements disclosed herein present an optimized slot bow-tie antenna operating in the 140-220 GHz (WR5) frequency band with direct air radiation and substrate-enhanced gain using SiP embedded die technology.
In the illustrated configuration, ground RDL 104 extends beyond one side of semiconductor die and has a width Wgnd and a length Lgnd. In one arrangement, Wgnd is 2000 um, and Lgnd is 1425 um. A substrate, which includes semiconductor die 102, separates ground RDL 104 from antenna RDL 103. The shape of the slot bow-tie antenna 105 is patterned as RDL 103 on the top surface of the substrate. The outside dimensions of slot bow-tie antenna 105 are a generally rectangular shape having width Wout and length Lout. In one arrangement, Wout is 1625 um, and Lout is 1000 um. Antenna 105 has two mirror-image triangular openings or slots 301, 302 that have a base of length Lbase and two sides of length Lside. The base of the slots 301, 302 is spaced a distance Dbase away from the antenna feed channel. The openings 301, 302 have an isosceles, equilateral, or scalene triangular shape. In one arrangement, directed toward the 140-220 GHz frequency operating range (WR5), Lbase is 600 um, Lside is 623.87 um, and Dbase is 560 um.
Coplanar waveguide transmission line structure 106 connects semiconductor die 102 to slot bow-tie antenna structure 105. Feed strip 201 has a width Wfeed and is spaced apart from ground strips 202, 203 by a distance Dgnd. The width of the ground strips 202, 203 may be the same as the width Wfeed of the feed strip 201 or may be another width. Transmission line structure 106 has a length Lfeed between semiconductor die 102 and the edge 303 of antenna structure 105. A quarter-wave transformer 304 is used to compensate for impedance requirements at antenna feed 305. For example, the quarter-wave transformer may have an impedance of 75Ω. The quarter-wave transformer 304 includes a strip of width Wqtr that is spaced apart from slot bow-tie antenna structure 105 by a distance Dqtr. Quarter-wave transformer 304 has a length Lqtr. The antenna feed 305 has a width Want at its widest point of attachment to slot bow-tie antenna structure 105 and has a length of Lant. In one arrangement, Wfeed is 40 um, Dfeed is 20 um, Wqtr is 20 um, Dqtr is 30 um, and Lqtr is 475 um. Antenna feed 305 may have dimensions Want of 100 um and Lant of 50 um.
The slot bow-tie antenna is known to yield wide bandwidth and high efficiency. The linearly-polarized antenna radiation along the slot bow-tie antenna width is generated by exciting the two respective apertures 301, 302. The resonant frequency of the slot bow-tie antenna 105 may be adjusted by changing the width Wsbt. For example, increasing slot bow-tie width Wsbt increases the slot resonant length resulting in a longer current path and a lower resonant frequency. The length of the aperture base Lbase can be tuned to input matching to a desired frequency.
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An insulating dielectric layer 909 is formed on top of RLD 907. Dielectric layer 909 separates RDL 907 from conductive layer 910 that is formed on top of layer 909. Conductive layer 910 is electrically coupled to RDL 907 by one or more vias 911 that may be drilled through dielectric layer 909. A thin metal contact 912 is formed on conductive layer 910 and may function as an under bump material (UMB) for mounting contacts to external devices. A solder mask 913 or other protective material is deposited on dielectric layer 909 and conductive layer 910 so that only contact 912 is exposed on the top surface of device 900.
Similarly, insulating dielectric layer 914 is formed on the bottom of RLD 908. Dielectric layer 914 separates RDL 908 from a conductive layer 915 that is formed on the bottom of layer 914. Conductive layer 915 is electrically coupled to RDL 908 by one or more vias 916 that may be drilled through dielectric layer 914. A thin metal contact 916 is formed on conductive layer 915 and may function as an under bump material for mounting contacts to external devices. A solder mask 917 or other protective material is deposited on dielectric layer 914 and conductive layer 915 so that only contact 916 is exposed on the bottom surface of device 900.
The conductive vias or PTH 1007 have a width T7 of 105-150 um and are placed a distance T8 of 150-200 um away from the edge of semiconductor die 1001. The top and bottom RDL layers are spaced a distance T9 from the edges 1008 of package 1000.
While various examples of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed examples can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims. Thus, the breadth and scope of the present invention should not be limited by any of the examples described above. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.
