Patent Application
20250212317
At least one embodiment pertains to printed circuit board (PCB) fabrication. For example, at least one embodiment pertains to technology for implementing slot grounds for improved signal integrity.
A printed circuit board (PCB) can be used to connect electronic components. A PCB can include multiple conductive layers. The conductive layers can include at least a top layer and a bottom layer. The conductive layers can further include one or more layers disposed between the top layer and the bottom layer. In such PCBs, the top layer and the bottom layer can be referred to as “exterior layers” and each additional layer can be referred to as an “interior layer.” A PCB can include one or more vias that enable respective interconnections between conductive traces on the different layers. More particularly, a via can be formed by forming a hole that traverses through at least two adjacent conductive layers, and plating the hole with a conductive material that forms an electrical connection so that the conductive traces on different layers are electrically connected.
Crosstalk is a phenomenon where electrical signals on one trace and/or via unintentionally interfere with or affect the signals on nearby traces and/or vias. This interference can lead to signal degradation, data errors, or other performance issues in the associated electronic circuits. Crosstalk occurs due to electromagnetic coupling between traces and/or vias in close proximity, and it can be particularly problematic at high data transmission frequencies or in densely populated PCBs.
Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:
As described above, A PCB can further include at least one via. A via is a plated hole that passes through multiple layers of a PCB to make electrical connections between different layers of the PCB.
One example of a via is a through-hole via. A through-hole via extends through all layers of a PCB, connecting the top and bottom layers, as well as any interior layers. Accordingly, through-hole vias are visible from both sides of the PCB. Another example of a via is a blind via. A blind via refers to a via that connects an exterior layer of a PCB (e.g., the top layer or the bottom layer) to one or more interiors layer of the PCB. Accordingly, blind vias are only visible from one side of the PCB. A further example of a via is a buried via. A buried via refers to a via formed between two interior layers of a PCB. Accordingly, a buried via is not visible from either side of the PCB.
As described above, during transmission of signals across conductive signal traces on a PCB, crosstalk can occur. Crosstalk refers to undesired electromagnetic interference or coupling between signal traces and/or vias on the PCB. This interference can occur when signals on one trace and/or via affect or “talk” to nearby traces and/or vias, causing unintended signal distortion or noise. Crosstalk can be particularly problematic in high-speed digital circuits and analog circuits where signal integrity is critical. Crosstalk can cause various issues, including distorting signal shapes, affecting the timing of signals, and/or introducing bit errors or data corruption.
To improve signal integrity, and mitigate crosstalk on a PCB, the PCB can include ground planes that act as shields helping to block or reduce the electromagnetic fields that cause crosstalk. Some common solutions that help mitigate crosstalk with respect to signal vias include forming multiple ground vias around each of the signal vias. The multiple ground vias are electrically coupled to the ground plane and extend between multiple layers of the PCB to form a shield around at least part of the signal via. However, this arrangement of ground vias does not provide sufficient shielding for especially high transmission rates, such as for high-speed differential pair or single-end signals. For example, ground vias may not provide sufficient ground shielding of a signal via transmitting 212 Gbps per differential pair or 45 Gbps per lane single-end signals. Additionally, ground vias often extend through all layers of a PCB, limiting a power plane of the PCB and limiting the locations at which signal traces can fan out from the signal via.
Other solutions that help mitigate crosstalk include a coaxial via design where a ground shield is formed around the signal via. The ground shield is coaxial with the signal via and extends from the bottom of the signal via to the top of the signal via. Although the coaxial ground arrangement provides good shielding, a signal trace electrically coupled to the signal via cannot fan out (e.g., extend from the signal via) at just any layer of the PCB; the signal trace(s) can only couple to the signal via at the top or bottom of the signal via. Moreover, this coaxial via design is expensive to implement in a PCB.
Aspects of the present disclosure can address the deficiencies above and other challenges by implementing slot grounds on PCBs for improved signal integrity. A PCB as described herein can include a stack of layers. The stack of layers can include a first signal trace on a first layer and a second signal trace on a second layer. The signal traces can be electrically coupled by a signal via extending between the two layers. To reduce signal interference with respect to the signal via, the PCB can include a slot ground that provides ground shielding for the signal via. The slot ground can be made up of a slot formed in the PCB at least partially surrounding the signal via. In some embodiments, the slot substantially forms a C-shaped profile. The signal traces may couple to the signal via through the open portion of the C-shaped profile, allowing the signal traces to couple to the signal via at any layer of the PCB. The slot ground further includes metal plating on the walls of the slot. The metal plating may be electrically coupled to a ground plane of the PCB. In some embodiments, the ground slot includes a resin (e.g., and/or ink) at least partially filling the slot so that the ground slot does not form a void in the PCB.
In some embodiments, the slot ground at least partially surrounds a single signal via, such as for the transmission of single-lane signals. However, in some embodiments, the slot ground at least partially surrounds two signal vias, such as for the transmission of a differential pair signal. Two signals can be accommodated within the slot ground by elongating the profile of the slot (e.g., by lengthening the C-shaped profile). In some embodiments, where the slot ground at least partially surrounds a single signal via, the central axis of the slot is substantially coaxial with a central axis of the signal via. For example, the center axis of the C-shaped profile of the slot may be coaxial with the center axis of the signal via.
A slot ground may be formed in a PCB using methods described herein. In some embodiments, multiple layers (e.g., conductive and/or non-conductive) layers are laminated together to form a multi-layer structure. One or more holes may be drilled through the laminated layers to form one or more vias. In some embodiments, the holes are drilled completely through all the layers, such as to form a through-hole via. In some embodiments, the holes are drilled through only some of the layers, such as to form a blind via. The one or more vias may be signal vias for transmitting an electrical signal between signal traces that are located on different layers of the PCB. To form a slot ground, multiple holes may be drilled around a signal via through at least some of the laminated layers. The multiple holes may be drilled adjacent to one another so that a slot is formed that substantially surrounds the signal via. The slot may have a C-shaped profile. In some embodiments, the holes are drilled to a first depth using a mechanical drilling tool (e.g., such as a drill bit, etc.) and are finish-drilled to a deeper second depth using a laser drilling tool. Once the signal via and slot are formed by drilling, the interior walls may be plated with a conductive material. The slot and/or the signal via hole may be filled with a resin (e.g., an ink resin, etc.) to eliminate voids in the signal via hole and/or in the slot.
Advantages of the present disclosure include, for example, improved signal integrity by reducing crosstalk between signal traces and/or signal vias within close proximity. A slot ground provides improved ground shielding of a signal via for high rates of data transfer (e.g., such as for 212 Gbps per differential pair or 45 Gbps per lane single-end signals) when compared to current solutions. Additionally, the slot ground described herein allow for signal traces to connect to a signal via at any layer of the PCB, which is an improvement in versatility compared to other techniques currently used. Moreover, the slot ground described herein can be made with a reduced cost compared to conventional solutions.
In some embodiments, the inner walls of the slot ground 110A are plated with a metal plating. The inner walls of the signal via 106 may be plated with the same metal plating and may be plated during the same plating operation. The metal plating can include a metal such as copper, tin, lead, gold, nickel, silver, or one or more metal alloys, etc. In some embodiments, the metal plating of slot ground 110A is electrically coupled to a ground plane of a PCB. By electrically coupling the metal plating of slot ground 110A with a ground plane, the slot ground 110A can reduce signal interference with respect to the signal via 106. For example, the slot ground 110A may protect the signal via 106 from crosstalk emitted from other signal vias in close proximity on the PCB. In some embodiments, the signal via 106 and/or the slot ground 110A are at least partially filled with resin 108. The signal via 106 and/or the slot ground 110A are filled with resin to minimize and/or eliminate voids in the PCB. The resin may include an epoxy resin or a polyimide resin. In some embodiments, the signal via 106 has a nominal impedance of between approximately 60 ohms and approximately 100 ohms. In some embodiments, the signal via 106 has a nominal impedance of approximately 85 ohms.
Referring to
Each conductive layer 210-1 through 210-8 can include any suitable electrically conductive material (e.g., metal). Examples of materials that can be used to form each conductive layer 210-1 through 210-8 include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc. Non-conductive layers including non-conductive layer 220-1 may be formed from a non-conductive (e.g., electrically insulating) material. Examples of non-conductive materials that may be used for the non-conductive layers including non-conductive layer 220-1 include a composite plasticized phenol resin and paper material (e.g., FR-2), a composite material of woven fiberglass (e.g., FR-4), plastics, flexible plastics (e.g., for flexible circuit boards), and so on.
Each conductive layer 310-1 through 310-8 can include any suitable electrically conductive material (e.g., metal). Examples of materials that can be used to form each conductive layer 310-1 through 310-8 include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc. Non-conductive layers including non-conductive layer 320-1 may be formed from a non-conductive (e.g., electrically insulating) material. Examples of non-conductive materials that may be used for the non-conductive layers including non-conductive layer 320-1 include a composite plasticized phenol resin and paper material (e.g., FR-2), a composite material of woven fiberglass (e.g., FR-4), plastics, flexible plastics (e.g., for flexible circuit boards), and so on.
A mechanical drilling tool may also be used to drill multiple adjacent holes to form the slot 322. The slot 322 may be formed by drilling a first hole, a second hole immediately adjacent to the first hole, a third hole immediately adjacent to the third hole, etc. to make a C-shaped profile slot that at least partially surrounds the blind hole 324. In some embodiments, the blind hole 324 is drilled through a conductive pad 312 (e.g., a signal pad) disposed on a conductive layer (such as conductive layer 310-5). In some embodiments, the holes forming the slot 322 are drilled using the mechanical drilling tool to a first depth. For example, the holes forming the slot 322 are drilled to a depth between layer 310-5 and layer 310-6. The holes may be finish-drilled using a laser drilling tool as explained herein below with respect to
At operation 410, a signal via is formed in a PCB. The signal via may be a blind via or a through-hole via as described herein above. The via may be formed by drilling through one or more layers in the PCB and plating the walls of the hole to electrically connect conductive signal pads on different layers of the PCB. In some embodiments, another signal via (e.g., a second signal via) is formed, such as in embodiments where the signal vias are to transmit a differential pair signal.
At operation 420, a slot ground is formed in the PCB. To form the slot ground, one or more sub-operations are performed. At operation 422, a slot is formed in the PCB. The slot may be formed at least partially surrounding the signal via. In some embodiments, the slot has a substantially C-shaped profile. The center of the slot (e.g., the center of the C-shaped profile) may be substantially coaxial with the central axis of the signal via. At operation 424, a plating operation is performed to plate at least a wall of the slot with metal plating. The plating operation may be performed with respect to both the slot and the signal via to plate the slot and the signal via with metal plating. The metal plating may be a conductive metal plating (e.g., copper, tin, lead, gold, nickel, silver, or one or more metal alloys, etc.). At operation 426, the slot is at least partially filled with resin. The resin may include an epoxy resin or a polyimide resin. Filling the slot with resin may reduce voids in the PCB.
Referring to
At operation 510, multiple layers are laminated to form a PCB. The multiple layers may include alternating conductive and non-conductive layers. The conductive layers may include traces to transmit electrical signals. The non-conductive layers may insulate the conductive layers from one another.
At operation 520A, a hole is drilled through the multiple layers to form a signal via hole. The signal via hole may be a through-hole that extends through all layers of the PCB. In some embodiments, the hole is drilled using a mechanical drilling tool.
At operation 530, multiple adjacent holes are drilled to form a slot. The slot may at least partially surround the hole drilled at operation 520A. The holes may be drilled adjacent to one another to remove material from around the signal via. In some embodiments, the slot has a C-shaped profile. Using the mechanical drilling tool, the multiple adjacent holes may be drilled to a first depth.
At operation 540, the multiple adjacent holes are drilled to a second depth deeper than the first depth (e.g., the first depth drilled at operation 530). The multiple adjacent holes may be drilled to the second depth using a laser drilling tool. The laser drilling tool may have better tolerance control than the mechanical drilling tool so the final depth of the slot (e.g., the second depth) can be more precisely controlled.
At operation 550, a plating operation is performed to plate a wall of the signal via hole and a wall of the slot with metal plating. In some embodiments, both the walls of the signal via hole and the walls of the slot are plated during the same plating operation. In other embodiments, the walls of the signal via hole are plated separately from the walls of the slot. The metal plating can include a conductive metal plating as described herein above.
At operation 560, the signal via hole is back-drilled to remove at least a portion of the metal plating from the walls of the signal via hole. Back-drilling may include increasing the diameter of the signal via hole to remove the plating. In some embodiments, plating is removed from the signal via hole beneath a conductive pad to reduce the stub length of the signal via. Back-drilling the signal via hole may be performed prior to filling the hole with resin at operation 570.
At operation 570, the plated signal via hole and the plated slot are at least partially filled with resin. The resin may be an epoxy resin, a polyimide resin, and/or an ink resin as described herein above. Filling the plated signal via hole and the plated slot with resin may reduce the number of voids in the PCB.
Referring to
At operation 510, multiple layers are laminated to form a PCB. The multiple layers may include alternating conductive and non-conductive layers. The conductive layers may include traces to transmit electrical signals. The non-conductive layers may insulate the conductive layers from one another.
At operation 520B, a hole is drilled partially through the multiple layers to form a signal via hole. The signal via hole may be a blind-hole that extends only partially through the PCB. In some embodiments, the hole is drilled using a mechanical drilling tool.
At operation 530, multiple adjacent holes are drilled to form a slot. The slot may at least partially surround the hole drilled at operation 520A. The holes may be drilled adjacent to one another to remove material from around the signal via. In some embodiments, the slot has a C-shaped profile. Using the mechanical drilling tool, the multiple adjacent holes may be drilled to a first depth.
At operation 535, the signal via hole is drilled, using a laser drilling tool, to increase the depth of the signal via hole. At operation 540, the multiple adjacent holes are drilled, using a laser drilling tool, to a second depth deeper than the first depth (e.g., the first depth drilled at operation 530). The laser drilling tool may have better tolerance control than the mechanical drilling tool so the final depth of the slot (e.g., the second depth) can be more precisely controlled.
At operation 550, a plating operation is performed to plate a wall of the signal via hole and a wall of the slot with metal plating. In some embodiments, both the walls of the signal via hole and the walls of the slot are plated during the same plating operation. In other embodiments, the walls of the signal via hole are plated separately from the walls of the slot. The metal plating can include a conductive metal plating as described herein above.
At operation 570, the plated signal via hole and the plated slot are at least partially filled with resin. The resin may be an epoxy resin, a polyimide resin, and/or an ink resin as described herein above. Filling the plated signal via hole and the plated slot with resin may reduce the number of voids in the PCB.
Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to a specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in appended claims.
Use of terms “a” and “an” and “the” and similar referents in the context of describing disclosed embodiments (especially in the context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. “Connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitations of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, the use of the term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, the term “subset” of a corresponding set does not necessarily denote a proper subset of the corresponding set, but subset and corresponding set may be equal.
Conjunctive language, such as phrases of the form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with the context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of the set of A and B and C. For instance, in an illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, the term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). In at least one embodiment, the number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, the phrase “based on” means “based at least in part on” and not “based solely on.”
Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause a computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of the code while multiple non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors.
Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and/or software that enable the performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations.
Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.
All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
In description and claims, terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system's registers and/or memories into other data similarly represented as physical quantities within computing system's memories, registers or other such information storage, transmission or display devices.
In a similar manner, the term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transform that electronic data into other electronic data that may be stored in registers and/or memory. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or in parallel, continuously, or intermittently. In at least one embodiment, terms “system” and “method” are used herein interchangeably insofar as the system may embody one or more methods and methods may be considered a system.
In the present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways such as by receiving data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, processes of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In at least one embodiment, processes of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from providing entity to acquiring entity. In at least one embodiment, references may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, processes of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface or inter-process communication mechanism.
Although descriptions herein set forth example embodiments of described techniques, other architectures may be used to implement described functionality, and are intended to be within the scope of this disclosure. Furthermore, although specific distributions of responsibilities may be defined above for purposes of description, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances.
Furthermore, although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.
