Patent Application
20230058638
The present invention relates generally to the field of chip packaging, and more particularly to preserving chip integrity in packaging using controlled collapse chip connection (“C4”) bump bonding.
Silicon chips are built on silicon wafers and diced into chips. Often, a circuit is formed by interconnecting two or more chips. A common interconnection technique is the so-called flip chip or area array technique, also known as controlled collapse chip connection, or simply C4. For flip chips, a common technique is for an array of solder bump interconnects to be formed on bonding pads of a wafer before the wafer is diced into discrete first dies. Second dies with corresponding bonding pads are then oriented and aligned with the bumps and the first and second dies are joined together at the bumps using techniques that include one or more of solder reflow processes, cold-welding techniques, and other methods that are suitable to the fabrication, materials, the anticipated operating environment of the circuit, and other design and field-of-use considerations.
One embodiment of the invention is directed to a die stack that includes a first chip die, a second chip die connected to the first chip die by one or more controlled collapse chip connection (“C4”) solder bump bonds, and a spacer die interposed between the first and second chip dies, wherein the spacer die includes through holes for the one or more C4 solder bumps, the spacer die has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness has a minimum defined spacing between the first and second chip dies, and the spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.
In one aspect, the die stack includes an alignment hole through the spacer die that engages a corresponding alignment pin on one of the first chip die or second chip die, or engages alignment pins on both of the first chip die and the second die. In another aspect, an alignment pin on the spacer die engages a corresponding alignment hole on one of the first or second chip dies. In another aspect, an alignment hole through the spacer die engages a corresponding alignment pin on one of the first chip die or the second chip die, or engages alignment pins on both of the first and the second chip dies, and an alignment pin on the spacer die engages a corresponding alignment hole on one of the first chip die or the second chip die. Further, each arrangement may include two alignment pins and corresponding two alignment holes, wherein one of the alignment holes is dimensioned to fit its corresponding alignment pin to a close tolerance, and the other alignment hole is dimensioned with a sufficient oblong shape to allow for differential movement between the spacer die and one or both chip dies as a result of a difference between the coefficient of thermal expansion (CTE) of the spacer die and the chip dies.
In another aspect, the spacer die further includes one or both of a device through hole aligned with a device on one of the first chip die or second chip die, to reduce one or both of mechanical interference of the spacer die on the device or electrical effects of the spacer die on the device, and a device pocket etched into the spacer die that is aligned with a device on one of the first chip die or the second chip die, to reduce one or both of mechanical interference of the spacer die on the device or electrical effects of the spacer die on the device.
In another aspect, the spacer die further includes a channel etched into the spacer die that accommodates airflow through the die stack.
In another aspect, the spacer die comprises a lattice configuration.
In another aspect, one of the first chip die and the second chip die includes a pre-loaded connection pin contact pad aligned with a portion of the spacer die that provides compressive structural support to the chip die at the point where the pre-loaded connection pin contacts the connection pad.
In another aspect, the spacer die thickness allows for cold-weld compression bonding of the first chip die to the second chip die.
In another aspect, the diameter of each through hole is sufficiently larger than its corresponding uncompressed C4 bump such that an aligned spacer die may be placed on its associated chip die without touching any of the uncompressed C4 bumps.
In another aspect, the dimensions of each through hole are such that when the first chip die and second chip die are compressed into contact with the spacer die, the volume of the through hole is greater than the volume of its corresponding C4 bump such that the C4 bump does not overflow the through hole, and expansion of the C4 bump diameter does not cause electrical shorting between adjacent bumps or other connections.
In another aspect, the spacer die is comprised of the same materials as the substrate materials of the first and second chip dies. In other embodiments, the spacer die is comprised of a non-conducting material that acts as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die, and with a coefficient of thermal expansion (CTE) similar enough to the CTE of the chip dies so as to eliminate damage to the C4 bumps caused by differential movement between the spacer die and one or both chip dies as a result of a difference between the CTEs of the spacer die and the chip dies. In certain embodiments, the spacer die is comprised a material selected from the group consisting of silicon, and glass.
In one embodiment, the invention is directed to a method of forming a die stack, that includes fabricating a first chip die, a second chip die, and a spacer die; placing the first chip die on a bonder base plate; placing the spacer die on top of the first chip die; placing the second chip die on a bonder pressure plate; and cold-welding the first chip die to the second chip die, at one or more controlled collapse chip connection (“C4”) solder bump bonds on one or both of the first chip die and the second chip die, by applying a compression force to the bonder compression plate. The spacer die includes through holes for the one or more C4 solder bumps, and has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness is a minimum defined spacing between the first and second chip dies. The spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.
In another aspect, the first chip die, second chip die, and spacer die are fabricated such that an alignment hole through the spacer die engages a corresponding alignment pin on one of the first chip die or the second chip die, or engages alignment pins on both of the first chip die and the second die. In another aspect, an alignment pin on the spacer die engages a corresponding alignment hole on one of the first chip die or the second chip die. In another aspect, an alignment hole through the spacer die engages a corresponding alignment pin on one of the first chip die or the second chip die, or engages alignment pins on both of the first chip die and the second die, and an alignment pin on the spacer die that engages a corresponding alignment hole on one of the first chip die or the second chip die. Further, each arrangement may include two alignment pins and a corresponding two alignment holes, wherein one of the alignment holes is dimensioned to fit its corresponding alignment pin to a close tolerance, and the other alignment hole is dimensioned with a sufficient oblong shape to allow for differential movement between the spacer die and one or both chip dies caused by a difference between the coefficient of thermal expansion (CTE) of the spacer die and the chip dies.
In another aspect, the spacer die further includes one or more of a device through hole aligned with a device on one of the first or the second chip dies, so as to reduce one or both of mechanical interference of the spacer die on the device or electrical effects of the spacer die on the device, and a device pocket etched into the spacer die and aligned with a device on one of the first chip die or the second chip die, so as to reduce one or both of mechanical interference of the spacer die on the device or electrical effects of the spacer die on the device.
In another aspect, the spacer die includes a channel etched into the spacer die to accommodate airflow through the die stack.
In another aspect, the spacer includes a lattice configuration.
In another aspect, one of the first chip die and the second chip die includes a pre-loaded connection pin contact pad aligned with a portion of the spacer die that provides compressive structural support to the chip die at the point where the pre-loaded connection pin contacts the connection pad.
In another aspect, the spacer die thickness allows for cold-weld compression bonding of the first chip die to the second chip die.
In another aspect, the diameter of each through hole is sufficiently larger than its corresponding uncompressed C4 bump such that a properly aligned spacer die can be placed on its associated chip die without touching the uncompressed C4 bumps.
In another aspect, dimensions of each through hole are such that when the first and second chip dies are compressed into contact with the spacer die, the volume of the through hole is greater than the volume of its corresponding C4 bump such that the C4 bump does not overflow the through hole, and the expansion of the C4 bump diameter does not cause electrical shorting between adjacent bumps and other connections.
In another aspect, the spacer die is comprised of the same materials as the substrate materials of the first and second chip dies. In other embodiments, the spacer die is comprised of a non-conducting material that acts as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die, and with a coefficient of thermal expansion (CTE) similar enough to the CTE of the chip dies so as to eliminate damage to the C4 bumps caused by a differential movement between the spacer die and one or both chip dies as a result of a difference between the CTEs of the spacer die and the chip dies. In certain embodiments, the spacer die is comprised a material selected from the group consisting of: silicon, and glass.
C4 interconnection techniques can be used to create high-density stacked-die packages typically that include multiple silicon dies in a stacked configuration. The C4 solder bumps are tiny metallic “balls” that typically electrically connect the contact pads on two dies. Each die may include multiple electrical components and devices, and multiple device layers, and may include multiple internal interconnect layers and structures, including, for example, layer-to-layer vias. Each die may include a complete system or sub-system, or multiple interconnected dies may be required for a complete system or sub-system. To interconnect two dies, a wire is typically patterned on or in a first die that connects to a contact pad. On a second die, a corresponding contact pad is formed. On one or the other contact pads, a C4 bump is formed, the two dies are aligned within, for example, a compression bonder, and the two dies are cold-welded at the C4 bump. The C4 bumps are typically made from a solder, such as a leaded solder, e.g. Pb—Sn, a lead-free solder, e.g. SAC, or a low temperature alloy for cryogenic use, e.g., Indium.
In chip packages formed with C4 techniques, the C4 solder balls are typically relied upon not only to provide the electrical connectivity between the dies of a die stack, but also to provide mechanical rigidity during processing and use for those cases where, for example, an epoxy underfill of the C4 bumps may not be feasible due to electrical or rework limitations.
During processing and use, the C4 bumps may experience compressive, shear, twist, and other forces. These forces might include, for example, cold-weld compression forces during fabrication, preload spring biasing forces from heat sinks and connectors, torque, twist, and compression forces during manual handling of the chip stacks, etc.
Under the influence of these forces, C4 bumps may tend to “flatten” and/or “smear,” collectively referred to herein as “creep.” Further, common situations and conditions may exacerbate C4 creep. For example, creep can increase if C4 bumps subject to these forces are exposed to elevated processing or operating temperatures, or if the solder is rather soft at room temperature, such as Indium.
C4 bump creep can be detrimental to the integrity of the package. For example, as the height of a C4 bump decreases with time, its diameter increases, which may lead to electrical shorting between adjacent bumps and other connections. A decrease in bump height will also cause changes to the die stack geometry. Depending on the particular device being fabricated, this change in geometry may cause unexpected changes in the device performance, such as a change in high frequency electrical characteristics. The decrease in bump height may also cause a reduction to the preload biasing force of connector contact pins, which may cause an unexpected change in contact resistance. It would therefore be advantageous to control bump creep in a C4 die stack package.
Embodiments of the invention are directed generally to a system that controls and limits C4 bump creep. The system may also provide structural support to a die stack that might otherwise be provided by the C4 bumps in the die stack package. In various embodiments, a separate rigid spacer die having holes at the corresponding C4 bump locations is interposed between two “chip dies” that will be joined. As used herein, the term “chip die” will refer to prior art device or interposer dies that can be joined to form a die stack. The spacer die thickness corresponds to a minimum defined spacing between chip dies that is sufficient to allow for the chip dies on either side of the spacer die to, in fact, be joined with a C4 bump bonding process, and in accordance with other considerations as described below. The spacer die thickness is also dimensioned to provide a hard stop to any bump compression beyond a minimum bump height. That is, the die stack can compress until the gap between the chip dies and the spacer dies is closed, subject to, for example, surface debris and other extraneous material on the opposing surfaces. At this point, the spacer dies are providing at least compressive structural integrity to the die stack, and further C4 bump compression should not occur. The spacer dies constrain the creep of the solder in the C4 bumps in a manner that will not compromise the electrical or mechanical performance of the device without requiring the typical underfill. In certain embodiments, the spacer die may also provide structural integrity to the die stack against other stress forces, such as shear forces, through, for example, contact friction and other surface effects between the spacer die and the adjacent chip dies, and the use of close-tolerance alignment pins. When fully compressed, the spacer dies may also provide a heat bridge to conduct heat away from hot spots on a die.
In various embodiments, the spacer die may be patterned to include “lattice”-like structures, etched “pockets”, etched “channels” and other forms to allow the spacer die to be interposed between two chip dies with minimal or no modifications to the chip dies.
For the sake of brevity, conventional techniques related to semiconductor and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture circuit material structures may be well known and so, in the interest of brevity, many conventional steps may only be mentioned briefly or may be omitted entirely without providing the well-known process details.
For the clarity of the description, and without implying any limitation thereto, illustrative embodiments may be described using simplified diagrams. In an actual fabrication, additional structures that are not shown or described herein, or structures different from those shown and described herein, may be present without departing from the scope of the illustrative embodiments.
Differently patterned portions in the drawings of the example structures, layers, and formations are intended to represent different structures, layers, materials, and formations in the example fabrication, as described herein. A specific shape, location, position, or dimension of a shape depicted herein is not intended to be limiting on the illustrative embodiments unless such a characteristic is expressly described as a feature of an embodiment. The shape, location, position, dimension, or some combination thereof, are chosen only for the clarity of the drawings and the description and may have been exaggerated, minimized, or otherwise changed from actual shape, location, position, or dimension that might be used in actual fabrication to achieve an objective according to the illustrative embodiments.
An embodiment when implemented in an application causes a fabrication process to perform certain steps as described herein. The steps of the fabrication process are depicted in the several figures. Unless such a characteristic is expressly described as a feature of an embodiment, not all steps may be necessary in a particular fabrication process; some fabrication processes may implement the steps in different order, combine certain steps, remove or replace certain steps, or perform some combination of these and other manipulations of steps, without departing the scope of the illustrative embodiments.
The illustrative embodiments are described with respect to certain types of materials, electrical properties, structures, formations, layers orientations, directions, steps, operations, planes, dimensions, numerosity, data processing systems, environments, and components. Unless such a characteristic is expressly described as a feature of an embodiment, any specific descriptions of these and other similar artifacts are not intended to be limiting to the invention; any suitable manifestation of these and other similar artifacts can be selected within the scope of the illustrative embodiments.
The illustrative embodiments are described using specific designs, architectures, layouts, schematics, and tools only as examples and are not limiting to the illustrative embodiments. The illustrative embodiments may be used in conjunction with other comparable or similarly purposed designs, architectures, layouts, schematics, and tools.
The examples in this disclosure are used only for the clarity of the description and are not limiting to the illustrative embodiments. Any advantages listed herein are only examples and are not intended to be limiting to the illustrative embodiments. Additional or different advantages may be realized by specific illustrative embodiments. Furthermore, a particular illustrative embodiment may have some, all, or none of the advantages listed herein.
For purposes of the description, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “outer”, “inner”, and derivatives thereof relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, and intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact”, “directly on top of”, or the like, means that a first element, such as a first structure, and a second element, such as a second structure, are in direct contact without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
As used herein, the term “same” when used for comparing values of a measurement, characteristic, parameter, etc., such as “the same width,” means nominally identical, such as within industry accepted tolerances for the measurement, characteristic, parameter, etc., unless the context indicates a different meaning. As used herein, the terms “about,” “approximately,” or similar terms, when used to modify physical or temporal values, such as length, time, temperature, quantity, electrical characteristics, etc., or when such values are stated without such modifiers, means nominally equal to the specified value in recognition of variations to the values that can occur during typical handling, processing, and measurement procedures. These terms are intended to include the degree of error associated with measurement of the physical or temporal value based upon the equipment available at the time of filing the application. For example, the term “about” or similar can include a range of ±8% or 5%, or 2% of a given value. In one aspect, the term “about” or similar means within 10% of the specified numerical value. In another aspect, the term “about” or similar means within 5% of the specified numerical value. Yet, in another aspect, the term “about” or similar means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the specified numerical value. In another aspect, these terms mean within industry accepted tolerances.
Typically, each chip die 112 is successively bonded to the chip die below it. Thus, when an “upper” chip die is bonded onto the chip die beneath, the compressive force is transmitted down the die stack to the lower C4 bump arrays 114. Each C4 bump array 114 will therefore experience the compressive bonding forces of all subsequent cold-weld compression operations for each C4 bump array 114 higher in the stack. These successive cold-weld compressions may cause an undesirable level of C4 bump creep in one or more of the lower C4 bump arrays 114.
In a multi-die stack as illustrated, the use of an underfill, if allowed by electrical and reworkability constraints, might be impractical because dispensing and curing of the underfill at every stage of a cold-weld die connection process could potentially cause contamination of the upper surface of the top chip die where the next chip die is to be attached.
In certain situations, maintaining the alignment of the spacer die with respect to chip dies just above and just below the spacer die may be desirable. For example, if the process calls for the solder for the C4 bumps to be injected onto the contact pads of a chip die after alignment and placement of the spacer die, some mechanism to hold the spacer die in alignment on the chip die would be desirable. In other situations, the die stack may experience shear forces tending the smear the C4 bumps. Here, some mechanism to maintain structural integrity of the die stack against such shear forces would be desirable beyond, for example, what might be provided by surface friction and other surface effects between the spacer die and adjacent chip dies.
In various embodiments, the holes in the spacer dies have a diameter that is large enough to not make contact with the C4 bumps after the die stack is compressed to the maximum amount allowed by the height of the interposed spacer dies, and the C4 bump diameters have increased to their maximum amount due to their compression. Further, the volume of the holes in the spacer dies is larger than the volume of the C4 bump. This may be advantageous, for example, because changes to the fabrication process of record may be minimized with the exception of interposing the spacer dies between chip dies to be joined. Also, dimensioning the diameter of the holes in the spacer dies to be larger than the expected maximum bump diameter, and the volume of the holes to be larger than the C4 bumps, may help to ensure that there is no “overflow” out of the holes in the spacer dies of the C4 bumps after maximum compression.
As mentioned, it may be advantageous to dimension the through-holes 204 in spacer die 202 such that after an expected amount of symmetric radial expansion of the bumps resulting from an expected maximum amount of creep, the bumps do not contact the sidewalls of the through-holes 204. However, if bump creep does occur in an asymmetric manner, as illustrated by smeared bump 208, the creep is constrained within the through-holes 204.
A contact pad 660, to which C4 bump 658 is welded, is connected to another contact pad 662 on the surface of the die stack that is offset from contact pad 660. Contact pad 662 is positioned on chip die 652 such that it is above a portion of spacer die 654. When pre-loaded contact pin 664 makes contact with contact pad 662, the portion of spacer die 654 below contact pad provides compressive structural support to thin chip die 652 so as to prevent the deformation 618 shown in
While various aspects and configurations of a spacer die have been illustrated in separate embodiments, combinations of these may be implemented as desired and as may be required for a particular die stack.
Because a primary purpose of the spacer die is to provide a “hard” stop against compressive forces in a die stack, and also to mitigate bump creep from other forces, such as shear, torque, and twist, the spacer die should be formed from a material having sufficient rigidity along the different axes to limit creep to the desired degree. It may be advantageous if the coefficient of thermal expansion (CTE) of the spacer die material matches or is similar enough or is within a defined tolerance of the CTE of the chip dies so as to avoid damage to bumps caused by an expansion mismatch.
In various embodiments, the spacer die may be formed from the same material as the chip dies in the die stack, or from a non-conducting material with sufficient rigidity and with a CTE that matches or is within a defined tolerance of the CTE of the chip dies. Examples of such materials include silicon and glass. For microwave frequency applications, the use of a low dielectric material such as silicon may be desirable to minimize electrical loss in the circuits.
As described above, the spacer dies may be formed separately from the chip dies, and are aligned and placed on a first chip die before a second chip is joined to the first chip die via a C4 bump bonding process.
The through-holes in a spacer die may be fabricated by known techniques that are suitable to the spacer die material and the desired dimensions, such as etching the spacer material either by laser or chemical means, or by mechanical drilling. Similarly, the removal of material to form lattice structures, device “pockets”, and channels may be fabricated by known techniques.
A spacer die is placed on top of the lower chip die (step 906). For example, spacer die 306 is placed on top of lower chip die 310. As described above, the spacer die is aligned with the lower chip die before placement. In certain embodiments, this alignment is assisted by the use of alignment pins and alignment holes. See, for example, alignment pins 212 and 216, and associated alignment holes 210 and 214, described above with reference to
An upper chip die is placed on the bonder pressure plate (step 908). For example, chip die 304 is placed on bonder compression plate 302. The upper chip die is then cold-welded to the lower die by a compression welding process (step 910). For example, a compression force is applied to bonder compression plate 302 to cold-weld upper chip die 304 to lower chip die 310 at C4 bumps 308.
Optionally, if the chip stack includes additional chip dies, such as illustrated in
Based on the foregoing, a structure and a method have been disclosed. However, numerous modifications and substitutions can be made without deviating from the scope of the present invention. Therefore, the present invention has been disclosed by way of example and not limitation.
This invention was made with U.S. Government support. The U.S. Government has certain rights in this invention.
