With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (finFETs), and gate-all-around (GAA) FETs. Such scaling down has increased the complexity of semiconductor manufacturing processes.
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures.
Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.
The GAA transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.
The increasing demand for small, portable multifunctional electronic devices has increased the demand for low power devices that can perform increasingly complex and sophisticated functions while providing ever-increasing storage capacity. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power semiconductor devices in integrated circuits (ICs). These goals have been achieved in large part by scaling down the dimensions of the semiconductor devices, thus increasing the device density of the ICs. However, continued scaling also introduces considerable device fabrication challenges. For example, the scaled down dimensions have increased the challenges of preventing epitaxial source/drain (S/D) regions on adjacent fin structures of FETs (e.g., finFETs or GAA FETs) from merging with each other during fabrication. In addition, forming electrical connections between the S/D regions and front-side power rail structures in scaled down semiconductor devices have also become challenging.
The present disclosure provides example semiconductor devices (e.g., GAA FETs) having epitaxial S/D regions with reduced lateral dimensions and contact structures electrically connecting S/D regions with a back-side power rail. The present disclosure also provides example methods to manufacture the semiconductor devices.
In some embodiments, the semiconductor device can have S/D spacers formed along sidewalls of fin structures prior to epitaxially growing the S/D regions on the fin structures. The S/D spacers can include a dielectric material and can control the epitaxial lateral growth of the S/D regions. In some embodiments, the S/D spacers can limit the epitaxial lateral growth of each side of the S/D regions to a lateral dimension of about 1 nm to about 15 nm. To limit the epitaxial lateral growth to such lateral dimensions, the S/D spacers can have a width of about 3 nm to about 15 nm and a thickness of about 1 nm to about 30 nm. Thus, the S/D spacers can prevent the S/D regions on adjacent fin structures from merging during their epitaxial growth process. In addition, the use of S/D spacers reduces the number of processing steps and cost for forming the electrically isolated S/D regions on adjacent fin structures compared to other methods of forming electrically isolated S/D regions on adjacent fin structures without the S/D spacers.
In some embodiments, portions of the fin structures under the back-sides of one or more of the S/D regions can be replaced with back-side contact structures and the other portions of the fin structures under the other S/D regions and gate structures of the semiconductor device can be replaced with a first back-side dielectric layer. The back-side contact structures can be electrically connected to a back-side power rail formed in a second back-side dielectric layer disposed on the first back-side dielectric layer. In some embodiments, the formation of the back-side power rail and the electrical connections of one or more of the S/D regions to the back-side power rail can reduce device area and the number and dimension of interconnects between S/D regions and power rails, thus reducing device power consumption compared to other semiconductor devices without back-side power rails. In addition, the back-side power rail can be formed with a lower resistance than a front-side power rail formed on the front-sides of the S/D regions, as the back-side power rail can be formed in a larger area than the front-side power rail.
Furthermore, the back-side contact structures can be formed with smaller widths (e.g., about 5 nm to about 10 nm smaller than widths of the S/D regions) than front-side contact structures, which require deeper etching of the S/D regions than the back-side contact structures. Thus, electrically connecting the S/D regions to the back-side power rail through the back-side contact structures can reduce the loss of S/D regions during back-side contact structure formation, thus improving device performance compared to that of devices with S/D regions electrically connected to front-side power rails through front-side contact structures.
Referring to
In some embodiments, for NFET 100, each of S/D regions 102 can include an epitaxially-grown semiconductor material, such as Si and silicon carbide (SiC) doped with n-type dopants, such as phosphorus and other suitable n-type dopants. In some embodiments, for PFET 100, each of S/D regions 102 can include an epitaxially-grown semiconductor material, such as Si and SiGe doped with p-type dopants, such as boron and other suitable p-type dopants.
In some embodiments, the epitaxial lateral growth of S/D regions 102 along a Y-axis can be controlled by S/D spacers 104. As a result, S/D spacers 104 can prevent adjacent S/D regions 102, such as S/D regions 102A1 and 102B1, 102A2 and 102B2, and 102A3 and 102B3 from merging with each other during the epitaxial growth of S/D regions 102. In some embodiments, S/D spacers 104 can limit the epitaxial lateral growth of each S/D region 102 to lateral distances D1 and D2 extending outwards from bottom sidewalls 102s of S/D region 102, as shown in
The epitaxial lateral growth control of S/D regions 102 can depend on the dimension of S/D spacers 104. For example, to limit the epitaxial lateral growth of each S/D region 102 to lateral distances D1 and D2, S/D spacers 104 can have a width W1 of about 2 nm to about 15 nm and a thickness T1 of about 1 nm to about 30 nm. In some embodiments, S/D spacers 104 can include a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), and other suitable dielectric materials. In some embodiments, in addition to epitaxial lateral growth of S/D regions 102, S/D spacers 104 can reduce or minimize the etching of STI regions 118 during the formation of S/D regions 102, as described below with reference to
In some embodiments, FS contact structures 122F can be disposed directly on FS surfaces 102f of one or more S/D regions 102 (e.g., S/D regions 102A2, 102A3, and 102B2) to electrically connect S/D regions 102 to other elements of FET 100 and/or to other active and/or passive devices (not shown) in an integrated circuit. In some embodiments, each of FS contact structures 122F can include (i) a silicide layer 124F disposed directly on FS surface 102f, and (ii) a contact plug 126F disposed directly on silicide layer 124F. In some embodiments, silicide layers 124F can extend on sidewalls of S/D regions 102 to increase contact area with S/D regions, thus increasing conductivity between S/D regions 102 and FS contact structures 122F. In some embodiments, contact plugs 126F can have widths W2 along a Y-axis greater than width W3 of S/D regions 102 along a Y-axis to prevent misalignment between FS contact structures 122F and S/D regions 102. As a result of the larger width W2, contact plugs 126F can be partly disposed directly on ESLs 114F and ILD layers 116F surrounding S/D regions 102A2 and 102B2, as shown in
In some embodiments, silicide layer 124F can include titanium silicide (TixSy), tantalum silicide (TaxSy), molybdenum (MoxSy), zirconium silicide (ZrxSiy), hafnium silicide (HfxSy), scandium silicide (ScxSy), yttrium silicide (YxSy), terbium silicide (TbxSy), lutetium silicide (LuxSiy), erbium silicide (ErxSy), ybtterbium silicide (YbxSy), europium silicide (EuxSiy), thorium silicide (ThxSy), other suitable metal silicide materials, or a combination thereof for GAA NFET 100. In some embodiments, silicide layer 124F can include nickel silicide (NixSy), cobalt silicide (CoxSy), manganese silicide (MnxSy), tungsten silicide (WxSy), iron silicide (FexSy), rhodium silicide (RhxSy), palladium silicide (PdxSy), ruthenium silicide (RuxSy), platinum silicide (PtxSy), iridium silicide (IrxSy), osmium silicide (OsxSy), other suitable metal silicide materials, or a combination thereof for GAA PFET 100. In some embodiments, contact plugs 126F can include conductive materials, such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), stannum (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and a combination thereof.
FS ILD layers 116F and FS ESLs 114F can provide electrical isolation between FS contact structures 122F and between FS contact structures 122F and gate structures 108. In some embodiments, FS ILD layers 116F and FS ESLs 114F can include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), and other suitable dielectric materials. In some embodiments, FS ILD layers 116F can include an oxide material and FS ESLs 114F can include a nitride material different from FS ILD layers 116F. In some embodiments, the portions of FS ESLs 114F extending below S/D spacers 104 can have a semi-circular-shaped or open-circular-shaped profile, as shown in
In some embodiments, BS contact structure 122B can be disposed in S/D region 102A2 (shown in
In some embodiments, BS contact structure 122B can be formed with smaller dimensions than that of FS contact structures electrically connecting S/D regions to FS power rails in FETs without BS power rails. In some embodiments, BS contact structure 122B can have a height H1 of about 5 nm to about 40 nm and a width W6 that is smaller than width W5 of S/D region 102A2 by about 5 nm to about 10 nm. Such dimensions of BS contact structure 122B can achieve adequate electrical conductivity between BS contact structure 122B and S/D region 102A2 without compromising the size and manufacturing cost of FET 100. In addition to smaller dimensions, BS contact structure 122B can also be formed with less amount of etching of S/D region 102A2 compared to that with FS contact structures in FETs without BS power rails. For example, the formation of BS contact structure 122B extending into S/D region 102A2, as shown in
In some embodiments, BS contact structure 122B can be disposed between S/D spacers 104 of S/D region 102A2 and a width W7 of BS contact structure 122B can be limited by the distance between S/D spacers 104 of S/D region 102A2, as shown in
Diffusion barrier layer 128B can prevent the oxidation of contact plug 126B by preventing the diffusion of oxygen atoms from adjacent structures (e.g., BS ILD layers 116B and BS barrier layers 120) to contact plug 126B. In some embodiments, diffusion barrier layer 128B can include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), zirconium oxide (ZrO2), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium aluminum oxide (ZrAlO), zinc oxide (ZnO2), and other suitable dielectric materials. In some embodiments, diffusion barrier layers 128B can have a thickness of about 1.5 nm to about 4 nm. Within this range of thickness, diffusion barrier layer 128B can adequately prevent the oxidation of contact plugs 126B without compromising the size and manufacturing cost of FET 100.
In some embodiments, BS barrier layers 120 can be disposed directly on BS surfaces of gate structures 108 and on BS surfaces 102b of S/D regions 102 that do not have BS contact structures 122B, such as S/D regions 102A1, 102B1, and 102B2. BS ILD layers 116B can be disposed directly on BS barrier layers 120 and BS ESLs 114B can be disposed directly on BS ILD layers 116B. BS barrier layers 120, BS ILD layers 116B, and BS ESLs 114B can include a dielectric layer and can protect gate structures 108 and S/D regions 102 during the formation of BS elements, such as BS contact structure 122B and BS power rail 132. In addition, BS barrier layers 120 and BS ILD layers 116B can provide electrical isolation between BS contact structure 122B and other BS contact structures (not shown). In some embodiments, BS barrier layers 120 can include an oxide layer. The discussion of the materials of FS ILD layers 116F and FS ESL 114F applies to BS ILD layers 116B and BS ESL 114B, unless mentioned otherwise. In some embodiments, BS barrier layers 120 may not be included and BS ILD layers 116B can be disposed directly on BS surfaces of gate structures 108, as shown in
Referring to
Referring to
In some embodiments, each of gate structures 108 can include (i) an interfacial oxide (IL) layer 108A disposed on nanostructured channel regions 106, (ii) a high-k gate dielectric layer 108B disposed on IL layer 108A, and (iii) a conductive layer 108C disposed on high-k gate dielectric layer 108B. In some embodiments, IL layer 108A can include silicon oxide (SiO2), silicon germanium oxide (SiGeOx), or germanium oxide (GeOx). In some embodiments, high-k gate dielectric layer 108B can include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium aluminum oxide (ZrAlO), zirconium silicate (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3) zinc oxide (ZnO), hafnium zinc oxide (HfZnO), and yttrium oxide (Y2O3). In some embodiments, IL layer 108A can have a thickness of about 0.1 nm to about 2 nm and high-k gate dielectric layer 108B can have a thickness of about 0.5 nm to about 5 nm. Within these ranges of thicknesses, gate structures 108 can perform adequately without compromising the size and manufacturing cost of FET 100.
In some embodiments, conductive layer 108C can be a multi-layered structure. The different layers of conductive layer 108C are not shown for simplicity. Each of conductive layer 108C can include a work function metal (WFM) layer disposed on high-k gate dielectric layer 108B and a gate metal fill layer disposed on the WFM layer. In some embodiments, the WFM layer can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials for GAA NFET 100. In some embodiments, the WFM layer can include substantially Al-free (e.g., with no Al) Ti-based or Ta-based nitrides or alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti—Au) alloy, titanium copper (Ti—Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta—Au) alloy, and tantalum copper (Ta—Cu) for GAA PFET 100. The gate metal fill layers can include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and a combination thereof.
In some embodiments, gate structure 108 can be electrically isolated from adjacent FS contact structures 122F by outer gate spacers 110 and the portions of gate structures 108 surrounding nanostructured channel regions 106 can be electrically isolated from adjacent S/D regions 102 by inner gate spacers 112. Outer gate spacers 110 and inner gate spacers 112 can include a material similar to or different from each other. In some embodiments, outer gate spacers 110 and inner gate spacers 112 can include an insulating material, such as SiO2, SiN, SiON, SiCO, SiCN, SiCON, and other suitable insulating materials. In some embodiments, each of outer gate spacers 110 can have a thickness of about 1 nm to about 10 nm. Within this range of thickness, adequate electrical isolation can be provided by outer gate spacers 110 between gate structures 108 and adjacent FS contact structures 122F without compromising the size and manufacturing cost of FET 100. In some embodiments, adjacent S/D spacers 104 and outer gate spacers 110 are portions of the same spacer material layer and can be in direct contact with each other, as described below with reference to
In operation 205, superlattice structures are formed on fin structures on a substrate, and polysilicon structures are formed on the superlattice structures. For example, as shown in
Referring to
In some embodiments, outer gate spacers 110 and S/D spacers 104 can be formed from the same spacer material layer 304 at different stages of selectively dry etching spacer material layer 304. Spacer material layer 304 can include SiO2, SiN, SiON, SiCO, SiCN, SiCON, and other suitable insulating materials. The formation of outer gate spacers 110 and S/D spacers 104 can start with depositing a substantially conformal spacer material layer 304 directly on polysilicon structures 308, superlattice structures 307, fin structures 336A and 336B above STI regions 118, and STI regions 118, as shown in
In some embodiments, the first etching process can be an anisotropic dry etching process and can have a higher etching rate along a Z-axis rather than along an X-axis or a Y-axis. As a result, spacer material layer 304 on top surfaces of polysilicon structures 308, superlattice structures 307, and STI regions 118 can be removed, while spacer portions 304* on sidewall surfaces of superlattice structures 307 and fin structures 336A and 336B can remain. The etching gases used in the first etching process can have a higher selectivity for spacer material layer 304 than for polysilicon structures 308 and superlattice structures 307.
The first etching process can be followed by a second etching process to selectively etch portions of spacer portions 304* to form S/D spacers 104 and portions of superlattice structures 307 to form S/D openings 502, as shown in
In some embodiments, the second etching process can include a plasma-based dry etching process using etching gases, such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr), with mixture gases, such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar). The second etching process can be performed at a temperature ranging from about 25° C. to about 200° C. under a pressure from about 5 mTorr to about 50 mTorr. The flow rate of the etching gases can range from about 5 standard cubic centimeter per minute (sccm) to about 100 sccm. The plasma power can range from about 50 W to about 200 W with a bias voltage from about 30 V to about 200 V.
In some embodiments, width W1 and thickness T1 of S/D spacers 104 can be tuned by adjusting the second etching process conditions, such as the etch selectivity of the etching gases for superlattice structures 307 and spacer portions 304*, the flow rate of the etching gases, and the bias voltage of the plasma. In some embodiments, the etching gases used in the second etching process can have a higher selectivity for superlattice structures 307 than for spacer portions 304* to remove superlattice structures 307 at a higher etching rate than spacer portions 304*. As a result, at the end of the second etching process, the portions of superlattice structures 307 not covered by polysilicon structures 308 can be fully removed, while S/D spacers 104 can remain to control the epitaxial lateral growth of subsequently-formed S/D regions 102.
In some embodiments, the etching gases used in the second etching process can have a higher selectivity for STI regions 118 than for spacer portions 304*. As a result, portions of STI regions 118 can be etched to form recesses 518 in STI regions 118. In some embodiments, width W1 of S/D spacers 104 can be about 2 nm to about 15 nm to prevent recesses 518 from extending to fin structures 336A and 336B and exposing sidewalls of fin structures 336A and 336B to the etching gases of the second etching process.
Referring to
Referring to
In some embodiments, the formation of S/D regions 102 can be followed by the deposition of FS ESLs 114F on the structures of
Referring to
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In some embodiments, contact opening 1222 can be formed by using a photolithographic patterning process and an etching process to remove portions of fin structure 336A under S/D region 102A2. In some embodiments, the etching process can include a dry etching process using etchants including chlorine (Cl2), hydrogen bromide (HBr), and oxygen (O2). A flow rate of the etchants can range from about 5 sccm to about 200 sccm. The dry etching process can be performed at a pressure ranging from about 1 mTorr to about 100 mTorr with a plasma power ranging from about 50 W to about 250 W. In some embodiments, contact opening 1222 can extend a distance D3 of about 3 nm to about 20 nm into S/D region 102A2, as shown in
Referring to
Referring to
The present disclosure provides example FETs (e.g., GAA FET 100) having epitaxial S/D regions (e.g., S/D regions 102) with reduced lateral dimensions and contact structures (e.g., BS contact structure 122F) electrically connecting S/D regions with BS power rails (e.g., BS power rail 132). The present disclosure also provides example methods of the semiconductor devices. In some embodiments, the FET can have S/D spacers (e.g., S/D spacers 104) formed along sidewalls of fin structures (e.g., fin structures 336A and 336B) prior to epitaxially growing the S/D regions on the fin structures. The S/D spacers can include a dielectric material and can control the epitaxial lateral growth of the S/D regions. In some embodiments, the S/D spacers can limit the epitaxial lateral growth of each side of the S/D regions to a lateral dimension (e.g., lateral distances D1 and D2) of about 1 nm to about 15 nm. To limit the epitaxial lateral growth to such lateral dimensions, the S/D spacers can have a width (e.g., width W1) of about 3 nm to about 15 nm and a thickness (e.g., thickness T1) of about 1 nm to about 30 nm. Thus, the S/D spacers can prevent the S/D regions on adjacent fin structures from merging during their epitaxial growth process. In addition, the use of S/D spacers reduces the number of processing steps and cost for forming the electrically isolated S/D regions on adjacent fin structures compared to other methods of forming electrically isolated S/D on adjacent fin structures without the S/D spacers.
In some embodiments, portions of the fin structures under the BS of one or more of the S/D regions can be replaced with back-side contact structures (e.g., BS contact structure 122F) and the other portions of the fin structures under the other S/D regions and gate structures of the semiconductor device can be replaced with a first BS dielectric layer (e.g., BS ILD layers 116B). The BS contact structures can be electrically connected to a BS power rail (e.g., BS power rail 132) formed in a second BS dielectric layer (e.g., dielectric layer 130) disposed on the first BS dielectric layer. In some embodiments, the formation of the BS power rail and the electrical connections of one or more of the S/D regions to the BS power rail can reduce device area and the number and dimension of interconnects between S/D regions and power rails, thus reducing device power consumption compared to other semiconductor devices without BS power rails. In addition, the BS power rail can be formed with a lower resistance than a FS power rail formed on the FS of the S/D regions, as the BS power rail can be formed in a larger area than the FS power rail.
Furthermore, the BS contact structures can be formed with smaller widths (e.g., about 5 nm to about 10 nm smaller than widths of the S/D regions) than FS contact structures, which require deeper etching of the S/D regions than the BS contact structures. Thus, electrically connecting the S/D regions to the BS power rail through the BS contact structures can reduce the loss of S/D regions during BS contact structure formation, thus improving device performance compared to that of devices with S/D regions electrically connected to FS power rails through FS contact structures.
In some embodiments, a semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers (104) disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.
In some embodiments, a semiconductor device includes first and second nanostructured channel regions, first and second gate structures surrounding the first and second nanostructured channel regions, respectively, an epitaxial region disposed between the first and second nanostructured channel regions, a pair of spacers disposed on opposite sidewalls of the epitaxial region, and a contact structure disposed on the epitaxial region and between the pair of spacers.
In some embodiments, a method includes forming a fin structure on a substrate, forming a superlattice structure having first and second nanostructured layers on a first fin region of the fin structure, forming first and second spacers on opposite sidewalls of the fin structure, forming an epitaxial region on a second fin region of the fin structure and between the first and second spacers, replacing a first portion of the fin structure with a conductive layer, and replacing a second portion of the fin structure with a dielectric layer.
The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Patent Application No. 63/404,899, titled “Spacer Structures and Contact Structures in Semiconductor Devices,” filed Sep. 8, 2022, and U.S. Provisional Patent Application No. 63/342,464, titled “Semiconductor Device Structure,” filed May 16, 2022, each of which is incorporated by reference in its entirety.
Number | Date | Country | |
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63404899 | Sep 2022 | US | |
63342464 | May 2022 | US |