Patent Application
20060170088
This disclosure relates generally to manufacturing techniques for semiconductor devices, and more particularly to novel spacer structures for stacked semiconductor package devices.
The packaging of integrated circuit (IC) chips is one of the most important steps in the manufacturing process, contributing significantly to the overall cost, performance and reliability of the packaged chip. As semiconductor devices reach higher levels of integration, packaging technologies, such as wirebonding, have become critical. Packaging of the IC chip accounts for a considerable portion of the cost of producing the device and failure of the package leads to costly yield reduction.
As semiconductor device sizes have decreased, the density of devices on a chip has increased, along with the size of the chip, thereby making the wirebonding of chips to other components more challenging. One of the problems that may lead to device failure is the integrity of the wirebond connections formed on the chip substrates. As chip sizes increase, the density of wirebond connections is also increased, which may result in a higher number of wirebond failures. In addition, since chip real estate is limited, the area for wirebonding the chip to other circuitry can only hold a given number of connections. Problems can also occur with the encapsulation of a finished stacked device, for example, having the encapsulating material flow evenly and adequately between the stacked substrates in the package device, as well as the spacers used to separate those substrates. Without proper flowing of the encapsulant, device operation and longevity may also suffer.
Disclosed are novel spacer structures for stacked semiconductor package devices. In addition, methods of manufacturing spacers and stacked semiconductor package devices having such spacers are also disclosed. In one embodiment, a spacer includes a first mounting surface couplable to a longitudinal face of a first substrate, where the first mounting surface has a first surface area. The spacer also includes a second mounting surface substantially parallel to the first mounting surface and located on an opposing side of the spacer from the first mounting surface. Furthermore, the second mounting surface is couplable to a longitudinal face of a second substrate and has a second surface area larger than the first surface area.
In such embodiments, the smaller surface area of the first (e.g., lower) mounting surface of such a spacer, which is mounted to one side of an active substrate, permits wirebond connections to be made on a larger portion of the upper surface of that substrate, since less of the substrate's upper surface is covered by the spacer. In addition, such package device spacers may also allow for increased thermal transfer among interlevel substrates by covering up less surface area of the substrates, and thus allowing heat to escape directly from a substrate to the surrounding ambient, which is typically a dielectric encapsulant material. Still further, the larger upper mounting surface of the spacer provides beneficial overhang support for a mounted substrate, particularly in embodiments where the upper mounting surface has a surface area that is substantially equal with a surface area of the substrate.
In another embodiment, a spacer includes a first mounting surface couplable to a longitudinal face of a first substrate, and a second mounting surface substantially parallel to the first mounting surface and located on an opposing side of the spacer from the first mounting surface. In such embodiments, the second mounting surface is couplable to a longitudinal face of a second substrate. Also in this embodiment of the spacer, a footprint of the first or second mounting surface is formed as substantially non-rectilinear. In such embodiments, by providing substrate spacers having non-rectilinear footprints on their mounting surfaces in stacked semiconductor package devices, the encapsulating process used to seal such devices is improved. For example, pockets in the encapsulant material are less likely to form near or around the sharp corners found in conventional rectilinear-shaped spacer footprints. Thus, gases may be avoided that could form in such pockets, as well as other results that may threaten device operation or longevity.
As shown in
As discussed with respect to
Once the stacked semiconductor device 200 has been constructed using spacers 100A, 100B as disclosed herein, the stacked device 200 may then be mounted on another structure, such as a printed circuit board (PCB) 135. As shown, mounting the stacked device 200 to the PCB 135 may be accomplished using conventional flip-chip techniques, if desired. By constructing the stacked semiconductor device 200 using spacers 100A, 100B constructed according to the disclosed principles, the resulting device 200 contains significant advantages over conventional stacked semiconductor package devices.
As is shown in
Additionally, spacers constructed in accordance with the disclosed principles also offer improved heat-spreading capabilities within stacked semiconductor package devices. More specifically, as the semiconductor substrate, which are typically integrated circuits chips, are operated within the completed package device, the substrates themselves begin to generate more and more heat. Even in conventional devices, the spacers between such substrates are typically constructed from dielectric materials, such as silicon, that are capable of transferring heat away from the interlevel substrates (e.g., 120, 125, 130). However, package device spacers constructed as disclosed herein allow for increased thermal transfer among the interlevel substrates 120, 125, 130 by covering less surface area of the substrates 120, 125 with the first mounting surfaces of the spacers 100A, 100B. As a result, not only may heat be transferred from lower substrates (e.g., 120) up through the spacers 100A, 100B and out to the top of the device 200, but use of spacers constructed as disclosed herein also allows larger upper surface areas of the interlevel substrates 120, 125, 130 to remain uncovered by a spacer and therefore more readily capable of transferring heat into the surrounding ambient.
Still further, all of these benefits are provided by a disclosed package spacer, in addition to the overhang support offered for an interlevel substrate by providing a mounting surface that is substantially equal in surface area with the supported substrate. Such overhang support is provided by constructing the spacer with tapered transitional sides from its bottom surface to its top surface, as discussed above. In the embodiments illustrated in
In this illustrated embodiment, the lower spacers 100A, 100C of the package devices 200, 300 have been constructed such that they laterally extend towards each other and thus connect the first and second package devices 200, 300. By adjoining the edges of the first spacers 100A, 100C of the package devices 200, 300, another substrate 145, such as another IC chip, may also be coupled to the second (upper) surfaces of these lower spacers 100A, 100C. Moreover, since the overall surface area of the footprints of the first mounting surfaces of the spacer 100A, 100C are substantially smaller than that of the second mounting surfaces of the lower spacers 100A, 100C, active areas of the bottom interlevel substrates are still available to receive wirebond connections (e.g., as illustrated by wirebond connections 150). In short, the embodiment illustrated in
However, since conventional spacers typically have rectilinear footprints when viewed from above, pockets may form in the encapsulant as it flows around the rectilinear corners of a conventional spacer. In contrast, the novel spacer 410 illustrated in
For example, looking briefly at
By providing substrate spacers in stacked semiconductor package devices having non-rectilinear footprints, the encapsulating process used to seal such devices is improved. For example, pockets in the encapsulant material are less likely to form near or around the sharp corners found in conventional rectilinear-shaped spacer footprints. Moreover, in some embodiments, by eliminating the rectilinear footprint of the spacer an increase in exposed substrate surface area is provided, which may then provide increased surface area for wirebonding connections as discussed in detail above. As with all the spacers described herein, spacers 410, 510 in
Although the above description sets forth advantages relative to certain prior art implementations, these examples and their performance specifications should not be construed in any way as limitations on the invention or inventions disclosed. The scope of coverage for any patent that issues shall be defined by the claims that any such patent contains. It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and ranges of equivalents thereof are intended to be embraced therein.
Additionally, the section headings herein are provided for consistency with the suggestions under 37 C.F.R. §1.77 or otherwise to provide organizational cues. These headings shall not limit or characterize the invention(s) set out in any claims that may issue from this disclosure. Specifically and by way of example, although the headings refer to a “Technical Field,” the claims should not be limited by the language chosen under this heading to describe the so-called technical field. Further, a description of a technology in the “Background” is not to be construed as an admission that technology is prior art to any invention(s) in this disclosure. Neither is the “Summary of the Invention” to be considered as a characterization of the invention(s) set forth in the claims found herein. Furthermore, any reference in this disclosure to “invention” in the singular should not be used to argue that there is only a single point of novelty claimed in this disclosure. Multiple inventions may be set forth according to the limitations of the multiple claims associated with this disclosure, and the claims accordingly define the invention(s), and their equivalents, that are protected thereby. In all instances, the scope of the claims shall be considered on their own merits in light of the specification, but should not be constrained by the headings set forth herein.
