Patent Application
20200111758
One or more aspects of the present disclosure generally relate to device packaging, and in particular, to split pad for package routing and electrical performance improvement.
Interconnect features and design rules, such as line/space (US) and via size requirements, are getting tighter as package sizes are reduced. While helpful in decreasing the overall sizes of packages, the decreasing feature sizes come with their own issues. For example, a ball grid array (BGA) for a package can have a 0.35 mm pitch with 220 μm BGA pad, which are considerably large features compared to 10/10 μm US and 65 μm via pad. This means that each BGA pad itself can occupy more space on the final connection layer, which leaves less space to route traces and vias on this layer. This puts major restriction on the final connection layer for routing.
This summary identifies features of some example aspects, and is not an exclusive or an exhaustive description of the disclosed subject matter. Whether features or aspects are included in, or omitted from this summary is not intended as indicative of relative importance of such features. Additional features and aspects are described, and will become apparent to persons skilled in the art upon reading the following detailed description and viewing the drawings that form a part thereof.
An exemplary apparatus is disclosed. The apparatus may be selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and an automotive vehicle. The apparatus may include an inner connection layer, an outer connection layer on and above the inner connection layer, and one or more interconnects on and above the outer connection layer. The outer connection layer may include an outer substrate and an outer redistribution layer (RDL). The outer RDL may be within the outer substrate and on a top surface of the inner connection layer, and may include a plurality of split pads and one or more through-traces. First and second split pads of the plurality of split pads may be electrically coupled to a same interconnect of the one or more interconnects. At least one through-trace of the one or more through-traces may vertically overlap the same interconnect and may be laterally in between the first and second split pads.
An exemplary method is disclosed. The method may include forming an inner connection layer, forming an outer connection layer on and above the inner connection layer, and forming one or more interconnects on and above the outer connection layer. Forming the outer connection layer may include forming an outer substrate and forming an outer redistribution layer (RDL) within the outer substrate and on a top surface of the inner connection layer. The outer RDL may be formed to include a plurality of split pads and one or more through-traces. First and second split pads of the plurality of split pads may be formed so as to electrically couple to a same interconnect of the one or more interconnects. At least one through-trace of the one or more through-traces may be formed so as to vertically overlap the same interconnect and be laterally in between the first and second split pads.
Another exemplary apparatus is disclosed. The apparatus may include a die connected to a package board. The package board may include an inner connection layer, an outer connection layer on and above the inner connection layer, and one or more interconnects on and above the outer connection layer. The one or more interconnects may be electrically connected to one or more die pins of the die. The outer connection layer may include an outer substrate and an outer redistribution layer (RDL). The outer RDL, which may be within the outer substrate and on a top surface of the inner connection layer, may include a plurality of split pads and one or more through-traces. First and second split pads of the plurality of split pads may be electrically coupled to a same interconnect of the one or more interconnects. At least one through-trace of the one or more through-traces may vertically overlap the same interconnect and may be laterally in between the first and second split pads.
Yet another exemplary apparatus is disclosed. The apparatus may include an inner connection layer, an outer connection layer on and above the inner connection layer, and one or more interconnects on and above the outer connection layer. The outer connection layer may include an outer substrate and an outer redistribution layer (RDL). The outer RDL, which may be within the outer substrate and on a top surface of the inner connection layer, may include a plurality of means for providing a split connection and one or more means for providing a through-signal-connection. The plurality of means for providing the split connection may include means for providing a first split connection, and means for providing a second split connection. The means for providing the first split connection and the means for providing the second split connection may be electrically coupled to a same interconnect of the one or more interconnects. At least one of the means for providing the through-signal-connection may vertically overlap the same interconnect and may be laterally in between the first and second split pads.
The accompanying drawings are presented to aid in the description of examples of one or more aspects of the disclosed subject matter and are provided solely for illustration of the examples and not limitation thereof:
Aspects of the subject matter are provided in the following description and related drawings directed to specific examples of the disclosed subject matter. Alternates may be devised without departing from the scope of the disclosed subject matter. Additionally, well-known elements will not be described in detail or will be omitted so as not to obscure the relevant details.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments” does not require that all embodiments of the disclosed subject matter include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, processes, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, processes, operations, elements, components, and/or groups thereof.
Further, many examples are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer-readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the examples described herein, the corresponding form of any such examples may be described herein as, for example, “logic configured to” perform the described action.
Recall that in conventional panel level packaging, the BGA pad itself can occupy more space on the final connection layer. This leaves less space to route traces and vias, and thus puts major restriction on the final connection layer for routing.
The bent traces 125 are bent due to the presence of the pads 130. There are several disadvantages. As indicated above, one disadvantage is that the pad 130 can have considerably large features leaving less space to route the traces 122, 125 and vias (not shown), i.e., there can be a major restriction for routing. Another disadvantage is the bent traces 125 have increased length, which correspondingly increases signal propagation delay. Further, due to the large size of the pads 130, there can be an increase in the coupling effect.
To address one or more issues associated with the conventional package board, it is proposed to split the pad into two or more sub-pads to allow for more efficient routing on at least the final-i.e., the outermost-connection layer of a package board. It should be noted that while terms such as “upper”, “lower”, “left”, “right”, “top”, “bottom”, etc. are used in this disclosure, they should not be taken as defining absolute orientations. Rather, they should be taken simply as terms of convenience to indicate relative locations and orientations of the described components.
The split pads 230 may serve as contact pads for interconnects for external connection. In this way, the package board 300 may connect with other package boards and devices external to the package board. The traces 222 and the through-traces 225 may be configured to carry power, ground, and data signals. The outer connection layer may also include an outer substrate (not shown in
As will be shown further below, two or more (i.e., multiple) split pads 230 may be electrically coupled to each other. To state it another way, each split pad 230 may be electrically coupled to at least one other split pad 230. For illustration purposes, two of the split pads 230 are labeled in
One significant difference (not necessarily the only difference) between the proposed outer connection layer of
The following are some (not necessarily exhaustive) of the advantages of the proposed package boards. Mechanically, the routing may be simplified as compared to the conventional final connection layer. Also, the through-traces 225 can occupy less space than the conventional bent traces 125. Further, the through-traces 225 in general can have less bends and trace length.
There are also electrical advantages. One electrical advantage is that shielding may be provided for high speed signals. For example, in
Another electrical advantage is that unwanted coupling effect can be reduced. Note that in an aspect, the sizes of the first and second split pads 230A, 230B combined can still be smaller than the size of a single pad 130 of the conventional final connection layer. The reduced pad sizes can effectively reduce capacitive coupling that takes place.
The outer connection layer 320 may include an outer substrate 235 and an outer RDL within the outer substrate 235. The outer substrate 235 may be formed from electrically insulating materials such as dielectrics. The outer RDL may be below a top surface of the outer connection layer 320 and on the top surface of the inner connection layer 340. For example, the outer RDL may directly contact the top surface of the inner connection layer 340. The outer RDL may include any number of the split pads 230, the through-traces 225, and the traces 222. The outer RDL may be formed from conductive materials such as metal (e.g., copper).
Bottom surfaces of the outer substrate 235 and the outer RDL may together define a bottom surface of the outer connection layer 320. That is, the bottom surfaces of the outer substrate 235, the split pads 230, the through-traces 225, and the traces 222 may define the bottom surface of the outer connection layer 320. The outer RDL then may be viewed as vertically extending from the bottom surface of the outer connection layer 320 to a height below the top surface of the outer connection layer 320. In an aspect, the bottom surface of the outer connection layer 320 may be planar, i.e., the bottom surface of the outer substrate 235 may be planar with the bottom surfaces of the split pads 230, the through-traces 225, and the traces 222.
Recall from the discussion above with respect to
Also recall that the through-traces 225 may be laterally in between the electrically coupled split pads 230. This is also illustrated in
The inner connection layer 340 may include an inner substrate 345 and an inner RDL within the inner substrate 345. The inner substrate 345 may be formed from electrically insulating materials such as dielectrics. The inner RDL may be below the top surface of the inner connection layer 340. The inner RDL may include any number of inner traces 342 and any number of inner connection pads 344. The inner RDL may be formed from conductive materials such as metal (e.g., copper).
Bottom surfaces of the inner substrate 345 and the inner RDL may together define a bottom surface of the inner connection layer 340. That is, the bottom surfaces of the inner substrate 345, the inner traces 342, and the inner connection pads 344 may define the bottom surface of the inner connection layer 340. The inner RDL then may be viewed as vertically extending from the bottom surface of the inner connection layer 340 to a height below the top surface of the inner connection layer 340. In an aspect, the bottom surface of the inner connection layer 340 may be planar, i.e., the bottom surface of the inner substrate 345 may be planar with the bottom surfaces of the inner traces 342, and the inner connection pads 344.
The inner connection layer 340 may also include any number of inner vias 343. The inner vias 343 may be formed on the inner connection pads 344 such that each inner via 343 is electrically coupled to its corresponding inner connection pad 344. For example, bottom surfaces of the inner vias 343 may be in physical contact with upper surfaces of the corresponding inner connection pads 344. The inner vias 343 may be formed from conductive materials such as metal (e.g., copper).
The inner vias 343 may also be electrically coupled to the split pads 230 of the outer connection layer 320. For example, in
For ease of description, the left two inner vias 343 may be referred to as first and second inner vias 343 in relation to the left interconnect 310. In this instance, it is seen that the first and second inner vias 343 are also electrically coupled to each other, e.g., at least through the left interconnect 310. If the left through-trace 225 is a high signal trace, then shielding can be provided by grounding the left interconnect 310, which in turn would ground the related first and second split pads 230, the first and second inner vias 343, and the corresponding inner connection pads 344. As seen in
It should be noted that it is not a requirement that every split pad 230 be connected to an inner via 343. That is, each split pad 230 may or may not be physically connected to an inner via 343 intentionally based on routing preferences. For example, as seen in
It is contemplated that there can be any number of inner connection layers. The example package board 300 of
The next inner connection layer 350 may include a next inner substrate 355 and a next inner RDL within the next inner substrate 355. The next inner substrate 355 may be formed from electrically insulating materials such as dielectrics. The next inner RDL may include any number of next inner traces 352 and any number of next inner connection pads 354. The next inner RDL may be formed from conductive materials such as metal (e.g., copper).
Bottom surfaces of the next inner substrate 355 and the next inner RDL may together define a bottom surface of the next inner connection layer 350. That is, the bottom surfaces of the next inner substrate 355, the next inner traces 352, and the next inner connection pads 354 may define the bottom surface of the next inner connection layer 350. The next inner RDL then may be viewed as vertically extending from the bottom surface of the next inner connection layer 350 to a height below the top surface of the next inner connection layer 350. In an aspect, the bottom surface of the next inner connection layer 350 may be planar, i.e., the bottom surface of the next inner substrate 355 may be planar with the bottom surfaces of the next inner traces 352, and the next inner connection pads 354.
The next inner connection layer 350 may also include any number of next inner vias 353. The next inner vias 353 may be formed on the next inner connection pads 354 such that each next inner via 353 is electrically coupled to its corresponding lower connection pad 354. For example, bottom surfaces of the next inner vias 353 may be in physical contact with top surfaces of the corresponding lower connection pads 354. The next inner vias 353 may be formed from conductive materials such as metal (e.g., copper).
The next inner vias 353 may also be electrically coupled to the inner connection pads 344 of the inner connection layer 340. For example, in
As seen in
As mentioned, routing at the outer connection layer 320 may be made simpler and more flexible due to the through-traces 225. The through-traces 225 can occupy less space than the conventional bent traces 125, and have less bends and trace length. Electrically, shielding may be provided. Also electrically, unwanted coupling effect can be minimized due to reduction in sizes of the split pads 230, the inner vias 343, and the inner connection pads 344.
Another electrical advantage is that unwanted coupling effect can be reduced. Note that in an aspect, the size of the first and second split pads 230A, 230B combined can still be smaller than the size of a single pad 130 of the conventional final connection layer. The reduced pad sizes can effectively reduce capacitive coupling that takes place.
It should be noted that the split pads 230 may take on a variety of patterns as illustrated in
While not specifically illustrated, it should be noted that any number (i.e., zero or more) through-traces 225 may be in the spacing between any two split pads. Also, the widths of the spacings need not be uniform, i.e., some spacings may be wider than others. Further, the spacings need not be limited to up/down and side/side orientations, i.e., they may be oriented in any angle. If under bump metallization (UBM) is used, then patterns like that of
Referring back to
It should be noted that not all illustrated blocks of
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and methods have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The methods, sequences and/or algorithms described in connection with the examples disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled with the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an aspect can include a computer-readable media embodying any of the devices described above. Accordingly, the scope of the disclosed subject matter is not limited to illustrated examples and any means for performing the functionality described herein are included.
While the foregoing disclosure shows illustrative examples, it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosed subject matter as defined by the appended claims. The functions, processes and/or actions of the method claims in accordance with the examples described herein need not be performed in any particular order. Furthermore, although elements of the disclosed subject matter may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
