TREA

Stacked field-effect transistor switch

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Information

  • Patent Grant
  • 10749518
  • Patent Number
    10,749,518
  • Date Filed
    Friday, November 17, 2017
    7 years ago
  • Date Issued
    Tuesday, August 18, 2020
    4 years ago
Information
Abstract
A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.
Description
FIELD OF THE DISCLOSURE

The present disclosure relates to reducing noise generated by a radio frequency (RF) switch that is in an on-state while passing an applied RF signal through the RF switch.


BACKGROUND

An important electronic component of a radio frequency (RF) transceiver is a field-effect transistor (FET) that makes up stacked FET-type RF switches. An RF switch that is FET based typically needs linearity compensation to prevent generation of harmonic distortion when transmit signals are applied to the RF switch while the RF switch is in an on-state. The RF switch is effectively closed while in the on-state, and the transmit signals pass through the RF switch. However, while the RF switch is closed, undesirable harmonics are generated from the transmit signals in part due to non-linear conductance inherent to the RF switch. The undesirable harmonics pass from the RF switch and interfere with the RF transceiver's receiver circuitry. What is needed is an RF switch that limits undesirable harmonics due to non-linear conductance.


SUMMARY

A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port between 10% and 99% of a first breakdown voltage of the first FET device stack. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port between 10% and 99% of a second breakdown voltage of the second FET device stack.


Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.





BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.



FIG. 1 is a schematic of a stacked field-effect transistor (FET) switch that is structured in accordance with the present disclosure.



FIG. 2 is a schematic of an embodiment of the stacked FET switch of FIG. 1 that employs N-channel FET devices for a first plurality of FET devices and P-channel FET devices for a second plurality of FET devices that are coupled in parallel with the first plurality of FET devices.



FIG. 3 is a schematic of an embodiment of the stacked FET switch of FIG. 1 that employs N-channel FET devices for both the first plurality of FET devices and the second plurality of FET devices that are coupled in parallel with the first plurality of FET devices.



FIG. 4 is a schematic of another embodiment of a stacked FET switch that in accordance with the present disclosure includes at least a third FET device stack added to a structure in common with the stacked FET switch of FIGS. 1-3.



FIG. 5 is a schematic of an embodiment of a stacked FET switch that in accordance with the present disclosure includes a second FET device stack having fewer FET devices added to a structure in common with the stacked FET switch of FIGS. 1-3.



FIG. 6 is a schematic of an embodiment of a stacked FET switch that in accordance with the present disclosure includes a third FET device stack with a third plurality of FET devices having an equal number of FET devices as the second plurality of FET devices.



FIG. 7 is a schematic of an embodiment of the stacked FET switch of FIG. 1 that employs a plurality of capacitors wherein each of the plurality of capacitors is coupled in parallel with a corresponding one of the second plurality of FET devices.



FIG. 8 is a graph of relative magnitude for on-state conductance for drift FETs, ballistic FETs, and stacked drift FETs coupled in parallel with ballistic FETs to illustrate linearization of the on-state conductance for the stacked FET switches of the present disclosure.



FIG. 9 is a graph depicting a well-compensated drift FET- and ballistic FET-based stacked FET switch such as realized by any of the exemplary stacked FET switches of the present disclosure in comparison to a traditional drift FET-based stacked FET switch.



FIG. 10 is a plot of harmonic distortion versus signal voltage for a drift FET-only-based stacked FET switch and a well-compensated drift FET—and ballistic FET-based stacked FET switch such as the exemplary embodiment of the FET-based switch of FIG. 2.



FIG. 11 is a cross-sectional view of the stacked FET switch 10 showing a device layer in which the first FET stack 16 (FIG. 1) is formed over a substrate.





DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.


It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.


It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.


Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.


The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.


Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.


For the purpose of this disclosure, a ballistic field-effect transistor (FET) is a semiconductor device having a gate, a source, a drain, and a channel between the source and the drain in which the length L of the channel is less than a mean-free-path λ that is the average distance between electron scattering events within the channel. Due to the relatively short channel length L compared with the mean-free-path λ, the ballistic FET has a characteristic of electron propagation between the source and the drain with practically no electron scattering due to collisions with phonons and/or channel defects while in a current-conducting state controlled by a control voltage applied to the gate. Further still, in accordance with the present disclosure, a ballistic FET has conductance within the channel that increases with increasing voltage between the source and the drain between 10% and 99% of a breakdown voltage of the ballistic FET. Moreover, a ballistic FET is a device in which at least 70% of carriers are transported ballistically. Further still, ballistic transport occurs when carriers have enough speed to generate a transition from the indirect band to the direct band. A new schematic symbol is used to identify ballistic FETs in the Figures of the present disclosure. The new symbol has an arrow pointing between the source and drain of a traditional FET symbol. The arrow denotes the ballistic carrier transport between the source and drain of the ballistic FET.


Also for the purpose of this disclosure, a drift FET is a traditional semiconductor device having a gate, a source, a drain, and a channel between the source and the drain in which the length L of the channel is greater than the mean-free-path λ that is the average distance between electron scattering events within the channel. Moreover, a drift FET is a device in which at least 50% of carriers are transported by drift.



FIG. 1 is a schematic of a stacked FET switch 10 that is structured in accordance with the present disclosure. The stacked FET switch 10 has a first port 12 and a second port 14. When in a closed state, the stacked FET switch 10 allows passing of radio frequency (RF) signals between the first port 12 and the second port 14. When in an open state, the stacked FET switch 10 prevents RF signals from passing between the first port 12 and the second port 14. In the exemplary embodiment of FIG. 1, the first port 12 is an RF input RFIN and the second port 14 is an RF output RFOUT. However, it is to be understood that either of the first port 12 or second port 14 may be considered an RF input or an RF output depending on which direction an RF signal is passing through the stacked FET switch 10.


The stacked FET switch 10 has a first FET device stack 16 that is operable in an on-state when the stacked FET switch 10 is in the closed state and in an off-state when the stacked FET switch 10 is in the open state. The first device FET stack 16 is made up of a first plurality of FET devices 18 coupled in series between the first port 12 and the second port 14. Each of the first plurality of FET devices 18 has a first current terminal 20, a second current terminal 22, and a control terminal 24. The first current terminal 20 and the second current terminal 22 are typically a drain terminal and a source terminal, respectively, and the control terminal 24 is typically a gate terminal. In the exemplary embodiment of FIG. 1, the drain terminal and the source terminal are interchangeable; hence the first current terminal 20 and the second current terminal 22 are not specifically designated as source and drain.


The first FET device stack 16 has an on-state conductance GON that decreases with increasing voltage between the first port 12 and the second port 14 between 10% and 99% of a first breakdown voltage of the first FET device stack 16. In other words, an on-state resistance typically referred to as RON increases for each of the first plurality of FET devices 18 with increasing voltage between the first port 12 and the second port 14.


At some point between 10% and 99% of the first breakdown voltage of the first FET device stack 16, the on-state conductance GON decreases non-linearly, which results in non-linear harmonic distortion. To limit the non-linear harmonic distortion, the stacked FET switch 10 includes a second FET device stack 26 that is operable in the on-state and in the off-state, the second FET device stack comprising a second plurality of FET devices 28 coupled in series between the first port and the second port and having a conductance that increases with increasing voltage between the first port and the second port between 10% and 99% of a second breakdown voltage of the second FET device stack 26.


The second FET device stack 26 is made up of a second plurality of FET devices 28 coupled in series between the first port 12 and the second port 14. Each of the second plurality of FET devices 28 has a third current terminal 30, a fourth current terminal 32, and a second control terminal 34. The third current terminal 30 and the fourth current terminal 32 are typically a drain terminal and a source terminal, respectively, and the second control terminal 34 is typically a gate terminal. Similar to the plurality of FET devices 18, the drain terminal and the source terminal are interchangeable; hence the third current terminal 30 and the fourth current terminal 32 are not specifically designated as source and drain in this exemplary embodiment. Also, in this exemplary embodiment, each of the first plurality of FET devices 18 is coupled in parallel with a corresponding one of the second plurality of FET devices 28. Specifically, first current terminal 20 and third current terminal 30 of opposing ones of the first plurality of FET devices 18 and the second plurality of FET devices 28 are coupled together. Moreover, the second current terminal 22 and the fourth current terminal 32 of opposing ones of the first plurality of FET devices 18 and the second plurality of FET devices 28 are coupled together.


The second FET device stack 26 has a compensating on-state conductance GON_COMP that increases with increasing voltage between the first port 12 and the second port 14 between 10% and 99% of the second breakdown voltage of the second FET device stack 26. In other words, the on-state resistance typically referred to as RON decreases for each of the second plurality of FET devices 28 with increasing voltage between the first port 12 and the second port 14. The compensating on-state conductance GON_COMP of the second FET device stack 26 counteracts the on-state conductance GON of the first FET device stack 16, which in turn limits generation of harmonic distortion with the stacked FET switch 10.


The compensating on-state conductance GON_COMP of the second FET device stack 26 is effective at limiting generation of harmonic distortion over design corners of process, supply voltage, and temperature. A maximum limitation of harmonic distortion may be achieved by providing appropriate values of direct current (DC) bias voltages to the gates of the first plurality of FET devices 18 and/or the second plurality of FET devices 28.


In this regard, a first bias circuitry 35 provides a DC bias voltage to the control terminals 24 of the first plurality of FET devices 18 through resistors R1 coupled between a first bias output terminal 36 and individual ones of the control terminals 24. There is one each of the resistors R1 for each of the control terminals 24. The resistors R1 typically have mega-ohm resistance values. A first gate control voltage VGATE1 for turning the first plurality of FET devices 18 from the off-state to the on-state may be applied to the first bias output terminal 36. Also included is a second bias circuitry 38 that provides a DC bias voltage to the second control terminals 34 of the second plurality of FET devices 28 through resistors R2 coupled between a second bias output terminal 40 and individual ones of the second control terminals 34. There is one each of the resistors R2 for each of the control terminals 24. The resistors R2 typically have mega-ohm resistance values. A second gate control voltage VGATE2 for turning the second plurality of FET devices 28 from the off-state to the on-state may be applied to the second bias output terminal 40. In some embodiments, the first bias circuitry 35 and/or the second bias circuitry 38 are configured to automatically adjust bias voltage level to track with changes in process, supply voltage, and temperature. In some embodiments, the first bias circuitry 35 is configured to generate a first bias voltage level that is different from a second bias voltage level generated by the second bias circuitry 38 in order to appropriately bias the first plurality of FET devices 18 and the second plurality of FET devices 28, which have different electrical characteristics that require different bias voltage levels for proper operation.


Maximum limiting of harmonic distortion may also be achieved by changing the device sizes of the second plurality of FET devices 28 relative to the device sizes of first plurality of FET devices 18. Effective device size may be adjusted by controlling how many transistor fingers of the second plurality of FET devices 28 are active. Alternatively, fixed device sizes for the second plurality of FET devices 28 relative to the device sizes of first plurality of FET devices 18 may be selected to maximize the limitation of harmonic distortion over an expected range of process, supply voltage, and temperature changes.


To achieve opposing on-state conductance GON and compensating on-state conductance GON_COMP, FET devices having opposing conductance characteristics are selected for the first plurality of FET devices 18 and the second plurality of FET devices 28, respectively. For the exemplary embodiments of the present disclosure, traditional drift FETs are selected for the first plurality of FET devices 18, and ballistic FET devices are selected for the second plurality of FET devices 28. At least 50% carrier transport of the first plurality of FET devices is drift transport, and at least 70% of carrier transport of the second plurality of FET devices is ballistic transport. As a result, ballistic FET devices have increasing conductance as voltage increases from source to drain between 10% and 99% of the breakdown voltage for individual ballistic FET devices. Exemplary channel lengths L for N-channel ballistic FET devices are between 22 nm and 3 nm, whereas N-channel drift FET devices have channel lengths L that are greater than 22 nm. In general P-channel FET devices are the first FET devices to exhibit ballistic transport of carriers with decreasing gate length. P-channel FET devices typically begin to exhibit quasi-ballistic transport at 45 nm due to crystal strain that influences hole mobility greater than electron mobility. It is to be understood that while the present disclosure employs ballistic FET devices in exemplary embodiments, it is envisioned that other types of FET devices having increasing conductance as voltage increases across source and drain between 10% and 99% of the breakdown voltage for individual FET devices may also be employable to compensate for the opposing conductance characteristic of traditional drift FET devices.



FIG. 2 is a schematic of an embodiment of the stacked FET switch 10 of FIG. 1 that employs N-channel FET devices for the first plurality of FET devices 18 and P-channel FET devices for the second plurality of FET devices 28. P-channel FET devices typically begin to exhibit quasi-ballistic transport at 45 nm due to crystal strain that influences hole mobility greater than electron mobility. In at least one embodiment, the P-channel FET devices are germanium doped to enhance carrier mobility in comparison to P-channel silicon metal oxide semiconductor FETs. In some embodiments, the P-channel FET devices have a germanium-strained silicon structure. It is to be understood that drift-mode P-channel FET devices may be used for the first plurality of FET devices 18 while ballistic-mode N-channel FET devices are used for the second plurality of FET devices 28.



FIG. 3 is a schematic of an embodiment of the stacked FET switch 10 of FIG. 1 that employs N-channel FET devices for both the first plurality of FET devices 18 and the second plurality of FET devices 28. However, the N-channel FET devices making up the first plurality of FET devices 18 have channel lengths that are long enough to operate in the drift mode, whereas the N-channel FET devices making up the second plurality of FET devices 28 have channel lengths short enough to operate in the ballistic mode.



FIG. 4 is a schematic of an embodiment of a stacked FET switch 42 that in accordance with the present disclosure includes at least a third FET device stack 44 added to a structure in common with the stacked FET switch 10 of FIGS. 1-3. The third FET device stack 44 is made up of a third plurality of FET devices 46 coupled in series between the first port 12 and the second port 14. Each of the third plurality of FET devices 46 has a fifth current terminal 48, a sixth current terminal 50, and a third control terminal 52. The fifth current terminal 48 and the sixth current terminal 50 are typically a drain terminal and a source terminal, respectively, and the third control terminal 52 is typically a gate terminal. Also, in this exemplary embodiment of FIG. 4, each of the first plurality of FET devices 18 is coupled in parallel with a corresponding one of the second plurality of FET devices 28 and a corresponding one of the third plurality of FET devices 46. Specifically, first current terminal 20, the third current terminal 30, and the fifth current terminal 48 of opposing ones of the first plurality of FET devices 18, the second plurality of FET devices 28, and the third plurality of FET devices 46, respectively, are coupled together. Moreover, the second current terminal 22, the fourth current terminal 32, and the sixth current terminal 50 of opposing ones of the first plurality of FET devices 18, the second plurality of FET devices 28, and the third plurality of FET devices 46, respectively, are coupled together.


The addition of the third FET device stack 44 provides piecewise linearization compensation of the non-linear conduction characteristic of the first FET device stack 16. Moreover, additional FET stacks coupled in parallel with the third FET stack 44 may provide more degrees of freedom for piecewise linearization compensation of the non-linear conduction characteristic of the first FET device stack 16.


The second bias circuitry 38 provides a DC bias voltage to the third control terminals 52 of the third plurality of FET devices 46 through resistors R3 coupled between the second bias output terminal 40 and individual ones of the third control terminals 52. There is one each of the resistors R3 for each of the third control terminals 52. The resistors R3 typically have mega-ohm resistance values. The second gate control voltage VGATE2 is also for turning the second plurality of FET devices 28 from the off-state to the on-state. As with the stacked FET switch 10, in some embodiments, the first bias circuitry 35 and/or the second bias circuitry 38 are configured to automatically adjust bias voltage to track with changes in process, supply voltage, and temperature for the stacked FET switch 42. While the third plurality of FET devices 46 is depicted as comprising N-channel ballistic FETs, the third plurality of FET devices 46 may also comprise P-channel ballistic FETs.



FIG. 5 is a schematic of an embodiment of a stacked FET switch 54 that in accordance with the present disclosure includes a second FET device stack 56 added to a structure in common with the stacked FET switch 10 of FIGS. 1-3. In this exemplary embodiment, the second FET device stack 56 has a second plurality of FET devices 58 that has half as many FETs as the first plurality of FET devices 18. The second plurality of FET devices 58 is coupled in series between the first port 12 and the second port 14. Each of the second plurality of FET devices 58 has a third current terminal 60, a fourth current terminal 62, and a second control terminal 64. In this exemplary embodiment, there is one of the second plurality of FET devices 58 coupled in parallel across for every two of the first plurality of FET devices 18. Specifically, the first current terminal 20 and third current terminal 60 of every other opposing ones of the first plurality of FET devices 18 and the second plurality of FET devices 58 are coupled together. Moreover, the second current terminal 22 and the fourth current terminal 62 of every other opposing ones of the first plurality of FET devices 18 and the second plurality of FET devices 58 are coupled together. A benefit of having fewer FET devices in the second FET device stack 56 is that a larger voltage across each of the second plurality of FET devices 58 results in a carrier mobility increase.



FIG. 6 is a schematic of an embodiment of a stacked FET switch 66 that in accordance with the present disclosure includes a third FET device stack 68 with a third plurality of FET devices 70 having an equal number of FET devices as the second plurality of FET devices 58. In this exemplary embodiment, there is one of the third plurality of FET devices coupled in parallel across for every two of the first plurality of FET devices 18 beginning with two of the first plurality of FET devices 18 closest to the second port 14. As alluded to in the description of the embodiment of FIG. 5, a benefit of having fewer FET devices in the third FET device stack 68 is that a larger voltage across each of the third plurality of FET devices 70 results in a carrier mobility increase. However, the stacked FET switch 66 has an additional benefit of increased current handling due to the addition of the third FET device stack 68.



FIG. 7 is a schematic of an embodiment of the stacked FET switch 10 of FIG. 1 that employs a plurality of capacitors C1 wherein each of the plurality of capacitors C1 is coupled in parallel with a corresponding one of the second plurality of FET devices 28. The plurality of capacitors C1 stabilize the parasitic capacitances of the first plurality of FET devices 18 and the second plurality of FET devices 28 such that a total capacitance value for the stacked FET switch 10 deviates by no more ±5% while the stacked FET switch 10 is in an open state. In at least one embodiment, each of the plurality of capacitors C1 is a metal-insulator-metal type capacitor or a metal-oxide-metal type capacitor.



FIG. 8 is a graph of relative magnitude for on-state conductance for drift FETs, ballistic FETs, and stacked drift FETs coupled in parallel with ballistic FETs to illustrate linearization of the on-state conductance for the stacked FET switches of the present disclosure. The next-to-bottom curve depicted in medium dashed line depicts on-state conductance for a ballistic FET biased at a first bias voltage VG1. The bottom curve depicted in short dashed line depicts on-state conductance for a ballistic FET biased at a second bias voltage VG2. Notice that the on-state conductance increases as RF signal voltage VRF increases. This increase is opposed to the on-state conductance decrease with increasing RF signal voltage. Notice that the top curve depicted in long dashed line has decreasing conductance with increasing RF signal voltage. A curve second from the top depicted in thick dot-dash line represents an undercompensated result for a drift FET- and ballistic FET-based stacked FET switch. The compensation is improved by adjusting the bias voltage to the ballistic FETs making up the stacked FET switch. The solid curve depicts a well-compensated drift FET- and ballistic FET-based stacked FET switch such as that realized by any of the exemplary stacked FET switches of the present disclosure. The thinner dot-dashed line just below the solid curve depicts drain-to-source conductance GDS for a drift FET.



FIG. 9 is a graph depicting a well-compensated drift FET- and ballistic FET-based stacked FET switch such as that realized by any of the exemplary stacked FET switches of the present disclosure in comparison to a traditional drift FET-based stacked FET switch. In this particular case, the well-compensated drift FET- and ballistic FET-based stacked FET switch is made up of N-channel FETs and P-channel FETs, and the traditional drift FET-based stacked FET switch is made up of only N-channel FETs.



FIG. 10 is a plot of harmonic distortion versus signal voltage for a drift FET-only-based stacked FET switch and a well-compensated drift FET- and ballistic FET-based stacked FET switch such as the exemplary embodiment of the stacked FET switch 10 of FIG. 2. In this case, linearization provided by the stacked FET switch 10 of FIG. 2 decreases harmonic distortion by 24 dB. Harmonic distortion can even be further reduced by substrate selection for the stacked FET switch 10.


In this regard, FIG. 11 is a cross-sectional view of the stacked FET switch 10 showing a device layer 78 in which the first FET device stack 16 (FIG. 1) and the second FET device stack 26 reside. A substrate 80 supports the device layer 78. A buried oxide layer 82 may be an etch stop layer that is interfaced directly with and between both the device layer 78 and the substrate 80. In some embodiments, the substrate 80 is made of a polymeric material such as thermoplastic or epoxy. However, it is to be understood that other embodiments of the present disclosure remain functional on typical high-resistance semiconductor substrates such as silicon. Thus, in at least some embodiments, the stacked FET switch 10 is of the silicon-on-insulator type in which high-resistance silicon substrates are employed. Nevertheless, there are benefits to replacing the typical high-resistance semiconductor substrates with a substrate made of polymeric material. For example, polymeric material has electrical properties that provide superior isolation during operation and prevent harmonics from being generated within the substrate 80. Moreover, additives such as nanopowders may be included in the polymeric material to increase thermal conductivity of the stacked FET switch 10.


Semiconductor substrates may be replaced with polymeric substrates using techniques disclosed in U.S. Patent Publication Nos. 20140252566 A1, 20140306324 A1, 20150255368 A1, now issued as U.S. Pat. No. 9,812,350, 20160079137 A1, now issued as U.S. Pat. No. 9,824,951, 20160100489 A1 now issued as U.S. Pat. No. 10,085,352, 20160126196 A1 now issued as U.S. Pat. No. 10,121,718, 20160343604 A1, 20160343592 A1 now issued as U.S. Pat. No. 9,860,145, 20170032957 A1 now issued as U.S. Pat. No. 10,062,637, 20170098587 A1 now issued as U.S. Pat. No. 10,199,301, 20170271200 A1 now issued as U.S. Pat. No. 10,134,627, and 20170309709 A1 now issued as U.S. Pat. No. 10,038,055; U.S. Pat. Nos. 9,214,337, 9,583,414, and 9,613,831; and U.S. patent application Ser. No. 15/353,346, filed Nov. 16, 2016, now issued as U.S. Pat. No. 10,103,080, titled THERMALLY ENHANCED SEMICONDUCTOR PACKAGE WITH THERMAL ADDITIVE AND PROCESS FOR MAKING THE SAME; U.S. patent application Ser. No. 15/491,064, filed Apr. 19, 2017, now issued as U.S. Pat. No. 10,068,831, titled THERMALLY ENHANCED SEMICONDUCTOR PACKAGE AND PROCESS FOR MAKING THE SAME; U.S. patent application Ser. No. 15/498,040, filed Apr. 26, 2017, now issued as U.S. Pat. No. 10,109,502titled SEMICONDUCTOR PACKAGE WITH REDUCED PARASITIC COUPLING EFFECTS AND PROCESS FOR MAKING THE SAME; U.S. patent application Ser. No. 15/601,858, filed May 22, 2017, titled WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE; U.S. patent application Ser. No. 15/695,579, filed Sep. 5, 2017, titled MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY; and U.S. patent application Ser. No. 15/695,629, filed Sep. 5, 2017, now issued as U.S. Pat. No. 10,366,972, titled MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY, which are hereby incorporated by reference in their entireties. Some of the disclosed substrate replacement techniques are applied at a die-level process, whereas others are applied during a wafer-level process.


Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims
  • 1. A stacked field-effect transistor (FET) switch comprising: a first FET device stack that is operable in an on-state and in an off-state, the first FET device stack comprising a first plurality of FET devices coupled in series between a first port and a second port and having a first on-state conductance that decreases with increasing voltage between the first port and the second port between 10% and 99% of a first breakdown voltage of the first FET device stack when the first FET device stack is in the on-state; anda second FET device stack that is operable in the on-state and in the off-state, the second FET device stack comprising a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack is configured to have a second on-state conductance that increases with increasing voltage between the first port and the second port between 10% and 99% of a second breakdown voltage of the second FET device stack to compensate for decreasing of the first on-state conductance when both the first FET device stack and the second FET device stack are in the on-state.
  • 2. The stacked FET switch of claim 1 wherein the second plurality of FET devices comprises ballistic FET devices.
  • 3. The stacked FET switch of claim 1 wherein the first plurality of FET devices comprises N-channel FET devices and the second plurality of FET devices comprises P-channel FET devices.
  • 4. The stacked FET switch of claim 3 wherein the P-channel FET devices are germanium doped to enhance carrier mobility.
  • 5. The stacked FET switch of claim 1 wherein the first plurality of FET devices comprises N-channel FET devices and the second plurality of FET devices comprises N-channel FET devices.
  • 6. The stacked FET switch of claim 1 wherein each of the first plurality of FET devices is coupled in parallel with a corresponding one of the second plurality of FET devices.
  • 7. The stacked FET switch of claim 1 further comprising a plurality of capacitors wherein each of the plurality of capacitors is coupled in parallel with a corresponding one of the second plurality of FET devices such that parasitic capacitances of the first plurality of FET devices and the second plurality of FET devices cause a total capacitance of the stacked FET switch to deviate by no more ±5% while the stacked FET switch is in an open state.
  • 8. The stacked FET switch of claim 7 wherein the plurality of capacitors comprises metal-insulator-metal type capacitors.
  • 9. The stacked FET switch of claim 1 further comprising a first bias circuitry having a first output coupled to first control terminals of the first plurality of FET devices and a second bias circuitry having a second bias output coupled to second control terminals of the second plurality of FET devices.
  • 10. The stacked FET switch of claim 9 wherein the first bias circuitry and the second bias circuitry are each configured to automatically adjust bias voltage level to track with changes in supply voltage.
  • 11. The stacked FET switch of claim 9 wherein the first bias circuitry and the second bias circuitry are each configured to automatically adjust bias voltage level to track with changes in temperature.
  • 12. The stacked FET switch of claim 9 wherein the first bias circuitry and the second bias circuitry are each configured to automatically adjust bias voltage level to track with changes in supply voltage and changes in temperature.
  • 13. The stacked FET switch of claim 9 wherein the first bias circuitry is configured to generate a first bias voltage level that is different from a second bias voltage level generated by the second bias circuitry.
  • 14. The stacked FET switch of claim 1 wherein the second plurality of FET devices comprises fewer FET devices than the first plurality of FET devices.
  • 15. The stacked FET switch of claim 14 wherein there is one FET device of the second plurality of FET devices coupled in parallel across for every two FET devices of the first plurality of FET devices beginning with two FET devices of the first plurality of FET devices closest to the first port.
  • 16. The stacked FET switch of claim 15 further including a third plurality of FET devices having an equal number of FET devices as the second plurality of FET devices, wherein there is one FET device of the third plurality of FET devices coupled in parallel across for every two FET devices of the first plurality of FET devices beginning with two FET devices of the first plurality of FET devices closest to the second port.
  • 17. The stacked FET switch of claim 1 wherein the first plurality of FET devices and the second plurality of FET devices are of the silicon-on-insulator type.
  • 18. The stacked FET switch of claim 1 further comprising: a polymeric substrate; anda device layer within which the first FET device stack and the second FET stack reside, wherein the device layer is directly supported by the polymeric substrate.
  • 19. The stacked FET switch of claim 1, wherein at least 50% carrier transport of the first plurality of FET devices is drift transport and at least 70% of carrier transport of the second plurality of FET devices is ballistic transport.
  • 20. The stacked FET switch of claim 1 wherein the physical size of the second plurality of FET devices is different from the physical size of the first plurality of FET devices.
  • 21. The stacked FET switch of claim 1 wherein each of the first plurality of FET devices has a first number of gate fingers and each of the second plurality of FET devices has a second number of gate fingers that is different in number from the first number of gate fingers.
RELATED APPLICATIONS

This application claims the benefit of provisional patent application Ser. No. 62/423,815, filed Nov. 18, 2016, the disclosure of which is hereby incorporated herein by reference in its entirety.

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Related Publications (1)
Number Date Country
20180145678 A1 May 2018 US
Provisional Applications (1)
Number Date Country
62423815 Nov 2016 US