1. Field of the Invention
The present invention relates to an integrated circuit chip package, and more particularly, to a stacked flash memory chip package and a method for the stacked flash memory chip package.
2. Description of Related Art
An integrated circuit chip is generally encapsulated in a package to protect the chip and facilitate the carry and handle of the integrated circuit.
To improve the density of the integrated circuit package, a package design which encapsulates two chips 111 and 112 in a stacked form is provided as illustrated in
Therefore, it is desirable to provide an improved stacked flash memory chip package and a method for the stacked flash memory chip package to mitigate and/or obviate the aforementioned problems.
A primary object of the present invention is to provide a stacked flash memory chip package and a method for the stacked flash memory chip package so as to present a low-cost and high-density chip package.
According to one aspect of the present invention, a method for stacked flash memory chip package provided by the present invention comprises the steps of: (A) providing a substrate having predetermined circuit; (B) mounting a first flash memory chip on the substrate, in which the first flash memory chip has an inactive surface for adhering to the substrate and a number of bond pads of the flash memory chip are all disposed on one side of an active surface of the first flash memory chip; (C) mounting a second flash memory chip on the first memory chip in a non-alignment manner so that the second flash memory chip shields only part of the active surface of the first flash memory chip and that the bond pads of the first flash memory chip are exposed, in which the second flash memory chip has an inactive surface for adhering to the first flash memory chip and a number of bond pads of the second flash memory chip are all disposed on one side of an active surface of the second flash memory chip; and (D) connecting the bond pads of the first flash memory chip and the bond pads of the second flash memory chip respectively to the circuit of the substrate by wire bonding.
According to another aspect of the present invention, a stacked flash memory chip package provided by the present invention comprises: a substrate having predetermined circuit; a first flash memory chip mounted on the substrate, in which the first flash memory chip has an inactive surface for adhering to the substrate and a number of bond pads of the flash memory chip are all disposed on one side of an active surface of the first flash memory chip; a second flash memory chip mounted on the first flash memory chip in a non-alignment manner so that the second flash memory chip shields only part of the active surface of the first flash memory chip and that the bond pads of the first flash memory chip are exposed, in which the second flash memory chip has an inactive surface for adhering to the first flash memory chip and a number of bond pads of the second flash memory chip are all disposed on one side of an active surface of the second flash memory chip; and bonding wires for connecting the bond pads of the first flash memory chip and the bond pads of the second flash memory chip respectively to the circuit of the substrate.
According to a further aspect of the present invention, a method for stacked flash memory chip package provided by the present invention comprises the steps of: (A) providing a substrate having predetermined circuit, in which part of the circuit are disposed at the inner periphery of the substrate and the other circuit are disposed at the outer periphery of the substrate; (B) mounting a control chip on the substrate, in which the control chip has a number of bond pads; (C) connecting the bond pads of the control chip to the circuit disposed at the inner periphery of the substrate by wire bonding; (D) filling an encapsulant into the substrate where the control chip is mounted to encapsulate the control chip and the bonding wires without shielding the circuit disposed at the outer periphery of the substrate, and then, curing the encapsulant; (E) mounting a flash memory chip on the encapsulant being cured, in which the flash memory chip has a number of bond pads; (F) connecting the bond pads of the flash memory chip to the circuit disposed at the outer periphery of the substrate by wire bonding; and (G) encapsulating the flash memory chip and the bonding wires with an encapsulant, and then, curing the encapsulant to become an integrated circuit package.
According to another aspect of the present invention, a stacked flash memory chip package provided by the present invention comprises: a substrate having predetermined circuit, in which part of the circuit are disposed at the inner periphery of the substrate and the other circuit are disposed at the outer periphery of the substrate; a control chip mounted on the substrate, in which the control chip has a number of bond pads; a flash memory chip mounted on the control chip, in which the flash memory chip has a number of bond pads; bonding wires for connecting not only the bond pads of the control chip to the circuit disposed at the inner periphery of the substrate but also the bond pads of the flash memory chip to the circuit disposed at the outer periphery of the substrate; and an encapsulant for encapsulating the control chip, the flash memory chip and the bonding wires.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
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In the aforesaid integrated circuit package, the size is reduced because the first and second flash memory chips are stacked. Furthermore, because the bond pads 306, 308 of the first and second flash memory chips 305, 307 are oriented in the same direction (on the opposite side of the respective chips facing the substrate 301), it is easy for the bonding wires 309 to electrically connect the first and second flash memory chips 305, 307 to the substrate 301, dispensing with the need of a flip chip. Hence, the fabricating cost is effectively reduced.
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In the aforesaid integrated circuit package, the size is reduced because the control chip 405 and the flash memory chip 407 are stacked. Furthermore, the flash memory chip 407 has a larger size than the control chip 405. The stack of the flash memory chip 407 over the control chip 405 allows connections of the bonding wires 409 of the control chip 405 and placement of the electronic component 411 to be limited to the area covered by the flash memory chip 407 so as to increase the area usage, as a whole. Moreover, it is easy for the bonding wires 409, 409′ to electrically connect the control chip 405 and the flash memory chip 407 to the substrate 401, dispensing with the need of a flip chip. Hence, the fabricating cost is effectively reduced.
Although the present invention has been explained in relation to its preferred embodiments, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
Number | Date | Country | Kind |
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093122554 | Jul 2004 | TW | national |