The present disclosure generally relates to the field of electronics and, more particularly, to integrated circuits, including stacked transistors.
Integrated circuit devices including stacked transistors such as a complementary field effect transistor (CFET) stack, were introduced to reduce their areas compared to those of corresponding non-stacked devices. However, the integrated circuit devices including stacked transistors may include various stacked elements which may make manufacturing process(es) complex and challenging.
According to some embodiments, an integrated circuit device comprising: an upper transistor structure on a substrate, the upper transistor structure comprising a pair of upper source/drain regions spaced apart from each other in a first horizontal direction and an upper gate electrode between the pair of upper source/drain regions; a lower transistor structure between the substrate and the upper transistor structure, the lower transistor structure comprising a lower gate electrode; an upper insulating layer on the lower transistor structure, wherein the upper gate electrode is in the upper insulating layer; and a lower gate contact extending through the upper insulating layer and contacting the lower gate electrode, wherein a center of the upper gate electrode in a second horizontal direction and a center of the lower gate electrode in the second horizontal direction are offset from each other in the second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.
According to some embodiments, an integrated circuit device comprising: first and second upper transistor structures that are on a substrate and are spaced apart from each other in a horizontal direction, the first and second upper transistor structures comprising first and second upper gate electrodes, respectively; a lower transistor structure between the substrate and the first and second upper transistor structures, the lower transistor structure comprising a lower gate electrode that comprises a portion not overlapped by the first and second upper gate electrodes; an intergate insulator extending between the lower gate electrode and the first and second upper gate electrodes; and a lower gate contact between the first and second upper gate electrodes, the lower gate contact extending through the intergate insulator and is contact with the portion of the lower gate electrode.
According to some embodiments, a method of forming an integrated circuit device, the method comprising: forming a preliminary structure on a substrate, the preliminary structure comprising a preliminary upper structure and a preliminary lower structure between the substrate and the preliminary upper structure, the preliminary lower structure comprising a lower insulator and a preliminary lower gate electrode in the lower insulator, and the preliminary upper structure comprising a preliminary upper gate layer; forming a lower gate contact opening extending through the preliminary upper gate layer, thereby forming first and second preliminary upper gate electrodes, the lower gate contact opening exposing the preliminary lower gate electrode, and the first and second preliminary upper gate electrodes being spaced apart from each other in a horizontal direction; and removing the preliminary lower gate electrode through the lower gate contact opening, thereby forming a lower gate electrode opening in the lower insulator; forming a lower gate electrode in the lower gate electrode opening; and then forming a lower gate contact in the lower gate contact opening.
An integrated circuit device may include transistors (e.g., a lower transistor and an upper transistor) stacked in a vertical direction, and those stacked transistors are beneficial for increasing the integration density of the integrated circuit device. Those stacked transistors may be formed by processes performed separately at different times, and several elements (e.g., channel regions or gate electrode) of the stacked transistors can be formed to have different dimensions (e.g., dimensions in a width direction and/or in a height direction) and/or to include different materials. When transistors are stacked in a vertical direction and are formed through separate processes, however, there may be various difficulties in forming conducive contacts that are electrically connected to elements of those stacked transistors. For example, it may be difficult to form a contact that is in contact with an element of the lower transistor and is electrically connected to an element of a back-end-of-line (BEOL) structure, as the upper transistor is disposed between the element of the lower transistor and the BEOL structure. Further, it may be difficult to form an element of the lower transistor well aligned with an element of the upper transistor.
According to some embodiments of the invention, a lower gate electrode and an upper gate electrode and/or a lower source/drain region and an upper source/drain region are arranged in a staggered manner. The integrated density of a stacked integrated circuit device, therefore, may increase while maintaining enough spaces and degrees of design flexibility for contacts (e.g., gate contacts) that are electrically connected to the upper transistor structure and/or the lower transistor structure (e.g., an upper gate electrode and/or a lower gate electrode).
According to some embodiments of the present invention, the stacked integrated circuit device may be included in, for example, a standard cell (e.g., an inverter, a 2-input NAND gate, a 3-input NAND gate, a 2-input NOR gate, a 3-input NOR gate, an And-Or inverter (AOI), an Or-And inverter (OAI), an XNOR gate, an XOR gate, a multiplexer (MUX), a latch, or a D flip-flop), a passive device (e.g., a resistor or a capacitor) or a memory cell (e.g., a SRAM cell).
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The transistor stacks may be spaced apart from each other in a first direction X (also referred to as a first horizontal direction) and a second direction Y (also referred to as a second horizontal direction). The first direction X and the second direction Y may be parallel to the upper surface of the substrate 102 and/or the lower surface of the substrate 102. The first direction X and the second direction Y may intersect (e.g., perpendicularly intersect) each other.
The lower transistor structure 106 and the upper transistor structure 108 may have different conductivity types or the same conductivity type. In some embodiments, the lower transistor structure 106 may be a P-type transistor, and the upper transistor structure 108 may be a N-type transistor, or vice-versa. However, the present invention is not limited thereto.
The lower transistor structure 106 may include a lower gate electrode 110, a lower source/drain region 114 on and/or adjacent to a side surface of the lower gate electrode 110, a lower channel region 118 contacting the lower source/drain region 114 (e.g., a side surface of the lower source/drain region 114), and a lower gate spacer 236 (also referred to as a lower inner gate spacer) between the lower gate electrode 110 and the lower source/drain region 114. For example, the lower transistor structure 106 may include a pair of the lower source/drain regions 114 spaced apart from each other in the first direction X by the lower channel region 118, the lower gate electrode 110, and/or the lower gate spacer 236. The lower gate electrode 110 may include a lower metal gate layer 244 and a lower work function layer 240. Although not illustrated in
In some embodiments, the lower transistor structure 106 may include multiple lower channel regions 118 that are stacked in a third direction Z (also referred to as a vertical direction) and are spaced apart from each other in the third direction Z. Although
The upper transistor structure 108 may include an upper gate electrode 112, an upper source/drain region 116 on and/or adjacent to a side surface of the upper gate electrode 112, an upper channel region 120 contacting the upper source/drain region 116 (e.g., a side surface of the upper source/drain region 116), and an upper gate spacer 238 (also referred to as an upper inner gate spacer) between the upper gate electrode 112 and the upper source/drain region 116. For example, the upper transistor structure 108 may include a pair of the upper source/drain regions 116 spaced apart from each other in the first direction X by the upper channel region 120, the upper gate electrode 112, and/or the upper gate spacer 238. The upper gate electrode 112 may include an upper metal gate layer 246 and an upper work function layer 242. Although not illustrated in
In some embodiments, the upper transistor structure 108 may include multiple upper channel regions 120 that are stacked in the third direction Z and are spaced apart from each other in the third direction Z. Although
The upper channel region 120 and the lower channel region 118 may be spaced apart from each other in the third direction Z and may at least partially overlap with each other in the third direction Z. The upper gate electrode 112 and the lower gate electrode 110 may be spaced apart from each other in the third direction Z and may include respective portions that at least partially overlap with each other in the third direction Z. In some embodiments, the lower gate electrode 110 may have a shape the same as or similar to the upper gate electrode 112 in a plan view, but is not limited thereto. The upper source/drain region 116 and the lower source/drain region 114 may be spaced apart from each other in the third direction Z and may at least partially overlap with each other in the third direction Z. As used herein, “an element A overlapping an element B in a direction X” (or similar language) means that there is at least one line that extends in the direction X and intersects both the elements A and B.
In some embodiments, a center of the upper gate electrode 112 (e.g., the upper metal gate layer 246) in the second direction Y and a center of the lower gate electrode 110 (e.g., the lower metal gate layer 244) in the second direction Y may be offset from each other in the second direction Y. In some embodiments, the lower gate electrode 110 may have a first portion that does not overlap the upper gate electrode 112 in the third direction Z and a second portion that overlaps the upper gate electrode 112 in the third direction Z. In some embodiments, the upper gate electrode 112 may have a first portion that does not overlap the lower gate electrode 110 in the third direction Z and a second portion that overlaps the lower gate electrode 110 in the third direction Z. For example, the lower gate electrode 110 and the upper gate electrode 112 may be staggered in the third direction Z to have portions that are overlapped with each other in the third direction Z.
In some embodiments, a center of the upper channel region 120 in the second direction Y and a center of the lower channel region 118 in the second direction Y may be offset from each other in the second direction Y, as illustrated in
In some embodiments, each of the lower transistor structure 106 and the upper transistor structure 108 may have a structure different from that illustrated in
The lower transistor structure 106 may be disposed in a first insulating layer 226 (also referred to as a lower insulating layer) that is disposed on the substrate 102. A second insulating layer 228 (also referred to as an upper insulating layer) may be disposed on the first insulating layer 226. The upper transistor structure 108 may be disposed in the second insulating layer 228.
In some embodiments, a third insulating layer 232 and a fourth insulating layer 234 may be sequentially provided on the second insulating layer 228. However, the present invention is not limited to the numbers or relative locations of the insulating layers. For example, an upper surface of a first portion of the second insulating layer 228 may be coplanar with an upper surface of the third insulating layer 232, and an upper surface of a second portion of the second insulating layer 228 may be lower (e.g., closer to the upper surface of the substrate 102) than the upper surface of the third insulating layer 232. In some embodiments, the third insulating layer 232 and the fourth insulating layer 234 may comprise an integrated unitary structure. An integrated unitary structure herein may refer to a structure formed by the same process or the same series of processes without visible interface(s) between sub-elements therein or may include the same material such that there is no visible interface between sub-elements therein.
In some embodiments, an intergate insulator 230 may be disposed between the first insulating layer 226 and the second insulating layer 228. The intergate insulator 230 may include a first intergate insulator 230a disposed on the first insulating layer 226, and a second intergate insulator 230b disposed between the first intergate insulator 230a and the second insulating layer 228. In some embodiments, the intergate insulator 230 may be a single layer (e.g., a monolithic layer). Interfaces (represented by dotted lines in
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The substrate 102 may include semiconductor material(s), for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and/or InP and/or may include insulating material(s), for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material. In some embodiments, the substrate 102 may be a bulk substrate (e.g., a bulk silicon substrate), a semiconductor on insulator (SOI) substrate or an insulating layer (e.g., a monolithic insulating layer). For example, the substrate 102 may be a silicon wafer. The low-k material may include, for example, fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymeric dielectrics and/or spin-on silicon based polymeric dielectric.
Each of the device isolation layer 204, the first, second, third, and fourth insulating layers 226, 228, 232, and 234, and the intergate insulator 230 may include insulating material(s) (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material). In some embodiments, the intergate insulator 230 may include silicon oxynitride and the first, second, third, and fourth insulating layers 226, 228, 232, and 234 may include silicon nitride. Each of the device isolation layer 204, the first, second, third, and fourth insulating layers 226, 228, 232, and 234, and the intergate insulator 230 may be a single layer or multiple layers stacked on the substrate 102.
The lower gate electrode 110 and the upper gate electrode 112 may include the same material(s) or different material(s). The lower and upper metal gate layers 244 and 246 may include metallic layer(s) that include, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo) and/or ruthenium (Ru). The lower and upper work function layers 240 and 242 may include, for example, a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer and/or a WN layer, respectively.
The work function layer(s) (e.g., the lower work function layer 240 or upper work function layer 242) may be respectively provided between the metallic layer(s) (e.g., the lower metal gate layer 244 or upper metal gate layer 246) and the channel region(s) (e.g., the lower channel region 118 or the upper channel region 120). For example, the lower work function layer 240 may extend between the lower metal gate layer 244 and the lower channel region 118, and the upper work function layer 242 may extend between the upper metal gate 246 and the upper channel region 120.
In some embodiments, the lower work function layer 240 may extend between the lower metal gate layer 244 and the intergate insulator 230 (e.g., the first intergate insulator 230a). The lower work function layer 240 may be in contact with the intergate insulator 230 (e.g., the first intergate insulator 230a). In some embodiments, the upper work function layer 242 may extend between the upper metal gate layer 246 and the intergate insulator 230 (e.g., the second intergate insulator 230b). The upper work function layer 242 may be in contact with the intergate insulator 230 (e.g., the second intergate insulator 230b).
Each of the lower channel region 118 and the upper channel region 120 may include semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP). In some embodiments, the lower channel region 118 and the upper channel region 120 may include the same material(s). In some embodiments, each of the lower channel region 118 and the upper channel region 120 may be a nanosheet that may have a thickness in a range of from 1 nm to 100 nm in the third direction Z or may be a nanowire that may have a circular cross-section with a diameter in a range of from 1 nm to 100 nm.
Each of the lower source/drain region 114 and the upper source/drain region 116 may include semiconductor layer(s) (e.g., a silicon layer and/or a silicon germanium layer) and may additionally include dopants in the semiconductor layer(s). In some embodiments, each of the lower source/drain region 114 and the upper source/drain region 116 may include metal layer(s) that include, for example, W, Al, Cu, Mo and/or Ru.
Each of the lower gate spacer 236 and the upper gate spacer 238 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride and/or a low-k material. The lower gate spacer 236 and the upper gate spacer 238 may include the same material(s) or different material(s).
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In some embodiments, a plurality of the lower gate contacts 122 may be respectively disposed on the lower gate electrodes 110. For example, the plurality of the lower gate contacts 122 may include a first lower gate contact 122a and a second lower gate contact 122b. Referring to
In some embodiments, the stacked integrated circuit device 100 may further include an upper gate contact 124 on the upper transistor structure 108 (e.g., the upper gate electrode 112). The upper gate contact 124 may extend through the third insulating layer 232. For example, the upper gate contact 124 may also extend through the fourth insulating layer 234 to be electrically connected (e.g., to contact) to the upper structure. In some embodiment, a portion (e.g., an upper portion) of the upper gate contact 124 may be formed by the middle-end-of-line (MEOL) portion and/or a part of the back-end-of-line (BEOL) portion.
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As a lower gate electrode and an upper gate electrode and/or a lower source/drain region and an upper source/drain region are disposed in a staggered manner, the integrated density of a stacked integrated circuit device may increase while maintaining enough spaces and degrees of design flexibility for contacts (e.g., an upper gate contact and/or a lower gate contact) that are electrically connected to the upper transistor structure and/or the lower transistor structure (e.g., the upper gate electrode and/or the lower gate electrode).
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The preliminary lower structure 1060 may include the first insulating layer 226, the preliminary lower gate electrode 910 in the first insulating layer 226, and the lower channel regions 118 and the lower sacrificial patterns 652 that are stacked in the third direction Z in the preliminary lower gate electrode 910. The lower channel regions 118 may be alternately stacked with the lower sacrificial patterns 652 in the third direction Z in the preliminary lower gate electrode 910.
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The preliminary upper gate layer 1112 and the preliminary lower gate electrode 910 may include, for example, poly-silicon. In some embodiments, the upper channel regions 120 may be formed in a staggered manner with the lower channel regions 118 in the third direction Z. For example, the center of the upper channel region 120 in the second direction Y and the center of the lower channel region 118 in the second direction Y may be offset from each other in the second direction Y.
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Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments herein should not be construed as limited to the particular shapes illustrated herein but may include deviations in shapes that result, for example, from manufacturing.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element is referred to as being “coupled,” “connected,” or “responsive” to, “adjacent to”, or “on,” another element, it can be directly coupled, connected, or responsive to, adjacent to, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly responsive” to, “directly adjacent to”, or “directly on,” another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Moreover, the symbol “/” (e.g., when used in the term “source/drain”) will be understood to be equivalent to the term “and/or.” It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
In one example, when a certain embodiment may be implemented differently, processes or methods may occur in a sequence different from that specified in the description herein. For example, two consecutive processes may actually be executed at the same time. Depending on a related function or operation, the processes may be executed in a reverse sequence. Moreover, a process may be separated into multiple processes and/or may be at least partially integrated.
In descriptions of temporal relationships, for example, temporal precedent relationships between two events such as “after”, “subsequent to”, “before”, etc., another event may occur therebetween unless “directly after”, “directly subsequent” or “directly before” is not indicated.
Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
This application claims priority to U.S. Provisional Application Ser. No. 63/496,701, entitled STACKED DEVICES INCLUDING STAGGERED ACTIVE STRUCTURES AND METHODS OF FORMING THE SAME, filed in the USPTO on Apr. 18, 2023, the disclosure of which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | |
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63496701 | Apr 2023 | US |