Stacked semiconductor memory device and control method thereof

Abstract

A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic cross-sectional view showing a structure of a stacked semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a schematic plan view showing the structure of the core chip 131;

FIG. 3 is a detailed circuit diagram showing principal parts corresponding to an area A shown in FIG. 2;

FIG. 4 is a timing chart for explaining an operation of the stacked semiconductor memory device according to the first embodiment;

FIG. 5 is a schematic diagram showing an alignment of the memory arrays activated through a series of read-out operations shown in FIG. 4;

FIG. 6 is a circuit diagram showing a structure of principal parts of a stacked semiconductor memory device according to the second embodiment;

FIG. 7 is a timing chart for explaining an operation of the stacked semiconductor memory device according to the second embodiment;

FIG. 8 is a schematic diagram showing an alignment of the memory arrays activated through a series of read-out operations shown in FIG. 7;

FIG. 9 is a timing chart for explaining an operation of the stacked semiconductor memory device according to the third embodiment;

FIG. 10 is a schematic diagram showing an alignment of the memory arrays activated through a series of read-out operations shown in FIG. 9;

FIG. 11 is a schematic diagram for explaining a structure of a stacked semiconductor memory device according to a fourth embodiment of the present invention; and

FIG. 12 is a timing chart for explaining the operation of the stacked semiconductor memory device according to the fourth embodiment.

Claims

1. A stacked semiconductor memory device in which a plurality of semiconductor chips including a plurality of core chips are stacked, comprising: a plurality of memory arrays each arranged on the plurality of core chips;a plurality of data through electrodes that mutually connect the plurality of core chips; anda connector that sequentially connects a plurality of predetermined memory arrays activated by an activation signal and a predetermined data through electrode.

2. The stacked semiconductor memory device as claimed in claim 1, wherein the activation signal activates the predetermined memory arrays included in the same core chip.

3. The stacked semiconductor memory device as claimed in claim 1, wherein the activation signal activates the predetermined memory arrays included in different core chips.

4. The stacked semiconductor memory device as claimed in claim 2, wherein the activation signal activates the predetermined memory arrays included in different core chips.

5. The stacked semiconductor memory device as claimed in claim 2, further comprising at least one selection-signal through electrode that mutually connects the plurality of core chips, wherein the selection-signal through electrode is supplied with a selection signal that selects which memory array, among the predetermined memory arrays activated by the activation signal, is connected to the predetermined data through electrode.

6. The stacked semiconductor memory device as claimed in claim 3, further comprising at least one selection-signal through electrode that mutually connects the plurality of core chips, wherein the selection-signal through electrode is supplied with a selection signal that selects which memory array, among the predetermined memory arrays activated by the activation signal, is connected to the predetermined data through electrode.

7. The stacked semiconductor memory device as claimed in claim 5, wherein said at least one selection-signal through electrode includes first and second selection-signal through electrodes,the connector connects, in response to activation of a selection signal supplied via the first selection-signal through electrode, a first memory array and the predetermined data through electrode, and connects, in response to activation of a selection signal supplied via the second selection-signal through electrode, an activated second memory array and the predetermined data through electrode, andthe first memory array and the second memory array are included in the same core chip.

8. The stacked semiconductor memory device as claimed in claim 6, wherein said at least one selection-signal through electrode includes first and second selection-signal through electrodes,the connector connects, in response to activation of a selection signal supplied via the first selection-signal through electrode, a first memory array and the predetermined data through electrode, and connects, in response to activation of a selection signal supplied via the second selection-signal through electrode, an activated second memory array and the predetermined data through electrode, andthe first memory array and the second memory array are included in the same core chip.

9. The stacked semiconductor memory device as claimed in claim 5, wherein the plurality of semiconductor chips further include an interface chip on which a peripheral circuit for at least the core chip is formed, and the selection signal is generated by the interface chip.

10. The stacked semiconductor memory device as claimed in claim 6, wherein the plurality of semiconductor chips further include an interface chip on which a peripheral circuit for at least the core chip is formed, and the selection signal is generated by the interface chip.

11. The stacked semiconductor memory device as claimed in claim 1, wherein while data is continuously transferred using the connector, a parity of the data is transferred via another data through electrode different from the predetermined data through electrode.

12. A method of controlling a stacked semiconductor memory device in which a plurality of core chips each having a plurality of memory arrays are stacked and the plurality of core chips are mutually connected by a plurality of data through electrodes, comprising: a first step for activating, in response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode; anda second step for sequentially connecting the activated memory arrays and the predetermined data through electrode.

13. The method of controlling a stacked semiconductor memory device as claimed in claim 12, wherein at the first step, a plurality of memory arrays included in the same core chip are activated.

14. The method of controlling a stacked semiconductor memory device as claimed in claim 12, wherein at the first step, a plurality of memory arrays included in different core chips are activated.

15. The method of controlling a stacked semiconductor memory device as claimed in claim 13, wherein at the first step, a plurality of memory arrays included in different core chips are activated.

16. The method of controlling a stacked semiconductor memory device as claimed in claim 12, wherein while data is successively transferred at the second step, a parity of the data is transferred via another data through electrode different from the predetermined data through electrode.

17. A method of controlling a semiconductor memory device in which a plurality of core chips each having a plurality of memory arrays are stacked and the plurality of core chips are mutually connected by a plurality of data through electrodes including first and second data through electrodes, comprising: a first step for successively transferring a series of data via the first data through electrode; anda second step for transferring, while the data is successively transferred at the first step, a parity of the data via the second data through electrode.