Patent Application
20090032970
Embodiments disclosed herein are generally directed to the field of semiconductor fabrication and, more particularly, to stacking of integrated circuits.
Generally, stacked integrated circuits such as stacked memory devices and/or three dimensional interconnects are used to provide larger storage volume or processing capacity while using cheaper, lower density manufacturing designs. Currently, wafers may be stacked by bonding Cu pads of two integrated circuits together using temperatures in excess of about 200° C. at pressures exceeding about 40 kN. Such thermal bonding process may require heating and cooling of separate wafers/dies resulting in poor bonding qualities during post-bonding processes. Exposure to high temperature and/or heating and cooling of separate wafers/dies may affect the quality and uniformity of a metallic bonding surface leading to problems such as delamination. Furthermore, current metallic bonding may form relatively brittle intermetallic compounds at the interface, which are typically a source of a host of reliability issues such as drop or shock failures.
Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
Embodiments of stacking integrated circuits using glassy metal bonding are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
Bulk glassy metals or bulk metallic glasses 1101 . . . n, 1121 . . . n are materials that may exhibit both metallic properties (i.e.—electrical, thermal conduction, and high strength/toughness) and polymeric properties (i.e.—glass transition, thermoplastic behavior above glass transition temperature, Tg). Bulk glassy metals 1101 . . . n, 1121 . . . n may exhibit exceptional glass forming ability and thermal stability similar to polymers. Such glassy metals 1101 . . . n, 1121 . . . n may be amorphous in the solid state and become viscous liquid above Tg. In an embodiment, glassy metals 1101 . . . n, 1121 . . . n have unique rheological behavior above Tg that enables excellent formability and pattern replication ability on the scale of nanometers. In an embodiment, a bulk glassy metal 1101 . . . n, 1121 . . . n is amenable to polymer-like processing such as injection molding.
Because of their excellent pattern replication ability, bulk glassy metals 1101 . . . n, 1121 . . . n may have good adhesion on a variety of materials through nanometer scale interlocking without intermetallic compound formation. In other words, adhesion of bulk glassy metal 1101 . . . n, 1121 . . . n with other materials may not rely on intermetallic compound. The absence of intermetallic compound in bonding applications may be highly beneficial because intermetallic compounds are the source of reliability issues such as drop or shock failure in current microelectronic joints. Joints 1121 . . . n formed using bulk metallic glass may provide a benefit of creating substantially no reliability-threatening intermetallic compounds at the interface between the joints 1121 . . . n and the one or more pads 1041 . . . n,1081 . . . n of the first 102 and second 106 integrated circuits. Reliability-threatening intermetallic compounds may include those compounds at the joint 1121 . . . n interface that are more brittle relative to the rest of the joint.
Glassy metal 1101 . . . n, 1121 . . . n bonding may enable low temperature bonding between integrated circuits 102, 106. For example, a first 102 and second 106 integrated circuit may be thermoplastically bonded using glassy metal 1101 . . . n as a bond layer at temperatures above Tg, the glass transition temperature, but below Tm, the melting temperature of the glassy metal 1101 . . . n.
A sufficient amount of thermal energy applied to a bulky glass metal over a period of time may crystallize the material due to the metastability of bulky glass metals above Tg. Various stages of crystallization may be achieved in a bulky glass metal 1121 . . . n including the onset of crystallization, partial crystallization in terms of %, or complete crystallization. In an embodiment, a bulky glass metal bonding material 1101 . . . n is raised above Tg whereupon it is converted from a solid state glass to a viscous liquid. Above Tg, a liquid bulky glass metal 1101 . . . n may be a supercooled liquid. In an embodiment, a bonding temperature for a first 102 and second 106 integrated circuit is above Tg and below Tm of a selected bulk metallic glass 1101 . . . n such that thermoplastic bonding occurs within this temperature regime.
Thermoplastic bonding may also include the application of a low pressure. A low pressure may be provided by applying opposing force that is about normal to each planar backside surface of the first 102 and second 106 integrated circuits, the force being applied in a direction that tends to bring the first 102 and second 106 integrated circuits together. The backside of an integrated circuit 102, 106 may be a surface that does not have microcircuitry on the surface itself (i.e.—the planar surfaces opposite the pads 1041 . . . n, 1081 . . . n).
In an embodiment, the bonding temperature for the bulk metallic glass joint 1121 . . . n is less than about 200° C. and the bonding pressure is less than about 40 kN. In an embodiment, the bonding temperature is about 100° C. or below according to the composition of the bulk metallic glass 1101 . . . n. In an embodiment, the bonding pressure is about 1 MPa. Bonding temperature and pressure may vary or be different for different-sized wafers and dies and/or selected bulk glassy metals 1101 . . . n.
A time period for thermoplastic bonding, annealing, or crystallization may be selected for a given temperature using a time-temperature-transformation diagram for the bulk glassy metal 1101 . . . n, 1121 . . . n. In an embodiment, a bulk glassy metal 1101 . . . n bonding material is brought above its Tg and held at a selected temperature under low pressure for thermoplastic bonding for a selected time, the selected time being determinative of the amorphous and/or crystalline nature of a final glassy metal joint 1121 . . . n. The bulk glassy metal joint 1121 . . . n may be cooled down to room temperature after thermoplastic bonding or after any crystallization that may have occurred according to the selected time, temperature, and pressure for a given bulk glassy metal 1101 . . . n, 1121 . . . n.
In an embodiment, the bulk metallic glass joints 1121 . . . n are amorphous, crystalline, or suitable combinations thereof. In an embodiment, the bulk metallic glass 1121 . . . n becomes crystalline to provide stability and reliability. In another embodiment, the bulk metallic glass 1121 . . . n remains in glass form. The operating temperatures of the stacked integrated circuits 102, 106 at the bulk metallic glass joint 1121 . . . n and the Tg of the bulk metallic glass 1121 . . . n may influence whether or not the joints 1121 . . . n are desirably crystalline or amorphous. For example, a bulk metallic glass joint 1121 . . . n with a very low Tg may be crystalline to avoid reaching the glass transition temperature (Tg) during operation of the stacked device. Reaching or exceeding the Tg for an amorphous joint 1121 . . . n may compromise reliability by enabling liquid flow characteristics in the joint 1121 . . . n.
In an embodiment, the bulk metallic glass joints 1121 . . . n include materials such as Au49.2Cu27Ag5.5Pd2.35Si16, Pt57.5Cu14.7Ni5.3P22.5, or Mg65Cu25Y10, or suitable combinations thereof, where the numbers represent approximate atomic %. In an embodiment, Au49.2Cu27Ag5.5Pd2.35Si16 has a Tg of about 128° C. and a suitable bonding temperature of about 160° C. to about 170° C. Other suitable glassy metals may be selected that accord with temperature and/or pressure embodiments described herein beyond the example materials listed above. Such glassy metals also fall within the scope and spirit of this specification.
In an embodiment, the first 102 and second 106 integrated circuits are in wafer form or die form. A wafer may be a circular semiconductor substrate upon which integrated circuits 102, 106 are formed with typical wafers being about 150 mm, 200 mm, or 300 mm in diameter. A die may be a rectangular portion on a wafer upon which one or more integrated circuits 102, 106 are formed. A wafer may be cut into one or more dies when the wafer is cut into individual product units. In an embodiment, the first 102 and second 106 integrated circuits include stacked wafers, dies, or suitable combinations thereof In another embodiment, a first 102 or second 106 integrated circuit may be a memory or logic device, or any suitable combination thereof.
In an embodiment, an apparatus according to
In an embodiment according to
In another embodiment, the one or more pads 1041 . . . n, 1081 . . . n include Cu bond pads. Other suitable bonding pad 1041 . . . n, 1081 . . . n materials compatible with glassy metal bonding 1121 . . . n may be used as well. The one or more bonding pads 1041 . . . n, 1081 . . . n may be on the order of microns or nanometers in size. For example, bonding pads 1041 . . . n, 1081 . . . n may be about 5-10 microns in size in an embodiment. Many more pads 1041 . . . n, 1081 . . . n may be bonded together than depicted in FIG. 1, which depicts only eight pads 1041 . . . n, 1081 . . . n for the sake of clarity and convenience. In an embodiment, the bonding pads 1041 . . . n, 1081 . . . n are patterned onto the surface of an integrated circuit 102, 106 using a bonding template layer pattern that defines at least the pitch and size of the pads 1041 . . . n, 1081 . . . n.
In other embodiments, one or more integrated circuits (not shown) in addition to the first 102 and second 106 integrated circuits are stacked together with the first 102 and second 106 integrated circuits using bulk metallic glass as a bonding material 1121 . . . n.
Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
In an embodiment, a method 200 includes applying a bulk metallic glass bonding material to one or more pads of a first integrated circuit or a second integrated circuit 204 wherein the bulk metallic glass bonding material provides a low temperature and low pressure bonding solution to reduce delamination or wherein the bulk metallic glass provides reduced intermetallic compound to increase joint reliability, or suitable combinations thereof. In another embodiment, applying a bulk metallic glass bonding material 204 includes applying materials such as Au49.2Cu27Ag5.5Pd2.35Si16, Pt57.5Cu14.7Ni5.3P22.5, or Mg65Cu25Y10, or suitable combinations thereof, where the numbers represent approximate atomic %.
In an embodiment, the bonding pads include Cu materials. In an embodiment, the pads are formed by creating a bond layer template pattern, which may be a Cu patterned layer on which glassy metal is applied 204. A glassy metal may be applied onto the template pattern 204, according to an embodiment.
In an embodiment, stacking the first and second integrated circuits 210 includes using a bonding temperature that is less than about 200° C. and applying a bonding pressures that is less than about 40 kN. In another embodiment, stacking the first and second integrated circuits 210 includes forming a bulk metallic glass joint having substantially no reliability-threatening intermetallic compounds at the interface between the joint and the one or more pads of the first and second integrated circuits.
In an embodiment, aligning the one or more pads 206 and bringing the surfaces of the pads together 208 for bonding is accomplished on a single piece of semiconductor manufacturing equipment. In an embodiment, current equipment used to align and bring together circuits to be stacked is used to align and bring together circuits to be stacked using metallic glass.
A method 200 may include preparing the surfaces of a first and second integrated circuit for bonding 202 prior to applying a bulk metallic glass bonding material to one or more pads 204. Preparing the surfaces 202 may include polishing, etching, or vapor deposition of the one or more pads to be joined, or suitable combinations thereof.
In an embodiment, a method 200 includes applying a post-bonding process 212 after stacking the first and second integrated circuits 210. In an embodiment, applying a post-bonding process 212 includes thinning a backside surface of the stacked integrated circuits, creating vias through the thinned surface and creating interconnect bumps onto the thinned surface of the stacked integrated circuit, and/or electrically coupling the stacked device with other packaging or assembly components through the created vias and interconnect bumps, or suitable combinations thereof. Thinning a backside surface may be performed until about 100 microns or less of semiconductor substrate remains between the backside surface and the integrated circuit. In another embodiment, wirebonding is used to couple the stacked device with other microelectronic devices.
In another embodiment, applying a post-bonding process 212 includes stacking one or more additional integrated circuits with the stacked first and second integrated circuit, the one or more integrated circuits being stacked together with the first and second integrated circuits using bulk metallic glass as a bonding material. In other embodiments, a stacked integrated circuit formed using method 200 is coupled with other components, microelectronic devices, or electronic systems as depicted in
In one embodiment, electronic system 300 includes stacked integrated circuits bonded using bulk glassy metal 100 in accordance with embodiments described with respect to
Electronic system 300 may include bus 305 or other communication device to communicate information, and processor 310 coupled to bus 305 that may process information. While electronic system 300 may be illustrated with a single processor, system 300 may include multiple processors and/or co-processors. In an embodiment, processor 310 includes stacked logic integrated circuits 100 in accordance with embodiments described herein. System 300 may also include random access memory (RAM) or other storage device 320 (may be referred to as memory), coupled to bus 305 and may store information and instructions that may be executed by processor 310.
Memory 320 may also be used to store temporary variables or other intermediate information during execution of instructions by processor 310. Memory 320 is a flash memory device in one embodiment. In another embodiment, memory 320 includes stacked integrated circuits 100 formed using glassy metal bonding techniques 100, 200 disclosed herein.
System 300 may also include read only memory (ROM) and/or other static storage device 330 coupled to bus 305 that may store static information and instructions for processor 310. Data storage device 340 may be coupled to bus 305 to store information and instructions. Data storage device 340 such as a magnetic disk or optical disc and corresponding drive may be coupled with electronic system 300.
Electronic system 300 may also be coupled via bus 305 to display device 350, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user. Alphanumeric input device 360, including alphanumeric and other keys, may be coupled to bus 305 to communicate information and command selections to processor 310. Another type of user input device is cursor control 370, such as a mouse, a trackball, or cursor direction keys to communicate information and command selections to processor 310 and to control cursor movement on display 350.
Electronic system 300 further may include one or more network interfaces 380 to provide access to network, such as a local area network. Network interface 380 may include, for example, a wireless network interface having antenna 385, which may represent one or more antennae. Network interface 380 may also include, for example, a wired network interface to communicate with remote devices via network cable 387, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.
In one embodiment, network interface 380 may provide access to a local area network, for example, by conforming to an Institute of Electrical and Electronics Engineers (IEEE) standard such as IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported.
IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents. IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents. Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Previous or subsequent versions of the Bluetooth standard may also be supported.
In addition to, or instead of, communication via wireless LAN standards, network interface(s) 480 may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol.
In an embodiment, a system 300 includes one or more omnidirectional antennae 385, which may refer to an antenna that is at least partially omnidirectional and/or substantially omnidirectional, and a processor 310 coupled to communicate via the antennae.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of this description, as those skilled in the relevant art will recognize.
These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the scope to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the embodiments disclosed herein is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
