Patent Application
20250006766
This relates generally to imaging systems and, more specifically, to imaging systems with single-photon avalanche diodes (SPADs).
A SPAD is a type of P-N junction diode biased above a breakdown voltage using a high voltage. In this state, the SPAD can be sensitive to a single impinging photon. A SPAD can be coupled to associated high voltage switches and digital readout circuits. The high voltage switches can include a pull-up transistor and a pull-down transistor. The digital readout circuits can include a comparator, level shifter, and pulse generators.
Conventionally, an array of SPADs and the high voltage switches are formed on separate chips or packages. In such configurations, it can be challenging to achieve active pixel quenching and to minimize package size while ensuring connection reliability. It is within this context that the embodiments described herein arise.
Imaging systems or devices may include single-photon avalanche diodes (SPADs), forming SPAD-based imaging systems or devices (sometimes referred to herein simply as SPAD devices). SPAD-based devices are sometimes referred to as silicon photomultipliers (SiPMs).
Some imaging systems include image sensors that sense light by converting impinging photons into electrons or holes that are integrated (collected) in pixel photodiodes within the sensor array. After completion of an integration cycle, collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In complementary metal-oxide semiconductor (CMOS) image sensors, the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog pixel voltage can also be later converted on-chip to a digital equivalent and processed in various ways in the digital domain.
SPAD devices, on the other hand, employ a different photon detection mechanism. In some illustrative configurations sometimes described herein as an example, SPAD devices may form light detection and ranging (LIDAR) devices or imaging systems. A LIDAR device may include a light source that emits light toward a target object or scene. A light sensing diode (SPAD) in the LIDAR device may be biased above its breakdown point and when an incident photon from the light source (e.g., light that has reflected off of the target object/scene) generates an electron-hole pair, these carriers initiate an avalanche breakdown with additional carriers being generated. As the avalanche multiplication is a self-sustaining process, a current signal may be produced and can be easily detected by readout circuitry associated with the SPAD. The avalanche breakdown process needs to be stopped (quenched) in order to detect a new photon by lowering the voltage bias across the diode below its breakdown point. In LIDAR devices, the SPAD pixels may be used to measure photon time-of-flight (ToF) from a synchronized light source to a scene object point and back to the sensor, which can be used to obtain a 3-dimensional image of the scene (as an example).
Imaging system 10 may include or implement a LIDAR-based device (sometimes referred to as a LIDAR module) having SPAD device(s). The LIDAR module may use the SPAD device(s) to capture images of a scene and measure distances to obstacles (also referred to as targets) in the scene. As an example, in a vehicle safety system, information from the LIDAR module may be used by the vehicle safety system to determine environmental conditions surrounding the vehicle. As examples, vehicle safety systems may include systems such as a parking assistance system, an automatic or semi-automatic cruise control system, an auto-braking system, a collision avoidance system, a lane keeping system (sometimes referred to as a lane-drift avoidance system), a pedestrian detection system, etc. In at least some instances, the LIDAR module may form part of a semi-autonomous or autonomous self-driving vehicle.
An illustrative example of a vehicle such as an automobile 8 is shown in
Referring back to
SPAD-based device 12 may include control circuitry. The control circuitry for SPAD-based device 12 may be formed either on-chip (e.g., on the same semiconductor substrate as the SPAD-based device 12) or off-chip (e.g., on a different semiconductor substrate as the SPAD-based device 12). The control circuitry may control operation of SPAD-based device 12. For example, the control circuitry may operate active quenching circuitry or other adjustable (transistor) circuitry within each SPAD pixel, may control one or more bias voltages provided to each SPAD pixel, may control/monitor the readout circuitry associated with each SPAD pixel, etc.
The SPAD-based semiconductor device 12 may optionally include additional circuitry such as logic gates, digital counters, time-to-digital converters, bias circuitry (e.g., source follower load circuits), sample and hold circuitry, amplifier circuitry, analog-to-digital (ADC) converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc. Any of the aforementioned circuits may form part of the control circuitry or, when provided on a per-pixel basis, may form part of the SPAD pixel.
If desired, 3D image data output from SPAD-based device 12 may be provided to downstream image processing circuitry. The image processing circuitry may process data gathered by the SPAD pixels to determine a depth map of the scene (as another example) using the time-of-flight data. The full 3D image data of the specific scene may be obtained by combining the depth map of the scene with an intensity map. The intensity map can refer to a spatial representation of photon intensity or photon count obtained from detected photons and can provide information on the spatial distribution of photon intensities/counts across a two-dimensional area or even a three-dimensional volume in certain applications. In some cases, some or all of the control circuitry for SPAD device 12 may be formed integrally with the image processing circuitry (e.g., on the same die or package).
Imaging system 10 may provide a user with numerous high-level functions. For example, a user may be provided with the ability to run user applications on system 10. To implement these functions, imaging system 10 may include input-output devices 16 such as keypads, buttons, input-output ports, joysticks, and displays. If desired, other functional modules and/or additional storage and processing circuitry (e.g., other components 20) may also be included in imaging system 10. Other such modules or circuitry may include volatile and nonvolatile memory (e.g., random-access memory, flash memory, hard drives, solid state drives, etc.), microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, and/or other processing circuits for other (non-imaging) functional modules.
Input-output devices 16 may include output devices that work in combination with SPAD-based devices 12. For example, one or more light-emitting components 18 may be included in imaging system 10 to emit light (e.g., infrared light or light of any other desired type). Light-emitting component 18 may be a laser, light-emitting diode, or any other desired type of light-emitting component. SPAD-based device 12 may measure the reflection of the light off of an object to measure distance to the object in a LIDAR scheme (e.g., in scenarios where imaging system 10 implements or includes a LIDAR module). The control circuitry that is used to control operation of SPAD-based device 12 may optionally also be used to control operation of light-emitting component 18 for a coordinated sensing scheme.
A quenching circuit may be used to lower the bias voltage of SPAD 24 below or at the level of the breakdown voltage. Lowering the bias voltage of SPAD 24 below the breakdown voltage stops the avalanche process and the corresponding avalanche current. There are numerous ways to form a quenching circuit. As examples, the quenching circuit may be a passive quenching circuit or an active quenching circuit. A passive quenching circuit may, without external control or monitoring, automatically quench the avalanche current once initiated. As an example, a resistor (e.g., a passive resistive component) coupled between the cathode terminal of the SPAD and a corresponding voltage supply terminal may serve as a passive quenching circuit. On the other hand, an active quenching circuit may require external control or monitoring to apply a voltage to the cathode terminal of the SPAD.
In the example of
To control the state of switch 40, the quenching circuit of pixel 30 may also include control circuit 50 that supplies a control signal along path 52 that controls the state of switch 40. For example, the control circuit 50 may assert or de-assert the control signal to switch between on and off states of the switch 40 or may otherwise control switch 40 in any suitable manner. In the example of
In a similar manner, delay circuit 44 may provide a control signal on path 46 (e.g., based on an introduced delay) to control switch 36 to be in open or closed states at corresponding times. As an example, a suitable time period after the quenching operation of SPAD 24 (e.g., the assertion of the control signal on path 52 to close switch 40), delay circuit 44 may provide an asserted control signal to close switch 36 to reset or recharge SPAD 24 and prepare for detection of a subsequent photon. The time period after the quenching operation and the reset/recharge operation of SPAD 24 can have a duration equal to tens or hundreds of nanoseconds (ns), less than 100 ns, less than 10 ns, less than 1 ns, or more than 1 microsecond. Switch 36 is therefore sometimes referred to as a pull-up transistor or recharge transistor.
In the example of
To provide additional functionalities to SPAD pixel 30, control circuit 50 may receive additional input signals, such as DIS and TST. In particular, input signal DIS may be a disable signal that, when asserted, enables control circuit 50 to use (assert) the control signal on path 52 to maintain switch 40 in a closed or activated state such that SPAD avalanching is prevented, thereby actively disabling pixel 30 from performing sensing operations. Input signal TST may be a test signal that, when asserted, enables control circuit 50 to control switch 40 and/or other pixel elements to respond to a test input, thereby providing testability to pixel 30.
Delay circuit 44, control circuit 50, driver 54, and/or any other circuitry associated with the readout of a SPAD pixel 30 can be referred to collectively and defined herein as “digital readout logic.” For example, the other circuitry which may include one or more comparator, one or more pulse generators, one or more level shifter, one or more inverter, etc. The digital readout logic can be powered by a power supply voltage that is lower than supply voltage VH, sometimes referred to as a low supply voltage. As an example, the low supply voltage for powering the digital readout logic can be equal to 1.8 V. 1-2 VSS, 2-3 V. 3.3 V. 3-4 V, or other voltage lower than VH.
On the other hand, switches 36 and 40 that are powered using high voltage VH are sometimes referred to and defined herein as “high voltage” transistors or analog high voltage (HV) devices. High voltage transistors 36 and 40 coupled to cathode terminal 34 are considered analog devices since the signal generated at cathode terminal 34 when SPAD 24 senses an impinging photon is an analog signal. As an example, the high voltage VH for powering the analog high voltage transistors 36 and 40 can be equal to 5 V, 6 V, 7 V, 5-7 V, 4-6 V, 6-8 V, 4-8 V, more than 8 V, or other voltage greater than the low voltage powering the digital readout logic. On the other hand, bias voltage VBS at the anode terminal 32 can be set equal to at least 17 V, 18 V. 19 V, 20 V, 17-20 V, more than 10 V, more than 12 V, more than 14 V, more than 16 V, or other suitable level to ensure that SPAD 24 is biased in the breakdown operating regime.
In accordance with some embodiments, the SPAD pixel circuitry can be implemented using a stacked die arrangement, sometimes referred to as 3-dimensional (3D) stacking. The stacked die arrangement may include two or more die with different components and circuitry that, when stacked vertically together, form the SPAD pixel circuitry.
As shown in
An interconnect stack such as interconnect stack 112 can be formed on semiconductor substrate 110. Interconnect stack 112 may include alternating routing layers and via layers. If desired, interconnect stack 112 can optionally include only one routing layer and only one via layer. Each routing layer can include conductive (metal) routing paths such as metal routing structures 116 formed in a layer of dielectric material. Each via layer can include conductive (metal) vias such as metal via structures 118 formed in a layer of dielectric material. Interconnect stack 112 is therefore sometimes referred to as a dielectric stack (e.g., an interconnect stack having conductive routing paths formed within dielectric material such as silicon dioxide). The conductive routing structures 116 and the conductive via structures 118 can be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, a metal alloy, a combination of metals, and/or other types of conductive material. The metal routing structures 116 and the metal via structures 118 can form an electrical network for interconnecting together various components within die 102 and for coupling the digital readout logic on die 102 to other off-chip components (e.g., to components on die 104, die 106, and/or other external components).
Analog high voltage die 104 may be stacked on digital readout logic die 102. Analog high voltage die 104 may include a semiconductor substrate such as a silicon substrate 120. High voltage devices, such as n-type transistor N1 and p-type transistor P1, can be formed in semiconductor substrate 120. N-type transistor N1 may represent the high voltage pull-down switch 40 in
A more detailed view of the n-type high voltage (HV) transistor N1 is shown in
A more detailed view of the p-type high voltage (HV) transistor P1 is shown in
Referring back to
Interconnect stack 122 of die 104 may be bonded to interconnect stack 112 at a wafer bonding interface 103. Bonding interface 103 can be formed to ensure that the dielectric material in the interconnect stacks 112 and 122 are properly attached and also to ensure that the conductive routing structures 116 and 126 at bonding interface 103 are properly connected (bonded). Such bonding at interface 103 that ensures both a physical coupling and electrical coupling is sometimes referred to herein as a hybrid bond.
Interconnect stack 122 formed on the front side of semiconductor substrate 120 is illustrative. Furthermore, an interconnect stack such as interconnect stack 142 can be formed on the back side (surface) of semiconductor substrate 120. Interconnect stack 142 may include alternating routing layers and via layers. Each routing layer in interconnect stack 142 can include conductive (metal) routing paths such as metal routing structures 146 formed in a layer of dielectric material. Each via layer in interconnect stack 142 can include conductive (metal) vias such as metal via structures 148 formed in a layer of dielectric material. Interconnect stack 142 is therefore sometimes referred to as a dielectric stack (e.g., an interconnect stack having conductive routing paths formed within dielectric material such as silicon dioxide). The conductive routing structures 146 and the conductive via structures 148 can be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, a metal alloy, a combination of metals, and/or other types of conductive material. The metal routing structures 146 and the metal via structures 148 can form an electrical network for interconnecting together various components within die 104 and for coupling the high voltage devices (e.g., transistors N1 and P1) to the SPADs in sensor die 106.
One or more through silicon via (TSV) structures such as TSV 130 can be formed within analog high voltage die 104. In the example of
Sensor die 106 may be stacked on the back side of the analog high voltage die 104. Sensor die 106 may include a semiconductor substrate such as a silicon substrate 150. An array of SPADs can be formed in semiconductor substrate 150. Each SPAD pixel 30 may include a respective SPAD (see, e.g., SPAD1 and an adjacent SPAD2, etc.). Each SPAD may include an n+ contact 154 formed in a p-type region 155 (e.g., a p-substrate). The n+ contact 154 may serve as the cathode terminal on which a SPAD output voltage is generated, whereas the p-type region 155 may serve as the anode terminal configured to receive bias voltage VBS. In the example of
An interconnect stack such as interconnect stack 152 can be formed on a front side (surface) of semiconductor substrate 150. Interconnect stack 152 may include alternating routing layers and via layers. Each routing layer in interconnect stack 152 can include conductive (metal) routing paths such as metal routing structures 156 formed in a layer of dielectric material. Each via layer in interconnect stack 152 can include conductive (metal) vias such as metal via structures 158 formed in a layer of dielectric material. Interconnect stack 152 is therefore sometimes referred to as a dielectric stack (e.g., an interconnect stack having conductive routing paths formed within dielectric material such as silicon dioxide). The conductive routing structures 156 and the conductive via structures 158 can be formed using copper, aluminum, tungsten, titanium, gold, silver, nickel, a metal alloy, a combination of metals, and/or other types of conductive material. The metal routing structures 156 and the metal via structures 158 can form an electrical network for interconnecting together various components within die 106 and for coupling the array of SPADs to the analog high voltage die 104. The metal routing structures 156 can be coupled to the SPAD cathode terminals (e.g., for reading out the SPAD output voltages) and can be coupled to the SPAD anode terminals (e.g., for providing voltage VBS to bias each SPAD component in the breakdown operating regime).
Interconnect stack 152 of die 104 may be bonded to interconnect stack 142 at a wafer bonding interface 105. Bonding interface 105 can be formed to ensure that the dielectric material in the interconnect stacks 142 and 152 are properly attached and also to ensure that the conductive routing structures 146 and 156 at bonding interface 105 are properly connected (bonded). Such bonding at interface 105 that ensures both a physical coupling and electrical coupling is sometimes referred to herein as a hybrid bond.
One or more through silicon via (TSV) structures such as TSV 160 can be formed within sensor die 106. In some embodiments, TSV structure 160 can extend through the entire depth of semiconductor substrate 150 (e.g., through silicon via 160 can extend from the back side of substrate 150 to at least the front side of substrate 150). TSV structure 160 can extend at least partially into interconnect stack 152 and make an electrical connection with one of the metal routing structures 156 or with a conductive via. If desired, an additional interconnect stack can be formed between substrate layer 150 and passivation layer 170 in wafer 106, and TSV structure 160 can additionally or alternatively extend at least partially into or extend entirely through this additional interconnect stack. The TSV structure 160 can be lined with an insulating layer 162 and filled with conductive material 164. The insulating layer 162 can be formed from silicon dioxide, silicon nitride, silicon oxynitride, or other insulating material. The conductive filler material 164 can be formed from tungsten, aluminum, copper, copper tungsten, titanium, tantalum, a combination of these materials, or other conductive materials suitable for via structures.
A passivation layer such as passivation layer 170 may be formed along the back side (surface) of substrate 150. Passivation layer 170 may be formed using silicon dioxide, silicon nitride, silicon oxynitride, polyimide, other polymers, or other passivation material. Contact pads such as contact pads 172 (e.g., wire bond pads or other types of metal pads) can be formed on passivation layer 170. Contact pads 172 can be coupled to the through silicon vias 160 that traverse substrate layer 150 of sensor die 106. During operation of SPAD circuitry 100, incoming light 174 can enter through the back surface of sensor die 106 (i.e., the back side of sensor die substrate 150). Operated in this way, SPAD circuitry 100 can be referred to as a backside illuminated (BSI) SPAD-based sensor.
An image system as described herein may have a SPAD pixel vertically stacked with HV devices and corresponding readout logic. A SPAD may be connected to HV devices through an interconnect stack comprising TSVs and conductive vias. The HV devices may further be connected to external contact pads using another such interconnect stack. In some implementations, the HV devices are vertically stacked with the corresponding readout logic for the SPAD through another interconnect stack, and the readout logic is then connected to external contact pads through yet another interconnect stack. Arranged in the way shown in
The process of fabricating SPAD circuitry 100 of
During the operations of block 404, digital readout logic wafer 102 can be bonded to analog high voltage wafer 104. The result of block 404 can be shown in
During the operations of block 406, the handling wafer 302 can be removed from the backside of analog high voltage wafer 104. For example, handling (carrier) wafer 302 can be removed using a mechanical grinding and/or a wet etch process. The wet etch process can involve using an etchant that can selectively remove carrier wafer 302 while stopping at the buried oxide layer 300 (e.g., the wet etchant will only minimally remove silicon dioxide). The result of block 406 can be shown in
During the operations of block 408, the back side of analog high voltage wafer 104 can be processed. For example, interconnect stack 142 can be formed on the back side (surface) of semiconductor substrate 120 (see, e.g.,
During the operations of block 410, the front side of sensor wafer 106 can be processed. For example, interconnect stack 152 can be formed on the front side (surface) of semiconductor substrate 150 (see, e.g.,
During the operations of block 412, sensor wafer 106 can be bonded to the back side of analog high voltage wafer 104. The result of block 412 can be shown in
During the operations of block 414, the back side of sensor wafer 106 can be processed. For example, the p+ silicon layer 310 of
The operations of
The embodiments above described in connection with
Various embodiments of SPAD circuitry are included. An aspect of the disclosure provides circuitry that includes a first die having a plurality of single-photon avalanche diodes (SPADs), where each SPAD in the plurality of SPADs has an anode terminal configured to receive a bias voltage and a cathode terminal, and a second die having a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first die. The first die can be stacked on a back side of the second die. The first die can include a first semiconductor substrate layer in which the plurality of SPADs are formed, a first interconnect stack of alternating routing and via layers on a front surface of the first semiconductor substrate layer, and a first through silicon via (TSV) extending from a back surface of the first semiconductor substrate layer to the front surface of the first semiconductor substrate layer and at least partially into the first interconnect stack. The second die can include a second semiconductor substrate layer in which the plurality of switches are formed, a second interconnect stack of alternating routing and via layers on a back surface of the second semiconductor substrate layer, a second through silicon via (TSV) extending from the back surface of the second semiconductor substrate layer to a front surface of the second semiconductor substrate layer, and a third interconnect stack of alternating routing and via layers on the front surface of the second semiconductor substrate layer, wherein the second TSV extends at least partially into the third interconnect stack.
The plurality of switches can include p-type transistors having drain terminals coupled to routing structures in the second interconnect stack and having source and gate terminals coupled to routing structures in the third interconnect stack and optionally n-type transistors having drain terminals coupled to the routing structures in the second interconnect stack and having source and gate terminals coupled to the routing structures in the third interconnect stack. The circuitry can include a third die having digital readout logic coupled to the plurality of switches in the second die, where the second die is stacked on a front side of the third die. The third die further can include a third semiconductor substrate layer in which the digital readout logic are formed and a fourth interconnect stack of alternating routing and via layers on a front surface of the third semiconductor substrate layer.
An aspect of the disclosure provides a method that includes forming a first wafer that includes a plurality of single-photon avalanche diodes (SPADs), where each SPAD in the plurality of SPADs has an anode terminal configured to receive a bias voltage and a cathode terminal, forming a second wafer that includes a plurality of switches coupled to the cathode terminals of the plurality of SPADs in the first wafer, and bonding the first wafer to the second wafer. The method can further include forming a third wafer that includes digital readout logic coupled to the plurality of switches in the second wafer and bonding the third wafer to the second wafer. The method can further include forming through silicon via (TSV) structures through a semiconductor substrate layer in the first wafer and forming through silicon via (TSV) structures through a semiconductor substrate layer in the second wafer.
An aspect of the disclosure provides an apparatus that includes a sensor die having a plurality of single-photon avalanche diodes (SPADs), a digital die having digital readout logic powered by a first positive voltage, and an analog die having switches powered by a second positive voltage greater than the first positive voltage, where the analog die is vertically stacked between the sensor die and the digital die. The analog die can have a front side configured to face the digital die and can have a back side configured to face the sensor die. The apparatus can include first through silicon via (TSV) structures in the sensor die and second through silicon via (TSV) structures in the analog die. At least some of the second TSV structures can be coupled to routing structures in the sensor die and to routing structures in the digital die.
The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.
