The present invention specifically relates to interconnect structures for microelectronics, e.g., in the packaging of microelectronic units such as integrated circuits (“ICS” or “chips”) and other interconnect structures, e.g., circuit panels such as includes printed or other types of wiring boards.
In some multi-layer wiring boards, a heat-curable resin such as an epoxy resin is used as an insulator within each wiring level. Interconnections are patterned after a curing reaction performed while the cured substrate is held tightly in a fixture. In this way, interconnections do not twist or break as a result of joining the wiring levels and insulators together in one multilayer board.
Unfortunately, when wiring levels of a multilayer wiring board are insulated by a thermoplastic, presently available methods produce unsatisfactory results. The thermoplastic insulators of each level are joined at temperatures near the melting point of the thermoplastic resin. This causes the metal interconnects within such multilayer wiring boards to twist, short with adjacent interconnections, break, or the like.
In such boards, because the metal interconnect layer protrudes above the surface of each interlayer insulation layer, there was a tendency to have indentations and protrusions on the surfaces of the wiring board layers that make up the multilayer wiring board. When multilayer wiring boards are produced through joining together a plurality of these wiring board layers, the greater the number of layers, the larger the indentations and protrusions on the surface of the multilayer wiring boards. Given this, as wiring boards, the interconnection patterns could become distorted, the adjacent interconnections could short to each other, interconnections could break, and the like, producing fatal defects. In addition, electronic components mounted to such multilayer wiring boards, such as semiconductor integrated circuits, large-scale integrated circuits, and the like, in particular, have large numbers of small terminals. Accordingly, it is highly desirable to maintain the planarity of each set of metal interconnects on an interconnect element or multilayer wiring board. In some cases, large deviations from planarity of the surface of interconnect element on which electronic components such as a chip is mounted is an impediment to high-reliability mounting.
Consequently, excessive indentations and protrusions on the surface of a multilayer wiring board causes problems that cannot be ignored, and thus must be eliminated.
Secondly, given the conventional technology described above, the production of a single multilayer wiring board can require layering process in which one wiring board is joined to another wiring board and in which another wiring board is then joined to the layered unit produced by the prior joining process. This process would then be repeated multiple times, resulting in many manufacturing steps for the multilayer wiring board, making reductions in manufacturing costs difficult.
A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.
According to an aspect of the invention, a multilayer interconnect element is provided which includes a dielectric element having a first major surface, a second major surface remote from the first major surface, a plurality of first recesses extending inwardly from the first major surface and a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses, the plurality of first metal interconnect patterns having outer surfaces which are substantially co-planar with the first major surface and having inner surfaces remote from the outer surfaces. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses. The plurality of second metal interconnect patterns have outer surfaces which are substantially co-planar with the second major surface and inner surfaces remote therefrom. A plurality of solid metal posts conductive connecting the inner surfaces of the plurality of first metal interconnect patterns to the inner surfaces of the plurality of second metal interconnect patterns.
According to another aspect of the invention, a multilayer interconnect element is provided which has a top major surface and a bottom major surface remote from the top major surface. The multilayer interconnect element includes a first interconnect element and a second interconnect element joined thereto. The first interconnect element includes a first dielectric element having a first major surface exposed at the top major surface, a second major surface remote from the first major surface, and a plurality of first recesses extending inwardly from the first major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses, the plurality of first metal interconnect patterns having outer surfaces substantially co-planar with the first major surface, the plurality of first metal interconnect patterns further having inner surfaces remote from the outer surfaces. The first interconnect element further includes a plurality of solid metal posts conductively contacting and extending from the inner surfaces of the first metal interconnect patterns towards the second major surface of the first dielectric element.
The second interconnect element includes a plurality of second metal interconnect patterns that are in conductive communication with the plurality of first metal interconnect patterns. The plurality of second metal interconnect patterns have outer surfaces exposed at the bottom surface of the multilayer interconnect element, the outer surfaces being co-planar with a dielectric element that is exposed at the bottom surface, that dielectric element being either the first dielectric element or another (second) dielectric element other than the first dielectric element.
According to one or more preferred aspects of the invention, the multilayer interconnect element may further include one or more intermediate interconnect elements each including at least one intermediate dielectric element, and at least a plurality of intermediate metal interconnect patterns, the one or more intermediate interconnect elements being disposed between the first and second interconnect elements and providing conductive interconnection between the first and second interconnect elements.
According to one or more preferred aspects of the invention, each of the one or more intermediate interconnect elements includes a plurality of metal posts extending from the plurality of intermediate metal interconnect patterns through the at least one intermediate dielectric element.
According to one or more preferred aspects of the invention, the plurality of metal interconnect patterns of the one or more intermediate interconnect elements have exposed surfaces which are not co-planar with exposed surfaces of the at least one intermediate dielectric element.
According to another aspect of the invention, a method is provided for fabricating an interconnection element. Such method includes providing structure including a first metal layer overlying a second metal layer. A plurality of metal interconnect patterns are patterned from the first metal layer. A plurality of solid metal posts are provided in conductive communication with at least some of the plurality of metal interconnect patterns. A dielectric element is provided which overlies the structure, the dielectric element providing insulation between the plurality of metal posts. The second metal layer is removed selectively to the plurality of metal interconnect patterns to provide the interconnection element having the plurality of metal interconnect patterns embedded in the dielectric element.
According to one or more preferred aspects of the invention, the plurality of metal interconnect patterns have outer surfaces, the outer surfaces being co-planar with a first major surface of the dielectric element.
According to one or more preferred aspects of the invention, the step of forming the dielectric element includes pressing a layer including an uncured resin onto the plurality of metal posts and the plurality of metal interconnect patterns.
According to one or more preferred aspects of the invention, the uncured resin of the dielectric element is cured after pressing the dielectric element onto the plurality of metal posts.
According to one or more preferred aspects of the invention, the plurality of metal posts are formed by forming a mask layer overlying the plurality of metal interconnect patterns, at least some of the plurality of metal interconnect patterns being exposed within openings in the mask layer. A metal is then selectively plated onto the at least some of the plurality of metal interconnect patterns.
According to one or more preferred aspects of the invention, the plurality of metal interconnect patterns includes a plurality of first metal interconnect patterns and the dielectric element includes a second major surface remote from the first major surface. According to such aspect, such method further includes providing a plurality of second metal interconnect patterns in conductive communication with the plurality of solid metal posts, the plurality of second metal interconnect patterns having outer surfaces substantially co-planar with the second major surface of the dielectric element.
According to yet another aspect of the invention, a method is provided for making a multilayer interconnect element which has an exposed dielectric element and exposed metal interconnect patterns. In such interconnect element, the metal interconnect patterns have outer surfaces which are substantially co-planar with the dielectric element.
Such method includes providing a first interconnect element including at least one dielectric layer, at least one interconnect layer including a plurality of raised metal interconnect patterns overlying the dielectric layer and a plurality of interlayer conductors extending from the plurality of raised metal interconnect patterns through the at least one dielectric layer.
Such method further includes providing a second interconnect element having an exposed dielectric element and a plurality of exposed metal interconnect patterns having outer surfaces substantially co-planar with the exposed dielectric element, the second interconnect element including a plurality of metal posts extending from inner surfaces of the plurality of metal interconnect patterns through the exposed dielectric element.
The first interconnect element is joined to the second interconnect element such that the plurality of metal posts conductively interconnect the exposed metal interconnect patterns to the raised metal interconnect patterns and the exposed dielectric element overlies the dielectric layer of the first interconnect element.
According to certain embodiments of the invention, a multilayer interconnect element or multilayer wiring board is provided wherein metal traces of an interconnection layer are embedded within recesses at the surface of a dielectric element. In addition, the metal traces are formed in such manner that they are much less prone to become twisted, or produce shorts with adjacent interconnections, or break, even when the number of interconnect elements joined together is high. In such embodiments, the surface of each interconnect element presents a substantially planar major surface having conductive contacts thereon for interconnection with other microelectronic elements. In this way, the metal traces do not protrude in ways which interfere with mounting electronic components. Also, improved reliability of the electrical connections may be achieved between several interconnect elements that make up a multilayer interconnect element or multilayer wiring board having three or more layers on which such embedded metal traces are provided. In addition, it may be possible to achieve a reduction in the manufacturing processes required to fabricate such interconnect elements.
In an interconnect element 22 according to an embodiment of the present invention shown in
Embedded within the dielectric element 20 are first interconnection patterns 12, 12a provided as a first metal wiring layer and second interconnection patterns 13, 13a provided by a second metal wiring layer. Each of the first interconnect patterns and the second interconnect patterns includes a plurality of metal traces and contacts or other metallic interconnect features. The thickness of each metal wiring layer is preferably between about 10 microns and several dozen microns. The contacts and metal traces function to provide conductive interconnection between the interconnect element 22 and other microelectronic elements external thereto and/or between different external microelectronic elements. Such microelectronic elements can be, for example, any of microelectronic substrates, circuit panels, integrated circuits (“ICs” or “chips”), packaged chips, i.e., chips having package elements bonded thereto, whether or not such chips include only active circuit elements, passive circuit elements such as commonly known as “integrated passives on chip” (IPOC) or chips having a combination of active and passive types of circuit elements, among others.
A plurality of solid metal posts 18 extend through the dielectric element 20 between the first interconnect patterns 12 and the second interconnect patterns 13. The posts most preferably include or consist essentially of copper. Preferably the posts include high purity copper. The end-to-end length or “height” of each post within the dielectric element 20 is preferably between, for example, several dozen and about 150 microns. However, the height may be somewhat greater than or less than the stated preferred range.
In a particular embodiment a chip, circuit panel or packaged chip is directly or indirectly conductively interconnected to or bonded to interconnection patterns 12, 12a including traces and contacts exposed at a first major surface 24 of the interconnect element 22. On a second major surface 26 of the interconnect element 22 remote from the first major surface 24, contacts 13, 13a of the interconnect element can be further bonded, directly or indirectly, to a circuit panel, another chip, or package element of another packaged chip. In another embodiment, the metal traces on one or both major surfaces 24, 26 of the interconnect element 22 can be contacted by a packaged chip and maintain conductive communication with the packaged chip under a moderate amount of pressure in which some flexing of the dielectric element 20 may occur as a result of the pressure between the interconnect element and the packaged chip.
In an embodiment of manufacturing a multilayer interconnect element or wiring board, heating to a temperature of, for example, between 150 and 350° C. is suitable, and a pressure between 20 and 100 kg/cm2 is preferred. In addition, it is preferable to coat the metal traces exposed at one or both of the first and second major surfaces 24, 26 with a bond metal, especially when electronic components are to be mounted thereto such as integrated circuits (ICs or chips) that have high numbers of terminals with minute pitches. Gold is well suited for use as the bond metal layer 10.
The details of the present invention will be explained based on an embodiment shown in a figure.
First, a patternable conductive structure 2, made from a three metal layer structure is prepared as shown in
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Following this, the first such interconnect structure 2′, having an insulating layer 20 is formed in the state shown in
This joining process connects the metal posts 18 to the interconnect patterns, doing so through metal-to-metal bonding of the posts 18 to the interconnect patterns 13 and 13, especially via copper-to-copper contact. This process integrates the two structures 2 and 2′ into a single unit.
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Given this type of method for manufacturing, an interconnect element or wiring board is fabricated wherein the interconnection layer and the insulating layer are co-planar as shown in
As shown in
Note that each of the aforementioned patternable conductive structures 32 have three-layer structures wherein a metal layer 40 for fabricating an interconnection layer including or consisting essentially of copper, for example, overlies an etching barrier layer (an intermediate layer) 34, which includes or consists essentially of a metal that would not be attacked by an etchant which attacks the first metal. For example, when the first metal includes or consists essentially of copper, and the etching barrier layer can include or consist essentially of nickel. Copper can be etched by an etchant which substantially does not attack nickel. In turn, the first metal 40 and the etching barrier layer 34 are provided on or overlying a surface of a carrier layer 36 made from, for example, copper. The patternable conductive structure is preferably fabricated through rolling, although other methods can be used.
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Each of the aforementioned interconnection structures 52 and 52 includes an interconnection layer including interconnection patterns 60. The interconnection layer may include or consist essentially of copper, for example. In turn, the interconnection layer overlies an etching barrier layer (an intermediate layer 56), made from, for example, nickel. The etching barrier layer, in turn, overlies a carrier layer 54, made from, for example, copper. Moreover, each of these interconnection structures 52 and 52 are oriented so that the sides whereon the interconnect patterns 60 are formed are facing each of the interlayer insulation layers 50 and 50, and are provided aligned so that the various electrically conductive pillars 48 will be lined up with the corresponding interconnection layers 60.
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Following this, the aforementioned carrier layers 54 (
Following this, each of the aforementioned etching barrier layers 58 and 38
This type of method for manufacturing fabricates an interconnect element 55 or a wiring board such as shown in
Furthermore, because the fabrication processes for the two interconnect elements or wiring boards progress simultaneously for both sides until the interconnect elements are separated from the core material 30, this can improve the manufacturing efficiency and can increase the productivity.
In this embodiment, the same structure as shown in
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When this is done, first interconnect patterns 61, overlying one major surface 63 of the interlayer insulation layer (dielectric element), protrude above the major surface 63 of the interlayer insulation layer 50, as shown in
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Each of the aforementioned outer interconnect elements 72 and 72 includes interconnect patterns 86, which include or consist essentially of a metal such as copper which overlies an etching barrier layer 84. The etching barrier includes or consists essentially of a material such as, for example, nickel, which is not attached by an etchant which attacks the metal from which interconnect patterns 86 are made. The etching barrier layer 84, in turn, overlies a carrier layer 82, preferably including or consisting essentially of copper. A plurality of metal posts or electrically conductive pillars 88, preferably including or consisting essentially a metal such as copper extend from the interconnect patterns 86. An interlayer insulation layer 90 covers an inner surface of the interconnect patterns 86 and fills a space between the electrically conductive pillars 88. End surfaces 89 of the electrically conductive pillars 88 are exposed at an outer surface 91 of the interlayer insulation layer 90.
Furthermore, on both surfaces of the core substrate 70, interconnect elements 72 and 72 are positioned, oriented so that the end surfaces 89 of the electrically conductive pillars 88 and 88 and the outer surface 91 of the interlayer insulation layer 90 are facing the core substrate 70. The interconnect elements and the core substrate are aligned so that each of the electrically conductive pillars 88 and 88 line up with the positions of each of the outer interconnect patterns 78 and 78 of the core substrate 70.
Following this, heat and pressure are applied to join, e.g., bond, adhere or fuse the aforementioned interconnect elements 72 and 72 onto the exposed surfaces of dielectric layers and interconnect patterns 78 of the aforementioned core substrate 70.
This joining process not only strongly connects the end surfaces of each of the electrically conductive pillars 88 and 88 to the outer interconnect patterns 78 of the core substrate 70 through copper-copper bonding, but also integrates, adheres, bonds or preferably fuses the interlayer insulation layers 74 and 90 to each other.
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Following this, the aforementioned etching barrier layers 84 are removed through, for example etching, as shown in
This type of method for manufacturing can provide a multilayer interconnect element or wiring board wherein the outermost surfaces are flat and in which interconnect patterns are embedded in and are co-planar with those outermost surfaces. Such method utilizes a core substrate 70 as a base, which has indentations and protrusions on the surfaces thereof, due to the interconnection layers 78. Thereafter, the aforementioned interconnect elements 72 and 72 are aligned and joined thereto so that the electrically conductive pillars 88 and the exposed surfaces 91 of the interlayer insulation layers 90 face inward toward the core substrate 70, and so that the interconnect patterns 86 and 86 face outward.
Note that although in the embodiment described above, the number of layers for the core substrate 70 is four, and the number of layers in the multilayer interconnect element or wiring board produced therefrom is six, this is only a single example. The number of layers in the core substrate 70 is not limited to four, but rather may be a different number of layers, enabling the provision of a multilayer wiring board having a number of layers that is two layers more than the number of layers in the core substrate 70.
First, the method for manufacturing the interconnect elements 111 will be explained with reference to
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Following this, on the exposed surfaces of the aforementioned interconnect patterns 108, as is shown in
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Following this, the ends of the aforementioned electrically conductive pillars 114 are polished or ground to adjust the height and to planarize them to the surface of the interlayer insulation layer 116, to complete the interconnect element 118, as shown in
Note that two of these interconnect elements 118 are prepared, and provided according to the processes shown in
The method for manufacturing to provide a multilayer interconnect element or wiring board according to the present embodiment will be explained next with reference to
First, as shown in
In this core interconnect element 120, four interconnection layers 122 are provided on the inside thereof, each separated and insulated from others of the layers 122 by interlayer insulation layers 124. Metal layers 126 and 126 are provided on the outermost surfaces.
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Following this, a metal layer 134, including or consisting essentially of a metal such as copper, for example, is fabricated on the surface, as shown in
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The interconnect elements 118 and 118 are arranged so that the ends of the electrically conductively pillars 114 and the interlayer insulation layers 116 face the exposed surfaces of the interconnection layer 136 of the core interconnect element 120. The interconnect elements are aligned so that each of the electrically conductively pillars 114 are lined up with the interconnection layers 136 corresponding thereto. Thereafter, pressure and heat are applied to bond, adhere or fuse the interconnect elements 118 to the core interconnect element 120.
Following this, the carrier layers 102 and 102 (
This method of manufacturing produces a multilayer interconnect element or wiring board that has through holes for electrical connection between layers thereof and which has flat outer surfaces.
First, referring to
First the interconnect elements 182 (
This interconnect element 182 can be made through preparing a three-layer metal structure 180 (
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Following this, a plurality, or in the example as specifically shown, three interconnect elements 194 are stacked with interlayer insulation layers 202 interposed there between, after which the aforementioned interconnect elements for the outermost layers 182 are stacked at specific positions on both outside surfaces of the stack. Thereafter, heat and pressure are applied to join the interconnect elements 182 as outermost layers with the interconnect elements 194 disposed between them to join the components 202, 194, 194, 194, and 202.
Following this, the carrier layers 184 (
Following this, a plated underlayer 206, including or consisting essentially of a metal such as copper, for example is fabricated by electroless plating on the surface of the aforementioned layered unit, including the inner peripheral surface of the aforementioned through holes 204, after which a resist layer 208, which will serve as the mask layer for through hole fabrication, is deposited and patterned, e.g. by photolithography.
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Following this, the aforementioned resist layer 208 (
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Following this, a second interconnect element 158a, structured from the aforementioned interconnect element 158, with the electrically conductive pillars 156 removed from the interconnect element 158 (or, more precisely, a structure wherein the electrically conductive pillars 156 were not fabricated) is provided.
Given this, the surface 155 of the interconnect element 158 from which the electrically conductive pillars 156 and the interconnection layer 150 extend and the surface 155 from which the interconnection layer 150 of the interconnect element 158a extends are disposed facing each other, and aligned so that each of the electrically conductive pillars 156 of interconnect element 158 contacts the corresponding interconnection layer 150 of interconnect element 158a. An interlayer insulation layer 160 is interposed between the interconnect element 158a and the interconnect element 158. In this state, heat and pressure are applied to join, e.g. bond, adhere or fuse the interconnect elements 158a and 158 together.
Following this, the carrier layers 142 and 142 of the interconnect elements 158 and 158a are removed, after which the etching barrier layers 144 and 144 are also removed. Thereafter, the aforementioned metal underlayers 146 and 146 are also removed.
This provides a multilayer interconnect element or wiring board wherein interconnection layers 150 are fabricated on both surfaces of an interlayer insulation layer 160, co-planar therewith.
The multilayer interconnect elements or wiring boards shown and described in this embodiment are similar to those described above, having a structure in which outermost surfaces of the dielectric elements are flat and interconnect patterns exposed at those surfaces are co-planar thereto.
On the other hand, with reference to
Referring to
As these and other variations and combinations of the features set forth above can be utilized, the foregoing description of the preferred embodiment should be taken by way of illustration rather than by limitation of the invention.
The present invention can be used in, among others, in interconnect elements, e.g., wiring boards, etc. wherein a plurality of metal traces of an interconnection layer are exposed at one of the surfaces of a dielectric element, e.g., an interlayer insulation layer made from, for example, a resin such as a thermoplastic. Posts or interlayer contact pillars, made from a metal such as, for example, copper extend through such dielectric element. Such posts or pillars can provide interlayer connections corresponding to at least portions of interconnection layers of respective layers of a multilayer wiring boards. In addition, the present invention finds use in methods of making interconnect elements and in methods of manufacturing multilayer wiring boards.
Number | Date | Country | Kind |
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2004-294260 | Oct 2004 | JP | national |
This application is a continuation of U.S. patent application Ser. No. 11/643,724, filed Dec. 21, 2006, which is a continuation of U.S. patent application Ser. No. 11/410,388, filed Apr. 25, 2006, which is a continuation of U.S. patent application Ser. No. 11/246,402 filed Oct. 6, 2005, the disclosure of which is hereby incorporated by reference, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2004-294260, filed Oct. 6, 2004, the entire contents of which is incorporated herein by reference.
Number | Date | Country | |
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Parent | 11643724 | Dec 2006 | US |
Child | 11897200 | US | |
Parent | 11410388 | Apr 2006 | US |
Child | 11643724 | US | |
Parent | 11246402 | Oct 2005 | US |
Child | 11410388 | US |