Patent Application
20080308309
1. Field of the Invention
The present invention relates to a structure of a packaging substrate having capacitors embedded therein and a method for fabricating the same, which can reduce the parasitic capacitance, avoid the formation of voids and poor uniformity of thickness resulted from the high dielectric material layer of prior art.
2. Description of Related Art
Currently, the relentless progress in semiconductor fabricating process and electronic functions of microelectronic devices has lead to a highly integrated development of semiconductor chips. Quantity of input/output terminals and density of wiring in package structures increase as semiconductor chips develop toward high integration. However, as the density of wiring in a package structure increases, the noise also increases. Generally, in order to obviate noise or compensate electricity, passive components, e.g. resistors, capacitors, and inductors, are installed in a semiconductor chip package structure to eliminate noise and to stabilize circuits to thereby meet the requirements of microelectronic devices.
In conventional methods, utilizing surface mount technology (SMT) integrates most passive components onto a surface of a packaging substrate, such that the flexibility of wiring layout on the surface is restricted, and the occupied space is unfavorable to shrinkage of package size.
In view of the aforementioned drawbacks, many studies relative to lamination methods have appeared in recent years. High dielectric coefficient material is laminated between two copper layers and then electrode plates and circuits are formed to fabricate capacitors.
However, the prior art forms a whole piece of high dielectric material layer within a packaging substrate, wherein the used part of the high dielectric material layer for a capacitor is merely the one between the inner electrode plate and the outer electrode plate, while the unused part of the high dielectric material layer electrically contacts with the circuits, such that the structure has several drawbacks: first, the unused part of the high dielectric material layer causes waste, unfavorable to reduce the cost; second, owing to the poor fluidity of the high dielectric material, voids and poor uniformity of thickness occur; third, the unused part of the high dielectric material layer electrically contacts the circuits, so that parasitic capacitance occurs to interfere with electrical qualities; finally, because the electrode plates and the circuits are laid together in a circuit layer, such that the flexibility of layouts of both the electrode plates and the circuits is compromised.
Therefore, it is desirable to provide a structure of a packaging substrate having capacitors embedded therein and a method for fabricating the same, to thereby reduce the parasitic capacitance, avoid the formation of voids and poor uniformity of thickness.
In order to resolve the aforementioned disadvantages, the present invention provides a structure of a packaging substrate having capacitors embedded therein, comprising a core substrate, a dielectric layer, and an outer circuit layer. The core substrate has an inner circuit layer on each of two surfaces thereof. The dielectric layer is disposed on each of two sides of the core substrate, wherein a plurality of first conductive vias are disposed at least in one of the dielectric layers, each connecting to the inner circuit layer through a piece of outer electrode plate, a piece of high dielectric material layer, a piece of inner electrode plate, and a piece of adhesive layer in sequence. The outer circuit layer is disposed on the surface of each of the dielectric layers, wherein the first conductive vias electrically connects to the outer circuit layer of the same side. The capacitors are each composed of a piece of the outer electrode plate, a piece of the high dielectric material layer and a piece of the inner electrode plate.
The above structure further comprises in the dielectric layer at least one second conductive via electrically connecting the inner circuit layer and the outer circuit layer.
The above structure further comprises an outer plated through hole electrically connecting the outer circuit layers on the surfaces of the dielectric layers on two sides of the core substrate.
In the above structure the core substrate further comprises an inner plated through hole, so as to connect the inner circuit layers on two sides of the core substrate.
The packaging substrate structure having capacitors embedded therein can save production a lot of high dielectric material, avoid the formation of voids, and reduce the parasitic capacitance between the circuits.
The present invention also provides a method for manufacturing a structure of a packaging substrate having capacitors embedded therein, comprising the following steps: providing a metal plate first, wherein a plurality of high dielectric material layer pieces are formed on parts of the surface of the metal plate, and forming an inner electrode plate on the surface of the high dielectric material layer pieces each; subsequently, forming an adhesive layer on the surface of the inner electrode plate; then, connecting the metal plate through the adhesive layers to an core substrate having inner circuit layers formed on the two surfaces thereof; next, thinning the metal plate; removing the portion of the metal plate not connected to the high dielectric material layer pieces to form a plurality of outer electrode plates (i.e. the parts of the metal plate connecting to the high dielectric material layer pieces), and thereby accomplishing capacitors each consisting of a piece of outer electrode plate, a piece of high dielectric material layer and a piece of inner electrode plate; forming a dielectric layer on both surfaces of the core substrate by lamination, and forming in the dielectric layer a first via right on each of the outer electrode plates; and finally, forming by electroplating a first conductive via on the inside wall of each of the first vias as well as an outer circuit layer on the surfaces of the dielectric layer on each side of the core substrate at the same time.
In the present invention, in the dielectric layer at least one second via touching the inner circuit layer of the core substrate can further be formed after lamination of the dielectric layer. Then a second conductive via is formed in the second via at the same time when forming the first conductive vias and the outer circuit layers.
In addition, at least one through hole can be further formed in the dielectric layer before electroplating. The through hole extends through the core substrate and the dielectric layers on both sides of the core substrate. Then an outer plated through hole is formed in the through hole at the same time when forming the first conductive vias and the outer circuit layers.
In the present invention, an inner plated through hole can be further formed in the core substrate so as to connect the inner circuit layers on two sides of the core substrate.
The present invention can enhance the flexibility of layout of passive components and the circuit in the packaging substrate, as well as the usable surface area of the packaging substrate to meet the requirement of miniaturization.
In addition, the process of the present invention, fabricating a capacitor on the metal plate and then utilizing conductive vias or through holes for electro-connections, can save materials, avoid the formation of voids and poor uniformity of thickness, reduce the parasitic capacitance between the circuits, and simplify the process.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Subsequently, outer circuit layers 30,30′ are disposed respectively on the surface of the dielectric layers 26,26′. The structure further comprises an outer plated through hole 32, which connects the outer circuit layers 30,30′ on the surfaces of the dielectric layer 26,26′. The material of the outer circuit layers 30,30′ and the outer plated through hole 32 is copper, tin, nickel, chromium, titanium, a copper/chromium alloy, or a tin/lead alloy. In the present embodiment, the material is copper.
The packaging substrate structure having capacitors embedded therein can save production a lot of high dielectric material, avoid the formation of voids, and reduce the parasitic capacitance between the circuits.
The present invention also provides a manufacturing method for a structure of a packaging substrate having capacitors embedded therein, as shown in
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The present invention can enhance the flexibility of layout of passive components and the circuit in the packaging substrate, as well as the usable surface area of the packaging substrate to meet the requirement of miniaturization.
In addition, the process of the present invention, fabricating a capacitor on the metal plate and then utilizing conductive vias or through holes for electro-connections, can save materials, avoid the formation of voids and poor uniformity of thickness, reduce the parasitic capacitance between the circuits, and simplify the process.
Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
