Patent Application
20240234280
The present invention relates to substrates with a support and semiconductor devices.
When mounting semiconductor elements having fine wiring circuits on motherboards, the spacing between and size of electrodes serving as junction terminals of the semiconductor element do not necessarily match those of the motherboard. To address this, an intermediate substrate called a flip chip-ball grid array (FC-BGA) substrate is generally used between the semiconductor element and the motherboard. Such an intermediate substrate makes it possible to establish connection by converting the spacing between and size of the electrodes.
However, due to the increasing demand for faster and more highly integrated semiconductor devices, the FC-BGA substrates on which semiconductor elements are mounted are also required to have junction terminals with a narrower pitch and finer wiring.
On the other hand, for the spacing between the junction terminals between the FC-BGA substrate and the motherboard, they are required to have a pitch that is almost the same as the conventional pitch.
In order to cope with the narrowing of the pitch of the junction terminals of semiconductor elements and the accompanying miniaturization of the wiring in FC-BGA substrates, a multilayer wiring board having fine wiring is used between the FC-BGA substrate and the semiconductor element as an additional intermediate substrate also called an interposer.
Techniques for mounting a plurality of semiconductor elements on an FC-BGA substrate via such an interposer have emerged.
Early interposers were manufactured using a technique in the semiconductor element manufacturing process corresponding to a silicon wafer processing technique. However, when the semiconductor element manufacturing process is used, there is a problem that the manufacturing cost increases. In addition, regarding the interposers produced using silicon wafers, problems with their transmission characteristics due to the electrical characteristics of silicon itself have been pointed out.
There is also a method for forming a multilayer wiring board having a narrow pitch on the FC-BGA substrate by forming the interposer with a support such as a glass substrate and removing the substrate after mounting this on the FC-BGA substrate. This method is disclosed in PTL 1.
However, glass interposers have a problem in the processability of glass.
As a technique to compensate for the defects glass interposers have, there is a technique of forming an interposer using an organic insulating resin.
In the case where an interposer formed using an organic insulating resin is used, the wiring board is formed using an organic insulating resin and a wiring material on a support called a carrier. After mounting semiconductor elements on the wiring board and sealing it with resin, the support is removed, and the sealed wiring board is attached to the FC-BGA substrate to form a semiconductor device (PTL 2).
[Citation List] [Patent Literature] PTL 1: WO2018/047861; PTL 2: US 2021/0050298 A.
However, when an interposer is formed using an organic insulating resin, thermal changes may cause the conduction layer of the wiring board to peel off or the organic insulating resin to crack because the organic insulating resin has a larger coefficient of thermal expansion (CTE) than the FC-BGA.
In the method in which a multilayer wiring board is formed on a support, such as a glass substrate, and this is mounted on an FC-BGA substrate, followed by separating the support, a semi-additive method is often used when forming a multilayer wiring layer on the support. However, insulating resin layers formed using such a semi-additive method contain no filler and tend to have a lower elastic modulus and a higher coefficient of thermal expansion (CTE), compared to filler-containing underfill layers and solder resist layers used in later processes.
In other words, if the surrounding temperature changes significantly after the interposer is attached to the FC-BGA, only the organic insulating resin in the wiring board deforms significantly, causing the wiring board to warp or generating stress inside the wiring board. Consequently, fine wiring layers or other layers may be peeled, or cracking may occur, originating from the areas of peeling or the areas where stress is concentrated.
The present invention has been made in light of the issues set forth above and aims to provide a wiring board or a substrate with a support, which relieves stress inside the wiring board and is less likely to cause cracking originating from areas where stress is concentrated, and to provide a semiconductor device.
In order to solve the above issues, a substrate with a support according to the present invention is a substrate with a support, the substrate including a support and a wiring board provided on the support, wherein
In order to solve the above issues, a wiring board unit according to the present invention includes
According to the present invention, there can be provided a substrate with a support which relieves stress inside the wiring board and is less likely to cause cracking originating from areas where stress is concentrated, and to provide a semiconductor device.
Furthermore, in a method in which a fine wiring layer (corresponding to the second wiring board) is formed on a support substrate, the wiring layer on the support substrate is mounted, for example, on an FC-BGA wiring board (corresponding to the first wiring board), and semiconductor chips are mounted on the second wiring board, stress inside the second wiring board can be relieved, cracking originating from areas where stress is concentrated can be prevented, and reliability of the wiring board unit can be improved.
Problems, configurations, and advantageous effects other than those described above will be clarified in the following description on modes for carrying out the invention.
With reference to the drawings, some embodiments of the present invention will be described. In the following description of the drawings, components identical with or similar to each other are given the same or similar reference signs. It should be noted that the drawings are only schematically illustrated, and thus the relationship between thickness and planar dimensions of the components, the thickness ratio between the layers, and the like are not to scale. Accordingly, specific thicknesses or dimensions should be understood referring to the following description. As a matter of course, dimensional relationships or ratios may be different between the drawings.
The embodiments described below only exemplify devices or methods embodying the technical idea of the present invention. The technical idea of the present invention should not limit the materials, shapes, structures, layouts, and the like of the components to those described below. The technical idea of the present invention can be modified in various ways within the technical scope defined in the claims.
In the present disclosure, the term “surface” may refer to not only the surface of a plate-like member but also, for a layer included in the plate-like member, an interface with the layer that is substantially parallel to the surface of the plate-like member. The term “upper surface” or “lower surface” refers to a surface shown in the upward or downward direction in a drawing when a plate-like member or a layer included in the plate-like member is shown in the drawing. The term “upper surface” or “lower surface” may also be referred to as “first surface” or “second surface”.
The term “side surface” refers to a surface or a thick part of a plate-like member or of a layer included in the plate-like member. Furthermore, part of a surface and a side surface may be collectively referred to as “edge portion”.
The term “above” refers to the vertically upward direction when a plate-like member or a layer is horizontally placed. The term “above” and the term “below” that is opposite to the “above” may be referred to as “Z-axis direction”, and the horizontal direction may be referred to as “X-axis direction” or “Y-axis direction”.
The term “planar shape” or “in plan view” refers to a shape when a surface or a layer is seen from above. The term “cross-sectional shape” or “as viewed in cross section” refers to a shape as seen in a horizontal direction when a plate-like member or a layer is sectioned in a specific direction.
The term “semiconductor element and the like” refers to elements including semiconductor elements, electronic parts with substantially the same size as the semiconductor elements, and wiring boards.
The release layer may be, for example, a resin which becomes peelable due to heat generation as a result of absorbing light such as UV light or due to alteration, or a resin which becomes peelable due to foaming as a result of being heated. If a resin is used that becomes peelable due to light such as UV light, e.g., laser light, the support 1 can be removed from the joined body of the substrate 11 with a support and the FC-BGA substrate 12 by applying light, as shown in
The release layer can be selected, for example, from organic resins such as epoxy resins, polyimide resins, polyurethane resins, silicone resins, polyester resins, oxetane resins, maleimide resins, and acrylic resins, or from inorganic layers such as an amorphous silicon layer, a gallium nitride layer, and metal oxide layers. The material of the release layer 2 may contain additives such as photolysis accelerants, light absorbers, sensitizers, and fillers.
The release layer may be formed of a plurality of layers. For example, a protective layer may be further provided on the release layer for the purpose of protecting the fine wiring layer formed of multiple layers (second wiring board) formed on the support, or a layer enhancing adhesion to the support may be provided as an underlayer of the release layer. Furthermore, a laser light reflective layer or a metal layer may be provided between the release layer and the fine wiring layer formed of multiple layers which is formed on the release layer, and thus the structure should not be limited by the present embodiment.
The support is preferred to have transparency, e.g., may be made of glass, because the release layer may be irradiated with light via the support. Glass has good flatness and high rigidity, and thus is suitable for forming a fine pattern for substrates with a support. In addition, glass has a low coefficient of thermal expansion (CTE) and is resistant to strain, and thus is excellent in securing pattern placement accuracy and flatness.
If glass is used as a support, the thickness of the glass is preferred to be large, e.g., 0.7 mm or more, and more preferred to be 1.1 mm or more, from the perspective of suppressing occurrence of warpage in the production process. Furthermore, the CTE of the glass is preferred to be 3 ppm/K or more and 15 ppm/K or less, and is more preferred to be around 9 ppm/K from the perspective of the CTEs of the FC-BGA substrate 12 and the semiconductor elements 15. Examples of the glass include quartz glass, borosilicate glass, non-alkali glass, soda glass, and sapphire glass.
However, if the support is not required to have light transmission properties when releasing the support, such as the case where a resin that foams due to heat is used as the release layer, the support can be made of metal or ceramics, for example, inducing less strain.
In the embodiments of the present disclosure provided below, a resin that becomes peelable due to absorption of UV light is used as the release layer, and glass is used as the support.
Referring to
The support 51 is mainly formed of glass, and the wiring board 52 is configured using an organic insulating resin. The wiring board 52, semiconductor element and the like 55, and other wiring board 61 are illustrated in
The substrate 54 with a support shown in
The upper surface 56 of the wiring board 52 is provided with solder 58 for establishing an electrical connection with the semiconductor element and the like 55. The semiconductor element and the like 55 shown in
Referring to
First, the substrate with a support to which the semiconductor element and the like 55 are fixed with the molding resin 60 as shown in
Next, as shown in
As shown in
Next, as shown in
Although
With the configuration and the production processes described above, semiconductor elements with progressively narrower pitches can be mounted on other wiring board such as an FC-BGA substrate.
The above example has described that semiconductor elements are mounted on the substrate 54 with a support, and this is then connected to the other wiring board 61 such as an FC-BGA substrate.
However, the substrate 54 with a support, with the support 51 peeled off, may be connected to the other wiring board 61 such as an FC-BGA substrate before mounting semiconductor elements thereon, and then a semiconductor element and the like may be mounted thereon.
Next, referring to
The substrate 54 with a support includes a wiring board 52 on a support 51 that is a glass substrate and is provided with a release layer 53 between the support 51 and the wiring board 52.
Inside the wiring board 52, wiring 64 is formed over multiple layers using a damascene method. The wiring 64 includes wiring portions and vias for connecting between the wiring portions in the Z direction, which are formed in the X-Y plane. (Formation of multilayer wiring using a damascene method will be described later.)
In the wiring board 52, reinforcement layers 68 as surface layer insulating films, and inner insulating films 67 are firmed.
The inner insulating films are formed of a first organic insulating resin, and the reinforcement layers are formed of a second organic insulating resin. The CTE of the second organic insulating resin is set to be lower than that of the first organic insulating resin. The CTE of the second organic insulating resin is preferred to be 40 ppm/K or lower. The second organic insulating film can contain fillers which can contain silicon or silicon compounds.
The wiring or the vias to connect wiring portions in the wiring board are made of copper or an alloy containing copper. Portions of the surfaces of these materials contacting the first or second organic insulating resin can be provided with respective portions of a barrier metal layer. The barrier metal layer can contain titanium or tantalum or compounds thereof.
In
Next, referring to
The second embodiment is different from the first embodiment in that the intermediate layer 50 is provided between the release layer 53 and the reinforcement layer 68. In the following description, identical reference signs are given to components that are the same as or equivalent to those in the first embodiment to simplify or omit repeated description.
In the second embodiment, the intermediate layer 50 is provided between the release layer 53 and the reinforcement layer 68 shown in each of
In the second embodiment of the present disclosure, a titanium layer and then a copper layer are sequentially formed as the intermediate layer 50 by sputtering, from the perspective of electrical characteristics, ease of production, and cost. If the intermediate layer 50 is also used as an electrolytic plating power supply layer, the total thickness of the titanium layer and the copper layer is preferred to be 1 μm or less. In an embodiment of the present disclosure, Ti: 50 nm and Cu: 300 nm are formed.
Provision of such an intermediate layer 50 can improve adhesion between the release layer 53 and the reinforcement layer 68 and can prevent the support 51 from being easily peeled off.
Furthermore, the intermediate layer 50 plays a role of preventing mixing of the release layer 53 with the reinforcement layer 68 formed of a photosensitive insulating resin film, so that peeling can be reliably achieved between the release layer 53 and the intermediate layer 50.
Insulating films forming a wiring board 52 based on the conventional art have been made of materials of substantially the same quality, and for generally used insulating films, photosensitive insulating resins have been used due to ease of patterning. Such photosensitive resins had CTEs in the range of around 50 to 80 ppm/K.
However, if a wiring board 52 is joined as part of the semiconductor device, the outer periphery thereof is covered, in many cases, with a filler-containing resin layer such as a solder resist or underfill. In this case, due to the difference in clastic modulus depending on the presence or absence of a filler, or due to the difference in deformation due to the difference in CTE, there has been a risk of causing warpage, peeling, or cracking in the wiring board 52 under temperature-changing conditions.
In order to match the physical property values, such as CTE, of the wiring board 52 with those of the material of the outer periphery, it may be considered that a filler-containing insulating resin may also be used for the photosensitive resin used for the wiring board 52. However, if a filler is contained in the insulating resin of the wiring board 52 in which fine wiring is to be formed, required miniaturization is not necessarily achieved because film thickness reduction or miniaturization is limited by the size of the filler. Also, if the production processes of such wiring boards include chemical-mechanical polishing (CMP), and if the filler-containing insulating films are polished in this process, part of the fillers may be polished and exposed and, if the fillers become detached, the wiring boards may be no longer flat and formation of fine wiring may become difficult. Therefore, filler-containing resins could not be necessarily used for all the insulating resins of the wiring board 52, in which fine wiring is to be formed.
In this regard, in the first and second embodiments of the present disclosure, difference in physical properties is changed stepwise in the wiring board 52 from the surface layers toward the inner layers, so that the physical property values can match between the wiring board 52 and the materials of the outer periphery. Specifically, for the surface layers, materials with physical property values close to those of the material of the outer periphery are selected and, for the inner layers of the wiring board 52, materials with usual physical property values are used, so that the physical property values, such as CTE, match between the wiring board 52 as a whole and the material of the outer periphery to thereby suppress occurrence of cracking.
In other words, the CTE of the second organic insulating resin that is the material of the reinforcement layers 68 of the wiring board 52 is made lower than that of the first organic insulating resin that is the material of the inner insulating films 67 of the wiring board 52. Thus, occurrence of cracking or delamination can be suppressed on the inside of the wiring board 52.
Various methods can be used as a method of lowering the CTE of insulating resins, among which, for example, incorporating fillers into insulating resins is relatively easy. If fillers are mixed in insulating resins, no significant problem may arise as long as the insulating resins mixed with fillers are located at portions such as in the reinforcement layers 68 where electrodes are mainly formed and fine wiring is not required to be formed.
Next, referring to
The third embodiment is different from the first and second embodiments in that the wiring board 52 is produced using a known semi-additive method (SAP method). In the following description, identical reference signs are given to components that are the same as or equivalent to those in the first embodiment to simplify or omit repeated description.
In the third embodiment also, there is no significant difference in the effects, such as crack resistance, although the method of forming wiring is different from the damascene method. This will be described later when describing examples.
In
Next, referring to
The fourth embodiment is different from the second and third embodiments in that the reinforcement layer 68 covers only part of the upper surface of the wiring board 52, and the first insulating resin of the inner insulating films 67 is exposed in the portions not covered. This can also be implemented in the first embodiment.
Also, as shown in
If filler-containing reinforcement layers 68 are used, and if the filler has a large particle size in particular, the filler may inhibit formation of fine wiring when performing resist patterning in a damascene method, for example. In a SAP method, the filler may inhibit filling of gaps between the insulating resins, for example, and sufficient covering cannot be necessarily achieved.
These may occur in particular in portions where the solder 58 is formed to serve as fine electrodes for mounting the semiconductor element and the like 55. Therefore, a method of not providing covering of the reinforcement layer 68 can be taken, centering on the regions where electrodes of the solder 58 are arranged to mount the semiconductor element and the like 55.
If some kind of patterning is performed in the regions where no filler-containing reinforcement layer 68 is used, the patterning may be performed in a photosensitive resin. In this case, there is an advantage that the patterning precision is improved compared to patterning in the filler-containing reinforcement layer 68.
To cope with deterioration in strength due to not using a filler-containing reinforcement layer 68, the semiconductor element and the like 55 may be mounted in a later process, following which, portions not covered by the reinforcement layer 68 may be filled with the underfill 59 for fixture of these elements as shown in
Next, referring to
As shown in
Next, in the production method of the first embodiment, a filler-containing second organic insulating resin is applied onto the release layer 53 to provide a reinforcement layer serving as the reinforcement layer 68. The second organic insulating resin can be a filler-containing resin, regardless of whether the resin is photosensitive or non-photosensitive. Examples of the filler-containing resin may include insulating resins such as photosensitive epoxy or acrylic resins, and insulating resins such as non-photosensitive epoxy resins. The method of forming a reinforcement layer in the case of using a liquid photosensitive resin can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. In the case of using a film-like photosensitive resin, lamination, vacuum lamination, vacuum pressing, or the like can be applied.
In the case of the second embodiment, a release layer 53 may be formed, following which an intermediate layer 50 may be formed to improve adhesion between the release layer 53 and a reinforcement layer, and prevent mixing. The material for the intermediate layer 50 can be selected, for example, from nickel, copper, titanium, alloys of these, and multilayers in which two or more of these are used. With these materials, a method selected from plating, vapor deposition, and the like, can be used, but is not limited to this. In the case of providing an intermediate layer 50, the reinforcement layer 68 is formed on the intermediate layer 50.
In this way, using an insulating resin as a reinforcement layer in the wiring board 52, good processability can be achieved, and the entire surface of the substrate excepting the electrical connection portions, such as electrodes, can be covered by the reinforcement layer without any gaps. Thus, the reinforcement layer can effectively suppress occurrence of strain stress in the substrate.
Next, as shown in
Next, a barrier metal layer 63 is formed on the patterned second organic insulating resin. The barrier metal layer 63 can be formed of titanium or copper, or multiple layers of these.
Then, after sputtering copper for serving as a seed layer on the barrier metal layer 63, wiring 64 is formed using electrolytic copper plating. The method of forming wiring is not limited to this, but various known methods may be used.
Next, as shown in
Next, as shown in
The method of forming a photosensitive resin in the case of using a liquid photosensitive resin, similarly to a filler-containing organic insulating resin, can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.
In the case of using a film-like photosensitive resin, the method can be selected from lamination, vacuum lamination, vacuum pressing, and the like. For the photosensitive organic insulating resin, for example, a photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin, or modified products thereof can be used as an insulating resin.
In the subsequent processes, processes described referring to
The multilayer wiring described above has been formed using a damascene method; however, the method is not limited to this, but a SAP method may be used for the formation.
The production method described below is a method in the case where the second insulating resin does not cover part of the wiring board, i.e., in the case where part of the reinforcement layer 68 is open, not covering the entirety.
For example, as shown in
In the case of a SAP method, after applying a reinforcement layer 68, unnecessary portions of the reinforcement layer 68 may be removed.
It should be noted that
The example shown in
The method shown in
Another example of the production method will be described below, in which part of the reinforcement layer 68 is opened to provide a structure not completely covered by the reinforcement layer 68.
In this method, a semiconductor element and the like 55 are mounted prior to forming a reinforcement layer 68 which is an outermost layer of the wiring board 52, and then the underfill 59 is filled in. After this, a reinforcement layer 68 may be applied using, for example, spin coating or die coating, followed by removing portions of the reinforcement layer 68 from portions serving as the semiconductor element and the like 55 or electrodes, using photolithography. In this case, as shown in
Although not shown, a semiconductor element and the like may also be mounted on the lower surface of the wiring board 52 after peeling off the support 51, and the surfaces of the semiconductor element and the like may be covered by a reinforcement layer 68 using similar processing.
Next, as shown in
Copper post electrodes may be formed on the respective electrodes exposed on the first surface of the substrate 54 with a support, and solder may be deposited on them. Soldering can be performed using a known method, such as a method of printing a solder paste or a method of depositing tin by plating. (Formation of copper post electrodes will be described later.)
Without forming solder electrodes on the respective electrodes exposed on the first surface of the substrate 54 with a support, copper electrodes may be finished with only undergoing surface treatment. Surface treatments such as nickel-gold plating and OSP treatment, for example, can be used.
Next, referring to
First, as shown in
Next, as shown in
Next, as shown in
Next, referring to
When producing copper posts on the second surface 72 of the wiring board 52, a pattern of copper posts is formed first, as shown in
The substrate 54 with a support or the wiring board 52 completed as described above can be provided with semiconductor elements using the method described referring to
Referring to
First, as shown in
Next, referring to
The reinforcement layer is preferred to have a CTE which is lower than that of the resins used for photosensitive resin layers or insulating layers in the second wiring board including fine wiring layers.
Next, connection holes are formed in the reinforcement layer 18 to provide electrodes for establishing an electrical connection with semiconductor elements 15. In order to form the connection holes, the reinforcement layer 18 is patterned as shown in
Next, as shown in
Similarly to the reinforcement layer 18, the method of forming a photosensitive resin in the case of using a liquid photosensitive resin can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. In the case of using a film-like photosensitive resin, lamination, vacuum lamination, vacuum pressing, or the like can be applied.
For the photosensitive resin layer 3, for example, a photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin, or modified products thereof can be used as an insulating resin.
As a result of studying photosensitive resins and insulating resins suitable for forming fine wiring, it was found that the range of CTE at which fine wiring can be formed was around 50 to 80 ppm/K.
Next, as shown in
Next, referring to
In the first mode of forming connection holes in a fine wiring layer, as described referring to
However, in the second mode of forming a connection hole in a fine wiring layer, the reinforcement layer 18 formed on the support 1 or the release layer 2 does not necessarily cover substantially the entire surface excepting the regions where the openings of the photosensitive resin layer 3 are formed. In other words, not all the openings formed in the photosensitive resin layer 3 have to match the openings formed in the reinforcement layer 18, but part of the openings formed in the photosensitive resin layer may reach the release layer 2 without them passing through the reinforcement layer 18.
The second mode of forming connection holes in a fine wiring layer will be described in detail.
First,
Next, referring to
Next, referring to
According to the second mode of forming connection holes in a fine wiring layer, connection holes formed in the photosensitive resin layer 3 are open only in the photosensitive resin layer 3, as shown in
Next, referring to
In the case of this formation also, connection holes are formed depending on the patterning accuracy of the photosensitive resin layer 3, and therefore, can be beneficially formed with ease with a minute opening diameter, compared to connection holes formed passing through the reinforcement layer 18.
Next, referring to
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
As shown in
Next, as shown in
Next, as shown in
Next, as shown in
As shown in
In an embodiment of the present invention, two wiring layers are formed. Although a damascene method is used in the multilayer wiring formation shown in
Next, referring to
Next, as shown in
Next, as shown in
After that, as shown in
Next, as shown in
Next, as shown in
Next, referring to
First, as shown in
Then, as shown in
After that, semiconductor elements 15 are mounted, as shown in
Next, referring to
The sixth embodiment is different from the first embodiment in that an intermediate layer 50 is provided between the release layer 2 and the reinforcement layer 18. In the following description, identical reference signs are given to components that are the same as or equivalent to those in the fifth embodiment to simplify or omit repeated description.
In the sixth embodiment, as shown in
The specific method or materials described referring to
Provision of such an intermediate layer 50 can improve adhesion between the release layer 2 and the reinforcement layer 18 which will be formed in a later process.
Next, referring to
Next, referring to
In the sixth embodiment also, after patterning the reinforcement layer 18, a substrate with a support shown in
After this, the support 1 is peeled from the substrate with a support shown in
After removing the support 1, the seed adhesion layer 4 and the seed layer 5 configuring the intermediate layer 50 can be etched away.
Next, the semiconductor device of the first embodiment shown in
In each of evaluation examples and comparative examples, a conductor pattern of width 1,000 μm was formed as an outermost layer (as indicated by X in
Herein, the thickness of each reinforcement layer was as indicated by Z in
In each of the comparative examples, an organic insulating resin containing no filler was used as the first organic insulating resin in the insulating film of the surface layer.
For the configurations with Evaluation Conditions 1 to 5 and the comparative examples, via connection reliability testing was conducted. The via connection reliability testing was conducted according to the following conditions. The criteria for passing were the rate of change in resistance being ±3%, and cracking and delamination not occurring.
Before failing in the via connection reliability testing, the configurations with Evaluation Conditions 1 to 17 could undergo 1,000 to 2,000 testing cycles, but the comparative examples could undergo only 300 to 500 testing cycles. By forming the filler-containing organic insulating resin layers of the present invention on top and bottom of the fine wiring layer, stress inside the wiring layer could be relieved, and cracking originating from areas where stress was concentrated became less likely to occur, effectively exerting via connection reliability.
Since the CTE of the photosensitive insulating resin in which fine wiring could be formed was in the range of around 50 to 80 ppm/K, it can be said that the reinforcement layers could exert effects with a CTE of around 40 ppm/K lower than that of the photosensitive insulating resin.
It is considered that, since the volume of the reinforcement layers with a CTE lower than that of the photosensitive insulating resin increases by increasing the thickness of the reinforcement layer to 45 μm or greater, stress strain can be further reduced in the insulating resin and crack resistance can be further improved. It is also considered that, although the effects are reduced by reducing the thickness of the reinforcement layers to less than 45 μm, crack resistance can still be improved compared to the comparative examples with no reinforcement layers.
Since the results of Evaluation Condition 5 were equivalent to those of other evaluation conditions, it can be said that there is no great difference in crack resistance between the wiring formed using a damascene method and the wiring formed using a SAP method, although these methods are different from each other.
Furthermore, the results of the evaluation conditions with the reinforcement layers provided on both respective surfaces were equivalent to those of the evaluation conditions with the reinforcement layer provided on only one surface, and therefore, it can be said that there is no great difference in crack resistance whether the reinforcement layer was provided on each of both surfaces or on only one surface.
Next, the effects of using the configuration of the wiring board unit 14 of the fifth embodiment shown in
As comparative examples, wiring layers in which no reinforcement layers 18 were formed in the processes shown in
In each of evaluation examples and comparative examples, a conductor pattern of width 1,000 μm was formed as an outermost layer so that cracking would easily occur in the fine wiring layer 19 of the wiring board unit 14 to examine cracking improvement effects of the reinforcement layers 18.
Comparative examples were prepared under conditions similar to Evaluation Conditions 1 to 4 except that no reinforcement layers 18 were formed as outermost layers of the fine wiring layer 19 of the wiring board unit 14. The method used for forming the fine wiring layers was a damascene method.
For the configurations with Evaluation Condition 1 to the comparative examples, via connection reliability testing was conducted.
The via connection reliability testing was conducted according to the following conditions. The criteria for passing were the rate of change in resistance being ±3%, and cracking and delamination not occurring.
Before failing in the via connection reliability testing, the configurations with Evaluation Conditions 1 to 17 could undergo 1,000 to 2,000 testing cycles, but the comparative examples could undergo only 300 to 500 testing cycles. By forming the reinforcement layers 18 of the present invention as outermost layers of the fine wiring layer 19 of the wiring board unit 14, stress inside the wiring layer could be relieved, and cracking originating from areas where stress was concentrated became less likely to occur, which had an effect on via connection reliability.
Since the CTE of the photosensitive insulating resin in which fine wiring could be formed was in the range of around 50 to 80 ppm/K, it can be said that the reinforcement layers could exert effects with a CTE of around 40 ppm/K lower than that of the photosensitive insulating resin.
It is considered that, since the volume of the reinforcement layers with a CTE lower than that of the photosensitive insulating resin increases by increasing the thickness of the reinforcement layer to 45 μm or greater, stress strain can be further reduced in the insulating resin and crack resistance can be further improved. It is also considered that, although the effects are reduced by reducing the thickness of the reinforcement layers to less than 45 μm, crack resistance can still be improved compared to the comparative examples with no reinforcement layers.
In other words, in the present embodiment, the second wiring board configured using high-CTE materials is sandwiched between a high-CTE outermost layer and a high-CTE first wiring board to reduce stress strain inside the second wiring board. Therefore, cracking due to stress concentration, which tends to occur in a second wiring board having a fine wiring layer, can be prevented, and reliability of the wiring board unit can be improved.
Since the results of Evaluation Condition 5 were equivalent to those of other evaluation conditions, it can be said that there is no great difference in crack resistance between the wiring formed using a damascene method and the wiring formed using a SAP method, although these methods are different from each other.
The above embodiments are mere examples, and specific details may be modified as appropriate as a matter of course.
For example, although the reinforcement layers were formed only as outermost layers in the above examples, the effects of the reinforcement layers are not limited to be exerted by being present only as outermost layers. In other words, the reinforcement layers can each be formed adjacent to or close to an outermost layer.
In the above examples, the material of the reinforcement layers was a filler-containing resin; however, the material of the reinforcement layers is not limited to this. Various materials can be used for the reinforcement layers as long as the materials have a CTE of 40 ppm/K or lower.
Although a damascene method or a SAP method is used in the present disclosure, methods are not limited to these, but may be changed to other methods.
The present invention can be applied to various semiconductor devices including a wiring board which is provided with an interposer or the like provided between a main substrate and chips.
The semiconductor elements of the present disclosure can be replaced by other wiring board.
The present disclosure also encompasses the following modes.
A substrate with a support, the substrate including a support and a wiring board provided on the support, wherein
The substrate with a support, according to Mode 1, wherein
The substrate with a support, according to Mode 1 or 2, wherein
The substrate with a support, according to Mode 3, wherein
The substrate with a support, according to any one of Modes 1 to 4, wherein
The substrate with a support, according to any one of Modes 1 to 5, wherein
The substrate with a support, according to Mode 6, wherein
The substrate with a support, according to any one of Modes 1 to 7, wherein
The substrate with a support, according to any one of Modes 1 to 8, wherein
The substrate with a support, according to Mode 9, wherein
The substrate with a support, according to any one of Modes 1 to 10, wherein
A semiconductor device, wherein
The semiconductor device according to Mode 12, wherein
A method of producing a substrate with a support, according to Mode 11, including
The method of forming a substrate with a support, according to Mode 14, including
A method of producing a semiconductor device, including
A method of producing a semiconductor device, including
The method of producing a semiconductor device according to Modes 14 to 17, including
The present disclosure further encompasses the following modes.
A wiring board unit including
The wiring board unit according to Mode 19, wherein
The wiring board unit according to Mode 19 or 20, wherein
The wiring board unit according to any one of Modes 19 to 21, wherein
The wiring board unit according to any one of Modes 19 to 22, wherein
The wiring board unit according to any one of Modes 19 to 23, wherein
The wiring board unit according to any one of Modes 19 to 24, wherein
The wiring board unit according to Mode 25, wherein
The wiring board unit according to any one of Modes 19 to 26, wherein
A substrate with a support, the substrate including a second wiring board, a release layer, and a support, wherein
The substrate with a support, according to Mode 28, wherein
The wiring board unit or the substrate with a support, according to Modes 19 to 29, wherein
A method of producing a wiring board unit according to Modes 19 to 29, including
A method of producing a wiring board unit according to Mode 19 or 20, including a first step of forming a release layer on a support;
The method of producing a wiring board unit according to Mode 30 or 31, wherein a lithography technique is used in the step of forming a pattern in the reinforcement layer.
The method of producing a wiring board unit according to Mode 30 or 31, wherein a laser processing technique is used in the step of forming a pattern in the reinforcement layer.
[Reference Signs List] 1, 51: Support; 2, 53: Release layer; 3: Photosensitive resin layer; 4: Seed adhesion layer; 5: Seed layer; 6: Conductor layer; 7: Resist pattern; 8: Solder resist layer; 9: Surface treatment layer; 10, 58: Solder; 11, 54: Substrate with a support; 12: FC-BGA substrate; 13: Laser light; 14: Wiring board unit; 15: Semiconductor element; 16: Semiconductor device; 18, 68: Reinforcement layer; 19: Fine wiring layer; 20: Underfill layer; 50: Intermediate layer; 52: Wiring board; 55: Semiconductor element and the like; 56: Upper surface of wiring board 52; 57: Lower surface of wiring board 52; 59: Underfill; 60: Molding resin,; 61: Other wiring board; 62: Solder or copper post; 63: Barrier metal layer; 64: Wiring; 67: Inner insulating film; 69: Plating resist; 70: Copper plating; 71: First surface; 72: Second surface.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-153732 | Sep 2021 | JP | national |
| 2021-153750 | Sep 2021 | JP | national |
| 2022-108781 | Jul 2022 | JP | national |
| 2022-108783 | Jul 2022 | JP | national |
| 2022-139742 | Sep 2022 | JP | national |
| 2022-139745 | Sep 2022 | JP | national |
This application is a continuation application filed under 35 U.S.C. § 111(a) claiming the benefit under 35 U.S.C. §§ 120 and 365(c) of International Patent Application No. PCT/JP2022/033435, filed on Sep. 6, 2022, which is based upon and claims the benefit to Japanese Patent Application Nos. 2021-153732, and 2021-153750, both filed on Sep. 22, 2021; Japanese Patent Application Nos. 2022-108781, and 2022-108783, both filed on Jul. 6, 2022; and Japanese Patent Application Nos. 2022-139742, and 2021-139745, both filed on Sep. 2, 2022, the disclosures of which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2022/033435 | Sep 2022 | WO |
| Child | 18611641 | US |
