Patent Application
20250201669
The subject matter disclosed herein relates to microelectronics packaging and integrated circuits (IC) packaging. More particularly, the subject matter disclosed herein relates to a package architecture incorporating liquid cooling.
Semiconductor devices may connect to additional devices and circuitry on different substrates. Forming connections between substrates can provide increased computation. However, forming connections between substrates can cause complications. Packaging describes the general method for connecting and integrating multiple computational components together in an integrated unit, and may involve multiple different types of integrated circuits on multiple substrates which may combine into a single unit. Packaging may also describe the method for which multiple computational components within a single unit are protected by the use of various techniques to provide thermal, physical and electrical protection. It is further noted that background concepts discussed herein are for informational purposes only and are not intended to limit the present disclosure. Nor should the background or field described herein be intended to limit the disclosure herein to a particular use or concept
An example embodiment provides a device including a first layer with at least one transistor, a second layer on a first side of the first layer, the second layer including a signal layer, a third layer on a second side of the first layer, the second side opposite the first side. The third layer may include a backside power delivery device. A liquid heat exchanger may be connected to the signal layer, and the first layer, the second layer, the third layer and the liquid heat exchanger may be stacked. The liquid heat exchanger may include a first cooling layer, a second cooling layer connected to the first cooling layer, and a third cooling layer connected to the second cooling layer, the second cooling layer between the first cooling layer and the third cooling layer. The liquid heat exchanger may include an inlet contacting the second cooling layer and an outlet contacting the first cooling layer. The third cooling layer may include a first set of fins supporting cooling liquid flowing in a first direction and a second set of fins supporting cooling liquid flowing in a second direction, the second direction opposite the first direction. The third cooling layer may include a first outlet contacting a first set of fins and a second outlet contacting a second set of fins, and a shared inlet contacting the second cooling layer, the first set of fins, and the second set of fins. A first outlet may contact the first cooling layer and a second outlet may contact the first cooling layer. The liquid heat exchanger may include a fluid flow path connecting an inlet to the second cooling layer, the second cooling layer to a shared inlet, the shared inlet to a first set of fins, the first set of fins to a first outlet, the first outlet to the first layer, and the first layer to an outlet. The liquid heat exchanger may be formed of silicon. The liquid heat exchanger may contact the signal layer.
An example embodiment provides a system including a liquid heat exchanger, a first substrate with a first side, and a second side opposite the first side; a first cooling layer on the first side, the first cooling layer including a first set of fluidic conduits, an outlet connected to the first cooling layer, and a second cooling layer between the first cooling layer and the first substrate, the second cooling layer including a second set of fluidic conduits coupled to the first set of fluidic conduits; and an inlet connected to the second cooling layer. A third cooling layer may between the second cooling layer and the first substrate, the third cooling connected to the second cooling layer. The third cooling layer may include a first set of fins flowing in a first direction and a second set of fins flowing in a second direction opposite the first direction, and a base die may connect to the liquid heat exchanger. The liquid heat exchanger may be formed from silicon. An inlet may between the first set of fins and the second set of fins, with the inlet connecting the first set of fins and the second set of fins to the second set of fluidic conduits. A first outlet may connect to the first set of fins and a second outlet may connect to the second set of fins. The first outlet may connect the first set of fins to the second set of fluidic conduits, and the second outlet may connect the second set of fins to the second set of fluidic conduits. The first set of fins may include a first set of channels and the second set of fins may include a second set of channels. The base die may include a signal layer, a transistor layer, and a backside power delivery device.
An example embodiment may provide a method including forming a transistor layer with at least one transistor on a first side of a first substrate, forming a signal layer on the transistor layer, the transistor layer communicatively coupled to the transistor layer, forming a backside power delivery layer on a second side of the first substrate, the second side opposite the first side, the backside power delivery layer electrically coupled to the transistor layer. A liquid heat exchanger may be bonded to the signal layer, and the backside power delivery layer may be attached to a second substrate. The liquid heat exchanger may be bonded to the signal layer using a fusion bonding process. Bonding the liquid heat exchanger to the signal layer may include bonding a top manifold layer to a middle layer, the middle layer including a set of channels, and bonding the middle layer to a liquid carrier wafer. The liquid carrier wafer may include at least one fin. The set of channels of the middle layer may be aligned to at least one fin of the liquid carrier wafer.
In the following section, the aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the figures, in which:
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined,” etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined, etc.), and a capitalized entry (e.g., “Counter Clockwise,” “Row Select,” “3D,” etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., “counter clockwise,” “row select,” “3d,” etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.
Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element or layer is referred to as being on, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein substrates may refer to a variety of materials and structures, including wafers using silicon, wafers using silicon on an insulator (SOI) such as glass, wafers of other semiconductor materials such as germanium, as well as other semiconductor materials on an insulator. In some embodiments, a substrate may include an organic material. In some embodiments, the substrates may be referred to as wafers, dies, and chips alone or in combination. Bonding substrates may be thus known in some embodiments as die-to-die (D2D) bonding, wafer-to-wafer bonding (W2 W) or die-to-wafer bonding (D2 W). In some embodiments, the substrates may contain circuits such as integrated circuits including central processing units (CPUs), logic chips, memory such as static random-access memory (SRAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), double data rate DRAM or DDR DRAM, application processors (AP), graphical processing units (GPUs), other forms of auxiliary processing units (xPU), Artificial intelligence (AI) chips, High bandwidth memory (HBM) interfaces, and other application-specific integrated circuits (ASIC). In some embodiments, a combination of circuits may be present on a substrate. In some embodiments, a substrate may include a packaged chip.
As used herein, high bandwidth memory or HBM, may refer to a chip structure including one or more HBM modules. In some embodiments, the HBM may be manufactured by an advanced silicon node process.
As used herein packaging refers to a process of forming interconnections between substrates. In some embodiments, the interconnections may be between direct surfaces and involve W2 W, D2D, and D2 W bonding. In other embodiments, techniques including wire bonding and other forms of indirect bonding may be performed alone or in combination with W2 W, D2D, and D2 W bonding. In some embodiments, circuits may be bonded directly facing each other, while in other embodiments a flip-chip bonding may be used. In some embodiments, interconnections may be made between substrates on a front or circuit side of the substrate. In other embodiments, interconnections may be made on a rear or back side of the substrate opposite from the circuit structure. In some embodiments, an interconnection may include through-silicon vias (TSVs) or other forms of through-chip vias where one or more substrates may be connected using a via extending through an interposer such as another substrate or chip. In some embodiments, an interconnection may be formed using connections on a surface of a substrate, such as a pad, and may use additional materials between the pads such as solder to form an interconnection.
As used herein, conductors may refer to a variety of conductive materials, including which materials may be used alone or in combination with other materials such as in the form of an alloy. In some embodiments the conductor is copper (Cu). In some embodiments, copper (Cu) may be in the form of Cu (II), Cu (III) or other forms of copper, alone or in combination with additional elements, including cobalt (Co) and ruthenium (Ru). Such a listing of elements is not intended to be exhaustive, and in other embodiments, any known other type of conductive material may be used.
As used herein, the term fluidically coupled, fluidically connected, fluid path, fluidic flow path, and fluid flow path may refer to a route or path a fluid may travel, and may include one or more intermediate steps between two objects said to be fluidically coupled.
As discussed herein, a structure may be formed using power delivery networks and signal networks in a modular structure with additional computational components such as memory and processing devices. Such a modular structure may create an increase in circuitry density, which may, however increase the thermal energy which may be generated or trapped within a such a modular structure. As such, disclosed herein are various embodiments herein are various embodiments of devices, systems and methods related to packaging architecture to combine backside power delivery networks (BSPDNs), signal networks, and embedded liquid cooling. In some embodiments, a BSPDN may be formed on the backside of a substrate, with a signal network formed on the front side of the same substrate. In some embodiments, the BSPDN and signal network may be formed on separate substrates and transferred to the same substrate. The BSPDN and signal network may be separated by a transistor layer. The transistor layer may include a plurality of transistors. The transistors may provide different functions and take different forms, including a logic layer. The BSPDN and signal network may form a single monolithic structure on the same die in a semiconductor foundry process, which may be known as a base chip. A liquid cooling module may be separately formed in a semiconductor manufacturing process, and assembled in a packaging assembly process. In some embodiments, a signal network may be referred to a signal network layer or signal layer. In some embodiments, a backside power delivery network or BSPDN may be referred to as a backside power delivery device, a backside power delivery layer, or a backside power delivery network layer.
The liquid cooling module 102 may form the top of the stack formation of the cooling package architecture 100, although in another embodiment the stack may be inverted with the liquid cooling module 102 forming the bottom of the stack formation. The liquid cooling module 102 may include a plurality of channels 122 for carrying liquid coolant within the liquid cooling module 102. As used herein, a liquid cooling module may be referred to in some embodiments as a liquid heat exchanger, or fluid heat exchanger. The base of the liquid cooling module 102 may be a carrier wafer layer 110, made from a substrate material such as silicon (Si). The liquid coolant carried within the liquid cooling module 102 can be provided as one or more of a number of coolants, which may be liquid at or near room temperature (e.g., water, alcohols, glycols, etc., or various combinations thereof). The liquid coolant may enter the liquid cooling module 102 via an inlet 124 and exit the liquid cooling module 102 via an outlet 126. As further discussed below with reference to
The base chip 104 is bonded to the carrier wafer layer 110 of liquid cooling module 102 by a bonding layer 112. The carrier wafer layer 110 holds the liquid cooling module 102, and may be made of a substrate material such as silicon. The bonding layer 112 provides a bond between the base chip 104 and the liquid cooling module 102, both securing the liquid cooling module 102 to the base chip 104 and providing thermal transport between the base chip 104 and the liquid cooling module 102. In some embodiments, the bonding layer 112 may be made of a dielectric material such as silicon oxide (SiO2) or silicon nitride (Si3N4). The bonding layer 112 may contact a signal layer 114 of the base chip 104, which may in turn contact a transistor layer 116 of the base chip 104. The signal layer 114 may be a signal network layer. The bonding layer 112 may provide a thermal path for the signal layer 114 to thermally couple the base chip 104 to the liquid cooling module 102.
The signal layer 114 may comprise a network-on-a-chip (NOC), and may provide interconnections to transport signals for other layers, including the transistor layer 116. In some embodiments, the signal layer 114 may provide packet routing. In some embodiments, the signal layer 114 may be provided as a multi-layer structure capable of providing signal routing. In some embodiments, the signal layer 114 may comprise a plurality of conductive channels embedded within a dielectric material, and the plurality of conductive channels may be arranged in multiple layers, with the size of the conductive channels decreasing in distance from the transistor layer 116. In some embodiments, the signal layer 114 may have a plurality of conductive channels in 4, 8, 10, 12 or more layers. In some embodiments, the conductive channels may be conductive lines formed of a material such as a metal, including copper.
The transistor layer 116 separates the signal layer 114 from a power layer 118 of the base chip 104 and includes a plurality of transistors. As used herein, the transistor layer 116 may be used to refer to both the layer containing the plurality transistors and the plurality of transistors. In some embodiments, the transistor layer 116 may act as the base logic for both the signal layer 114 and the power layer 118. In other embodiments, the transistor layer 116 along with the signal layer 114 and the power layer 118 may provide the base logic for a memory device. The transistor layer 116 may be communicatively coupled to the signal layer 114 and may be electrically coupled to the power layer 118.
The power layer 118 provides a power delivery network for routing power supply lines on the back side of the transistor layer 116 and may provide both power and reference voltages to transistors in transistor layer 116. The power layer 118, may be known as well as a backside power delivery network layer or BSPDN layer. The power layer 118 may include multiple different layers of power supply lines 156 routing power within an insulating material. In some embodiments the insulating material may include a dielectric material. In some embodiments, the power layer 118 may include 4 to 6 layers of power supply lines and, in some embodiments, the size of the power supply lines may decrease as they approach the transistor layer 116. The power supply lines may be comprised of conductive materials, including various forms of low resistive metals, such as copper, alternatively or in addition, the conductive materials may include various forms of other conductive materials, including doped carbon.
The power layer 118 may be coupled to the supporting substrate 106 with interconnects 120. In some embodiments, a plurality of pads, plugs and vias may be used to couple the power layer 118 to the supporting substrate 106. The interconnects 120 may include pads, bumps, microbumps, pillars, balls, and other forms such as controlled-collapse chip connection (C4) bumps, alone or in combination. As used herein, a C4 bump refers to a form of solder bumps placed on pads on a top surface of a substrate prior to flipping the substrate to form a flip-chip. The interconnects 120 may further include a dielectric material, which may include a material such as an adhesive, resin, or elastomer which may form a connection between the power layer 118 and the supporting substrate 106 in addition to a conductive connection. In some embodiments, the combination of a conductive connection and a dielectric connection may form a hybrid bond. The supporting substrate 106 may in turn connect to other devices and dies, and in some embodiments, may take the form of an interposer. The supporting substrate 106 may be made of various materials, including organic materials, as well semiconductor materials such as silicon either alone or in combination with another material, such as a semiconductor-on-insulator substrate.
In some embodiments, the inlet 124 may connect directly to both the first cooling layer 210 and the second cooling layer 220, with a section 222 of the inlet 124 extending into the second cooling layer 220. In some embodiments, the outlet 126 may connect to only the first cooling layer 210. A direct connection between the inlet 124 and the second cooling layer 220 may reduce the pressure drop across the liquid cooling module 102 by more efficiently transporting the cooling liquid across the liquid cooling module 102 via the second cooling layer 220 and into the third cooling layer 230.
The third cooling layer 230 may contain the plurality of fins 232 and the corresponding plurality of channels 234. The plurality of fins 232 may be a series of fins extending vertically from the carrier wafer layer 110, the corresponding plurality of channels 234 being formed between the plurality of fins 232. The plurality of fins 232 may be formed into a series of sets of fins, which may be referred to as fin banks, each fin bank extending between a pair of the second set of connections 226.
As shown in the exemplary embodiment of
The plurality of fin banks 320 may be arranged in a set of rows, and in some embodiments may be arranged in a set of columns. In some embodiments, the plurality of fin banks 320 may extend across substantially the entirety of the third cooling layer 230. The plurality of fin banks 320 may be fluidically connected in series in parallel, or a combination thereof. The number of fin banks 320 in the plurality of fin banks 320 in a row may be adjusted based on the size of the liquid cooling module 102. In some embodiments, the number of fin banks in the plurality of fin banks 320 in a row may be at least 2, at least 4, at least 8, or more. In some embodiments, each bank of the plurality of fin banks 320 may extend only a portion of the distance across the third cooling layer 230. By using a plurality of fin banks 320 in each row, the pressure drop across the entirety of the liquid cooling module 102 may be reduced compared to using a single fin bank for each row, as the cooling liquid may more efficiently flow across the plurality of fins 232.
The heat exchanger 610 may be any suitable form of heat exchanger, such as radiators, cooling plates, helical coils, heat pumps, phase change exchangers, evaporators, etc. In some embodiments, the heat exchanger 610 may transfer heat from the cooling liquid to a secondary cooling fluid, such as air or water. In some embodiments, multiple cooling loops may be provided to provide further cooling to the secondary cooling fluid.
The pump 620 may be any suitable pump for transferring a cooling liquid, and may take the form of any suitable pump, including a positive displacement pump, a volumetric pump, a centrifugal pump, an axial-flow pump, or some combination thereof.
As shown in the illustrative embodiment of
In some embodiments, the liquid cooling module 102 may be formed using additive manufacturing processes such as Three-D printing. In some embodiments the liquid cooling module 102 may be printed of materials such as ceramics, while in other embodiments, other known types of fused deposition materials may be used.
While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.
Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.
This application claims the priority benefit under 35 U.S.C. § 119 (e) of U.S. Provisional Patent Application Ser. No. 63/612,356 filed on Dec. 19, 2023, the disclosure of which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63612356 | Dec 2023 | US |
