Patent Application
20190237436
Embodiments of the present invention relate generally to microelectronic packaging, and, more specifically, to multi-chip or system-in-package modules with semiconductor devices in a stacked arrangement.
Packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Integrated circuits are typically fabricated on a semiconductor wafer which may be diced to form a semiconductor die or chip. The die or chip may then be coupled to a substrate to form a package. Some packages may include multiple semiconductor dies coupled to a substrate to form Multi-Chip Module (MCM) devices. Certain MCM packages may include a processor, such that the package forms a mini-system. These self-contained mini-systems are commonly referred to as System-in-Package (SIP). SIP or MCM devices are commonly used in small electronic devices such as cell phones, digital music players, personal organizers, etc. One mechanism for increasing the amount of electrical circuitry in the package, without increasing the surface mount space necessary to house the components, is to stack the chips or dies on top of each other in a vertical fashion. The final step in formation of a SIP is to provide external interconnects to and/or encapsulate the stacked components.
Although the stacked arrangement in SIP and MCM devices minimizes the amount of surface area or “real estate” needed as compared to horizontally oriented packages, the stacked arrangement also introduces new challenges. The reduced surface area limits the horizontal placement of semiconductor dies and chips, and components that might not lend themselves to a stacked arrangement may be forced into a suboptimal location or orientation. Proper location and orientation are typically desirable to insure electrical conductivity between components and to reduce or eliminate any electrical interference. There are increasing difficulties in electrically connecting the various components to the substrate and each other because of the forced locations and orientations of the components due to the reduced surface area. For example, such components commonly use bond pads, in which the bond pads of one component are connected to a substrate or another component through the use of bond wires. The connectivity of the bond pads is limited by the space available on the mounting surface, and the bond pads of one component may not overlie the bond pads of another component or the contact pads of a substrate.
Other types of electronic connecting techniques, such as Fine-Pitch Ball Grid Array (FPGA) or Ball Grid Array (BGA) technology, may suffer similar problems. BGA packages implement conductive metal, such as solder, which is formed into spheres or balls and disposed on conductive ball pads on a substrate or other surface. The solder balls are generally configured into an array to provide mechanical as well as electrical interfaces between components and a substrate.
Additional challenges in designing SIP devices include the lack of vertical space between components and placement of components that may not lend themselves to embedding in a vertical stack. For example, vertical integration of components may lead to problems with encapsulating the package with a molding compound, resulting in air pockets and voids that may lead to conductivity gaps. Some components that may be required by the package, such as filter capacitors, may be limited to surface mounting and cannot be embedded elsewhere in the SIP or MCM stack, further complicating the space and connectivity issues.
One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
Turning now to the drawings,
In the embodiment illustrated in
The memory dies 16 and 17 are attached to the substrate 14. The substrate 14 may be formed from a dielectric material, such as a nonconductive polymer, glass, or ceramic, for instance. The memory dies 16 and 17 can be attached to the substrate 14 by epoxy, semiconductor tape, die attach film (DAF), or any desirable adhesive. As will be described below, the memory dies 16 and 17 and substrate 14 may be coupled together in a first sub-assembly before further assembly into the SIP stack 10. To incorporate the memory dies 16 and 17 into the SIP stack 10, each of the memory dies 16 and 17 are electrically coupled to the substrate 14 such that data and command signals can be directed to and from each of the memory dies 16 and 17 and throughout the SIP stack 10. As shown in
According to the embodiments of the present invention, the microcontroller 18 and the capacitors 20 are attached to the interposer 12. The microcontroller 18 and capacitors 20 can be attached to the interposer 12 by epoxy, semiconductor tape, DAF, or any desirable adhesive. In one embodiment, the interposer 12 is formed from bismaleimide triazine (BT), however the interposer may be formed from silicon, ceramic, or any other suitable material. The interposer material may be selected based on cost or manufacturing requirements. A second interposer may also be used, depending on the size of the stack, the number of components, and surface area and signal routing requirements. For example, if additional components, such as another microcontroller, are required in the SIP, placement of the additional components in the vertical SIP stack may produce the same problems described above. Use of a second interposer on top of the first interposer provides the same rerouting and relocation advantages described herein with respect to the first interposer.
The microcontroller 18 has contact pads or bond pads 28 located on the periphery of the chip for electrical connection to other components in the stack. Advantageously, the microcontroller 18 and capacitors 20 may be relocated and reoriented to a preferred area on the stack 10 by employing the interposer 12. Further, the signals from the microcontroller 18 are rerouted to a more optimal bonding area, as the bond pads 28 of the microcontroller 18 are closer to the bond pads of other components and the substrate. As shown in
In one embodiment, the SIP stack 10 may be manufactured by assembly of two individually fabricated, tested, and assembled subassemblies. The first subassembly may include the memory dies 16 and 17 coupled to the substrate 14. The second subassembly may include the microcontroller 18 and the capacitors 20 attached to the interposer 12. Each subassembly may include any number of different components to benefit from the testing and manufacturing advantages described herein. DAF or other desirable adhesive may be applied to a sheet of interposer material prior to cutting into the interposer 12 for use in the second subassembly of the SIP stack 10, as explained below. Advantageously, the two subassemblies may be tested separately before assembly into the SIP stack 10 such that only good subassemblies are coupled together to form the stack 10. As will be appreciated, separate fabrication of the two subassemblies may reduce the unnecessary disposal of good parts and increase the reliability of the SIP stack 10.
Referring now to
Turning now to
In one embodiment, attachment of the interposer 12 to the underlying dies or chips is accomplished by applying DAF to the interposer 12 according to the embodiments of the invention described herein. Before cutting the larger sheet of material from which the interposer 12 is sized and cut for incorporation into the stack, DAF is applied to a sheet of interposer material. Once DAF is applied to the interposer sheet, the interposer 12 is cut into the desired sizes. After cutting, the result of the application of DAF to the sheet of interposer material is a section of interposer cut to the appropriate size but with DAF already applied. Advantageously, in accordance with the present embodiment, after cutting, the interposer 12 is ready to be picked and placed to the desired location.
By testing both the first subassembly 40 and the second subassembly 46 before assembly into the SIP stack 10, any of the components that fail testing can be discarded without wasting the other subassembly of the stack. As more semiconductor dies and chips are added into a SIP stack, the chances of component failure increases and may result in lower yields of assembled SIP's. Testing preassembled subassemblies 40 and 46 before assembly into the SIP can mitigate this problem. Further, to aid in manufacturing, the first subassemblies of the stack, for example a memory subassembly, can be fabricated as a base “generic” package. Further, the second subassemblies, such as those subassemblies with application-specific microcontrollers, can be preassembled and used with the base generic package depending on the end application.
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
This application is continuation of Ser. No. 14/258,875, filed Apr. 22, 2014 which is a divisional of U.S. patent application Ser. No. 11/786,610, filed Apr. 12, 2007, now U.S. Pat. No. 8,735,183.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11786610 | Apr 2007 | US |
| Child | 14258875 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14258875 | Apr 2014 | US |
| Child | 16378260 | US |
