Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
Data in a solid state storage device decays over time requiring more error correction capability over time. To correct additional errors, enhanced error correction circuitry may be employed. However, such enhanced error correction circuitry may not be able to correct all mis-programming errors occurring in a solid state memory device.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for reducing errors in a solid state storage device.
Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
Various embodiments of the present invention provide methods for writing data to a solid state memory device. The methods include: programming a multi-bit cell of a memory device with a first value selected based upon a first bit value; reading the cell of the memory device using a currently modified reference value to yield a read data; programming the multi-bit cell of the memory device with a second value selected based upon a combination of a second bit value and the read data; and generating the currently modified reference value such that it yields a reduced bit error rate of the read data compared with a previous modified reference value.
This summary provides only a general outline of some embodiments of the invention. The phrases “in one embodiment,” “according to one embodiment,” “in various embodiments”, “in one or more embodiments”, “in particular embodiments” and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present invention, and may be included in more than one embodiment of the present invention. Importantly, such phases do not necessarily refer to the same embodiment. Many other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.
A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.
Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
Various embodiments of the present invention provide methods for writing data to a solid state memory device. The methods include: programming a multi-bit cell of a memory device with a first value selected based upon a first bit value; reading the cell of the memory device using a currently modified reference value to yield a read data; programming the multi-bit cell of the memory device with a second value selected based upon a combination of a second bit value and the read data; and generating the currently modified reference value such that it yields a reduced bit error rate of the read data compared with a previous modified reference value.
In some instances of the aforementioned embodiments, generating the currently modified reference value includes: programming two or more cells of a selected region of the memory device with a known pattern; reading back the two or more cells of the selected region of the memory device using a first test value as a reference voltage to yield a first read back data set; comparing the first read back data set with the known pattern; generating a first bit error rate corresponding to the first test value based upon the comparison of the first read back data set with the known pattern; reading back the two or more cells of the selected region of the memory device using a second test value as a reference voltage to yield a second read back data set; comparing the second read back data set with the known pattern; and generating a second bit error rate corresponding to the second test value based upon the comparison of the second read back data set with the known pattern. In some cases, the multi-bit cell of the memory device is a two-bit cell. In other cases, the multi-bit cell of the memory device is a three-bit cell. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety a numbers of bits per memory cell to which the method may be applied in accordance with different embodiments of the present invention.
In some cases, the generating the currently modified reference value further includes erasing the two or more cells of the selected region of the memory device and/or selecting the one of the first test value or the second test value as the currently modified reference value based at least in part on a comparison of the first bit error rate and the second bit error rate. In various cases, a first distribution corresponding to a first programming level of the two or more cells of the selected region of the memory device and a second distribution corresponding to a second programming level of the two or more cells of the selected region of the memory device overlap. In some such cases, the lower of the first bit error rate and the second bit error rate corresponds to a test value that is closer to the intersection of a first distribution and the second distribution.
Other embodiments of the present invention provide data storage systems that include: a memory device, a memory device access circuit, and a reference control circuit. The memory device access circuit is operable to: program a multi-bit cell of a memory device with a first value selected based upon a first bit value; read the multi-bit cell of the memory device using a currently modified reference value to yield a read data; and program the multi-bit cell of the memory device with a second value selected based upon a combination of a second bit value and the read data. The reference control circuit is operable to generate the currently modified reference value such that it yields a reduced bit error rate of the read data compared with a previous modified reference value.
In some cases, at least the memory device access circuit and the reference control circuit of the aforementioned embodiment are incorporated in an integrated circuit. In other cases, the entire system of the aforementioned embodiment is implemented on an integrated circuit. In one or more cases, the memory device is a flash memory device.
In some instances of the aforementioned embodiment, generating the currently modified reference value by the reference control circuit is done by the reference control circuit operable to: program two or more multi-bit cells of a selected region of the memory device with a known pattern; read back the two or more multi-bit cells of the selected region of the memory device using a first test value as a reference voltage to yield a first read back data set; compare the first read back data set with the known pattern; generate a first bit error rate corresponding to the first test value based upon the comparison of the first read back data set with the known pattern; read back the two or more multi-bit cells of the selected region of the memory device using a second test value as a reference voltage to yield a second read back data set; compare the second read back data set with the known pattern; and generate a second bit error rate corresponding to the second test value based upon the comparison of the second read back data set with the known pattern. In some cases, generating the currently modified reference value by the reference control circuit is done by the reference control circuit further operable to: erase the two or more multi-bit cells of the selected region of the memory device and/or select the one of the first test value or the second test value as the currently modified reference value based at least in part on a comparison of the first bit error rate and the second bit error rate.
Yet other embodiments of the present invention provide flash memory storage systems that include: a memory device including a plurality of multi-bit flash memory cells; a memory device access circuit; and a reference control circuit. Memory device access circuit is operable to: program a multi-bit flash memory cell of the memory device with a first value selected based upon a first bit value; read the multi-bit flash memory cell of the memory device using a currently modified reference value to yield a read data; and program the multi-bit flash memory cell of the memory device with a second value selected based upon a combination of a second bit value and the read data. The reference control circuit is operable to: program two or more multi-bit flash memory cells of a selected region of the memory device with a known pattern; read back the two or more multi-bit flash memory cells of the selected region of the memory device using a first test value as a reference voltage to yield a first read back data set; compare the first read back data set with the known pattern; generate a first bit error rate corresponding to the first test value based upon the comparison of the first read back data set with the known pattern; read back the two or more multi-bit flash memory cells of the selected region of the memory device using a second test value as a reference voltage to yield a second read back data set; compare the second read back data set with the known pattern; generate a second bit error rate corresponding to the second test value based upon the comparison of the second read back data set with the known pattern; and select the one of the first test value or the second test value as the currently modified reference value based at least in part on a comparison of the first bit error rate and the second bit error rate
Turning to
A data write is effectuated when host controller circuit 160 provides write data 105 to be written along with an address 110 indicating the location to be written. A memory access controller 120 formats write data 105 and provides an address 123 and an encoded write data 125 to a write circuit 130. Write circuit 130 provides a write voltage 135 corresponding to respective groupings of encoded write data 125 that is used to charge respective flash memory cells addressed by address 123. For example, where flash memory cells are two bit cells (i.e., depending upon the read voltage, a value of ‘11’, ‘10’, ‘00’, or ‘01’ is returned), the following voltages may be applied to store the data:
Of course, other bit patterns may be assigned to different thresholds.
A data read is effectuated when host controller circuit 160 provides address 110 along with a request to read data from the corresponding location in flash memory cells 140. Memory access controller 120 accesses a read voltage 145 from locations indicated by address 123 and compares the voltage to a number of threshold values 154 to reduce the voltage to a multi-bit read data 155. Using the same two bit example, the following multi-bit read data 155 results:
This multi-bit read data 155 is provided from memory access controller 120 to data processing circuit 170 as read data 107. Iterative data processing circuit 170 applies a data decoding algorithm to read data 107 using soft data 173 that is either accessed or generated by memory access controller circuit 120. Soft data may either be provided from flash memory cells 140 where such are available, or may be generated by memory access controller circuit 120. Such generation of soft information may be done using any approach known in the art for generating soft data. As one example, generation of soft information may be done similar to that disclosed in U.S. patent application Ser. No. 14/047,423 entitled “Systems and Methods for Enhanced Data Recovery in a Solid State Memory System”, and filed by Xia et al. on Oct. 7, 2013. The entirety of the aforementioned application was previously incorporated herein by reference for all purposes.
Iterative data processing circuit 170 repeatedly applies a data decoding algorithm to read data 107 and soft data 173 to yield a decoded output. Where the decoded output converges (i.e., results in a correction of all remaining errors in read data 107), the decoded output is provided as read data 175. Where the decoded output fails to converge (i.e., errors remain in the decoded output), another iteration of the data decoding algorithm is applied to read data 107 guided by the previous decoded output to yield an updated decoded output. This process continues until either all errors are corrected or a timeout condition occurs (e.g., 100 iterations). In some embodiments of the present invention, the data decoding algorithm is a low density parity check algorithm as is known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data decoding algorithms that may be used in relation to various embodiments of the present invention.
Voltage thresholds 154 include an lower page only threshold value that may be changed from time to time to reflect the changes in flash memory cells 140. The lower page only threshold value included in voltage thresholds 154 is set by lower page only read reference control circuit 180. In particular, lower page only read reference control circuit 180 provides a threshold value 186 to memory access controller circuit 120 that is provided as the lower page only threshold value included in voltage thresholds 154. Lower page only read reference control circuit 180 calculates threshold value 186 based upon a bit error rate 182 from memory access controller circuit 120. The calibration of threshold value 186 is more fully described below in relation to
Turning to
Turning to
The data to be stored as the most significant bits of the respective cells is loaded into a least significant bit storage buffer maintained as part of memory access controller circuit 120. Finally, the target threshold range for the combination of the least significant bit and the most significant bit for each of the cells is selected and used to program the respective cells. For example, where the combination of the least significant bit and the most significant bit is a ‘11’, the voltage to which the cell is charged is below the reference voltage VTH1 from
One problem with the aforementioned programming approach occurs where there is ambiguity between the aforementioned ‘X1’ state and ‘X0’ state. Such ambiguity can result in the difference between programming a cell in the Erase state or State C of
Turning to
Turning to
A target voltage is selected for each cell of the write target based upon a combination of the data in the least significant bit storage buffer and corresponding most significant bit information in the received write data (block 225). For example, where the combination of the least significant bit and the most significant bit is a ‘11’, the voltage to which the cell is charged is below the reference voltage VTH1 from
Alternatively, where a write request is not received (block 205), it is determined whether a read request is received (block 250). Where a read request is received (block 250), it includes an address indicating a location from which the data is to be accessed. Data is then accessed from the flash memory cells at the location indicated by the read request (block 255).
Turning to
Where it is determined that a calibration of the modified lowest page only reference value is to be performed (block 605), a test region of the solid state memory device is selected and erased (block 610). A known least significant bit pattern is written to the lower page only region of the cells in the selected region (block). The known least significant bit pattern may be selected as any pattern. In some cases, the known least significant bit pattern is designed to provide some variation in programming levels across the cells. In one particular embodiment of the present invention, the known least significant bit pattern is a repeating pattern of ‘101010101010 . . . . ’ Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other patterns that may be used for the known least significant bit pattern.
An initial value is selected for the modified lowest page only reference value (block 620). The data is read back from the selected test region using the selected value for the modified lowest page only reference (block 625), and the known least significant bit pattern is compared with the read back data to yield a bit error rate (block 630). This bit error rate is stored in relation to the corresponding lowest page only reference value that was used during the read back (block 635).
It is determined whether one or more additional values for the modified lowest page only reference remain to be tested (block 640). In some cases, a defined range of values for the modified lowest page only reference are tested, with each successive value of the modified lowest page only reference being an increment from the last one tested. In various cases, once three or more successive instances of the modified lowest page only reference are shown to cause an increasing bit error rate, then the minimum bit error rate is considered to have been found and no more values for the modified lowest page only reference are considered to remain for testing. Where additional values for the modified lowest page only reference remain to be tested (block 640), the next value of the modified lowest page only reference is selected (block 645) and the processes of blocks 625-640 are repeated for the newly selected value of the modified lowest page only reference.
Otherwise, once the range of values of the modified lowest page only reference have been tested (block 640), the resulting stored bit error rates are accessed from memory (block 650), and the lowest of the stored bit error rates is identified (block 655). The instance of the modified lowest page only reference value that corresponds to the identified, lowest bit error rate is selected as the modified lowest page only reference value that will be used in performing writes to the solid state memory device until the next calibration process is triggered (block 660).
It should be noted that the process of calibrating the modified lowest page only reference value has been discussed in relation to a two-bit per cell flash memory device, that that the process may be modified for use in relation to a three or more bit per cell flash memory device. In such a case where it is applied to a three-bit per cell memory device, the calibration may be performed for the read back after a write of the least significant bit to calibrate the lowest page only reference value. In some such cases, the calibration may also be performed for the read back after a write of the second least significant bit to calibrate the second lowest page only reference value.
It should be noted that the various blocks discussed in the above application may be implemented in integrated circuits along with other functionality. Such integrated circuits may include all of the functions of a given block, system or circuit, or a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
In conclusion, the invention provides novel systems, devices, methods and arrangements for data processing. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
The present application claims priority to (is a non-provisional of) U.S. Pat. App. No. 61/936,599 entitled “Systems and Methods for Hard Error Reduction in a Solid State Memory Device”, and filed Feb. 6, 2014 by Wu et al. The entirety of the aforementioned provisional patent application is incorporated herein by reference for all purposes.
Number | Name | Date | Kind |
---|---|---|---|
5892896 | Shingo | Apr 1999 | A |
6516425 | Belhadj et al. | Feb 2003 | B1 |
6651032 | Peterson et al. | Nov 2003 | B2 |
7127549 | Sinclair | Oct 2006 | B2 |
7254692 | Teoh et al. | Aug 2007 | B1 |
7310699 | Sinclair | Dec 2007 | B2 |
7523013 | Gorobets et al. | Apr 2009 | B2 |
7596656 | Elhamias | Sep 2009 | B2 |
7721146 | Polisetti et al. | May 2010 | B2 |
7778077 | Gorobets et al. | Aug 2010 | B2 |
8010738 | Chilton et al. | Aug 2011 | B1 |
8085591 | Moschiano | Dec 2011 | B2 |
8151137 | McKean et al. | Apr 2012 | B2 |
8174912 | Warren | May 2012 | B2 |
8176367 | Dreifus | May 2012 | B2 |
8289768 | Warren et al. | Oct 2012 | B2 |
8381077 | Warren | Feb 2013 | B2 |
8458416 | Warren et al. | Jun 2013 | B2 |
8499220 | Warren | Jul 2013 | B2 |
8539311 | Steiner | Sep 2013 | B2 |
8560765 | Warren | Oct 2013 | B2 |
8804421 | Motwani | Aug 2014 | B2 |
20020091965 | Moshayedi | Jul 2002 | A1 |
20050044459 | Scheuerlein et al. | Feb 2005 | A1 |
20050172067 | Sinclair | Aug 2005 | A1 |
20050204187 | Lee et al. | Sep 2005 | A1 |
20050209804 | Basso et al. | Sep 2005 | A1 |
20060245248 | Hu | Nov 2006 | A1 |
20070028040 | Sinclair | Feb 2007 | A1 |
20070266200 | Gorobets et al. | Nov 2007 | A1 |
20080010557 | Kume | Jan 2008 | A1 |
20080046779 | Merchant et al. | Feb 2008 | A1 |
20080086275 | Astigarraga et al. | Apr 2008 | A1 |
20080162079 | Astigarraga et al. | Jul 2008 | A1 |
20080307270 | Li | Dec 2008 | A1 |
20090063895 | Smith | Mar 2009 | A1 |
20090067303 | Poo et al. | Mar 2009 | A1 |
20090147698 | Potvin | Jun 2009 | A1 |
20090172280 | Trika et al. | Jul 2009 | A1 |
20090190396 | Cho | Jul 2009 | A1 |
20090204853 | Diggs et al. | Aug 2009 | A1 |
20090282301 | Flynn et al. | Nov 2009 | A1 |
20100121609 | Gorinevsky | May 2010 | A1 |
20100122148 | Flynn et al. | May 2010 | A1 |
20100306577 | Dreifus et al. | Dec 2010 | A1 |
20100306580 | McKean et al. | Dec 2010 | A1 |
20110058415 | Warren | Mar 2011 | A1 |
20110060862 | Warren | Mar 2011 | A1 |
20110060865 | Warren et al. | Mar 2011 | A1 |
20110286271 | Chen | Nov 2011 | A1 |
20120102261 | Burger et al. | Apr 2012 | A1 |
20120110376 | Dreifus et al. | May 2012 | A1 |
20120224420 | Sakurada | Sep 2012 | A1 |
20120317460 | Chilappagari | Dec 2012 | A1 |
20130155776 | Chilappagari | Jun 2013 | A1 |
20130311837 | Bedeschi | Nov 2013 | A1 |
20140119114 | Motwani | May 2014 | A1 |
20140173174 | Frickey | Jun 2014 | A1 |
20150078078 | D'Abreu | Mar 2015 | A1 |
20150078079 | D'Abreu | Mar 2015 | A1 |
20150085575 | Tam | Mar 2015 | A1 |
20150113354 | Wu | Apr 2015 | A1 |
20150149698 | Cai | May 2015 | A1 |
20150149840 | Alhussien | May 2015 | A1 |
20150149871 | Chen | May 2015 | A1 |
20150154069 | Tuers | Jun 2015 | A1 |
20150178152 | Cai | Jun 2015 | A1 |
Number | Date | Country |
---|---|---|
102009-0013394 | Feb 2009 | KR |
Entry |
---|
U.S. Appl. No. 14/072,530, filed Nov. 5, 2013, Cai. |
U.S. Appl. No. 14/072,571, filed Nov. 5, 2013, Wu. |
U.S. Appl. No. 14/085,553, filed Nov. 20, 2013, Cai. |
U.S. Appl. No. 14/108,226, filed Dec. 16, 2013, Chen. |
U.S. Appl. No. 14/178,201, filed Feb. 11, 2014, Wu. |
U.S. Appl. No. 14/047,423, Unpublished (filed Oct. 7, 2013) (Haitao Xia). |
U.S. Appl. No. 14/072,530, Unpublished (filed Nov. 5, 2013) (Yu Cai). |
U.S. Appl. No. 14/072,574, Unpublished (filed Nov. 5, 2013) (Yunxiang Wu). |
U.S. Appl. No. 14/108,226, Unpublished (filed Dec. 16, 2013) (Zhengang Chen). |
U.S. Appl. No. 14/085,553, Unpublished (filed Nov. 20, 2013) (Yu Cai). |
U.S. Appl. No. 13/912,063, Unpublished (filed Jun. 6, 2013) (Fan Zhang). |
Number | Date | Country | |
---|---|---|---|
20150220388 A1 | Aug 2015 | US |
Number | Date | Country | |
---|---|---|---|
61936599 | Feb 2014 | US |