1. Field of the Invention
The present invention relates to the manufacture of integrated circuits by a lithographic process and, in particular, to a method and system for determining critical dimension or overlay variation of integrated circuit fields within and between chip levels and layers.
2. Description of Related Art
Semiconductor integrated circuit manufacturing requires the sequential patterning of process levels on a single semiconductor wafer. Exposure tools print multiple integrated circuit patterns or fields by lithographic methods on successive levels of the wafer. These tools typically pattern the different levels by applying step and repeat lithographic exposure or step and scan lithographic exposure in which the full area of the wafer is patterned by sequential exposure of the stepper fields containing one or more integrated circuits. Typically, 20-50 levels are required to create an integrated circuit. In some cases, multiple masks are required to pattern a single level.
Successful fabrication of integrated circuit devices requires the precise and accurate measurements of registration of the mask (reticle) set and overlay placement of mask level to subsequent mask level. Current manufacturing technology uses separate methods of measuring mask registration and wafer level overlay. The use of bar in bar (box in box) and grating targets only allows for the measurement of overlay on the wafer level with no information of mask registration information. Current technology has limited application due to size restriction for placement around the mask reticle field. These targets are also greatly affected by process induced variations given that they are not within the shape pattern densities found within the functioning chip. Hence, these targets are susceptible to chemical mechanical planarization, thermal processing, and lithography image processing.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved target and method for determination of overlay error within a chip level.
It is another object of the present invention to provide an improved target and method for correlating mask-to-wafer variations of critical dimension and overlay.
A further object of the invention is to provide an improved target and method for distinguishing mask and wafer components of critical dimension and overlay variation.
It is yet another object of the present invention to provide an improved target and method to minimize on-wafer critical dimension and overlay variation.
It is another object of the present invention to provide an improved target and method that measures mask and wafer registration, critical dimension at the same physical location.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects, which will be apparent to those skilled in the art, are achieved in the present invention which in one aspect is directed to a method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method comprises creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets on the masks, determining overlay variation between the masks, exposing and creating with one of the masks a first lithographic processing layer on a wafer, and exposing and creating with another of the masks a second lithographic processing layer on the wafer, over the first layer. The method further includes measuring the targets on the wafer at one or more of the layers, and correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation.
The method preferably further includes using the correlated mask and wafer measurements to control the mask and wafer fabrication processes to minimize wafer critical dimension and overlay variation.
The compact targets preferably include a first set of optical target structures resolvable by optical microscopy when exposed and created on the wafer and a second set of chip-like target structures not resolvable by optical microscopy when exposed and created on the wafer, but resolvable by SEM or AFM microscopy. The first set of optical target structures may be used to measure overlay and the second set of chip-like target structures may be used to measure critical dimension.
The first set of optical target structures may comprise lines on the masks that are adjacent one another when projected by the masks onto the wafer.
The first set of optical target structures may also comprise a first target pattern on one mask having a center at the origin of an orthogonal grid and sub-patterns with 180° symmetry, and a second target pattern on another mask having a center at the same location as the first target pattern and sub-patterns with 180° symmetry, with the sub-patterns of the second target pattern being located at different locations than the sub-patterns of the first target pattern.
The first set of optical target structures may also comprise a first target pattern on one mask having a center at the origin of an orthogonal grid of pitch p, with the sub-patterns of the first target pattern have coordinates of:
The second set of chip-like target structures may comprise non-functional structures in the functional circuit structures, such as shallow trench isolation structures, gate structures, contact structures and metal line structures. Preferably, the second set of chip-like target structures have line widths and spacing not greater than about 200 nm, and have a density gradient ranging from a lower density near the optical structures to a higher density away from the optical structures.
The target sub-patterns enable pattern specific critical dimension measurements on the masks and wafer, pattern placement measurements on the masks and overlay measurement between two or more layers on the wafer. The targets should be sufficiently small to be placed within unutilized regions of the chip being manufactured, preferably, less than 10 μm on an edge.
In another aspect, the present invention is directed to a mask having structure patterns for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The mask comprises functional circuit structure patterns on the mask in areas corresponding to chips to be made on a wafer and targets on the mask at locations between functional circuit structure patterns. The target containing structure pattern is suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on at least one patterning layer on the wafer. The target structures include a first set of optical target structures resolvable by optical microscopy when exposed and created on the wafer and a second set of chip-like target structures not resolvable by optical microscopy when exposed and created on the wafer, but resolvable by SEM or AFM microscopy.
The targets are located within areas corresponding to chips to be made on the wafer, are sufficiently small to be placed within unutilized regions of the chip being manufactured and are preferably less than 10 μm on an edge. The optical structures are preferably located on opposite sides of the target, and wherein the chip-like structures are located on opposite sides of the target between the optical structures. The first set of optical target structures is typically used to measure overlay and the second set of chip-like target structures is typically used to measure critical dimension.
The first set of optical target structures may comprise lines on the mask. The first set of optical target structures may also comprise a target pattern having a center at the origin of an orthogonal grid and sub-patterns with 180° symmetry. The first set of optical target structures may also comprise a target pattern having a center at the origin of an orthogonal grid of pitch p, with the sub-patterns of the first target pattern have coordinates of:
The second set of chip-like target structures preferably comprise non-functional structures in the functional circuit structures, such as shallow trench isolation structures, gate structures, contact structures and metal line structures. The chip-like target structures preferably have line widths and spacing not greater than about 200 nm and have a density gradient ranging from a lower density near the optical structures to a higher density away from the optical structures.
The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
In describing the preferred embodiment of the present invention, reference will be made herein to
The present invention provides a target and method for combining both reticle critical dimension (CD) and registration measurement with wafer level or layer overlay measurement in the lithographic production of integrated circuits. The invention allows for precise correlation of wafer level or layer overlay measurements and reticle registration measurements, as well as vastly improving the ability to make thru-field overlay measurements. The invention also provides a method for separating reticle-induced overlay components from wafer exposure-induced overlay errors. This is particularly important because double exposure patterning, where a mask prints first set of lines and then shifts to print a second set of lines, is often used because there is not sufficient resolution to print required pitch in one exposure.
The integrated target of the present invention incorporates both optical structures and chip-like structures. Optical structures are relatively low-resolution, optically-viewable target structures that may be viewed by optical microscopy. Chip-like structures are relatively high resolution structures that mimic the configuration of circuit devices and features found in the functional circuits in the chips formed on the wafer, but are not part of those chip circuits and are non-functional with respect to the operation of the chip. The optical structures are preferably used in the present invention for overlay (OL) and pattern placement (PP) measurements. The chip-like structures are preferably used in the present invention primarily for CD measurement, but may also be used to a limited degree for overlay measurement.
The present invention places the integrated target in unutilized regions of the chip design on the mask, such as in kerf regions and in unused areas of the chip regions. The target structures of the different masks and levels are stacked at common locations. The target structures may be used to correlate pattern placement and wafer overlay measurements, correlate mask CD and wafer CD measurements, determine any mask component of critical dimension and overlay variation and determine lithographic process induced deviations of same. The ultimate goal is to minimize wafer critical dimension and overlay variation between the different process levels and layers.
One type of optical target is the blossom target disclosed in U.S. Ser. Nos. 11/162,506 and 11/833,304, the disclosures of which are hereby incorporated by reference. The blossom target system places a plurality of sub-patterns or petals at a constant radial distance about a common center, such that the sub-patterns are symmetric about a target pattern center and preferably define the corners of a geometric shape, more preferably a square. Other geometric shapes may also be used, with the sub-patterns located at the corners of the shapes. The sub-patterns can be any feature or combination of features that is symmetric about the X-Y axes, such as a cross, circle, square, square grid, and the like. The cross is the simplest among the sub-pattern options. Each sub-pattern or petal has a unique x-y location. The center of symmetry of each petal or sub-pattern may be determined by optical microscopy, although higher resolution scanning electron microscope (SEM) and atomic force microscopy (AFM) can also be used.
As shown in
r=p√(N2+M2)
Each group of petals corresponds to a different lithographic level or layer. As the target groups are created on each of the different lithographic levels or layers containing the other portions of the integrated circuit, the (N, M) values are preferably incremented by integers (n, m). As used herein, the term lithographic level refers to the physical level as seen in vertical cross-section of the wafer. The term layer refers to the different mask exposures during lithographic processing. A lithographic level may have only one layer if only one mask exposure level is required to produce the level. On the other hand, it is common to require more than one mask exposure or layer to create the circuit images on each lithographic level. In this blossom target system, each level or layer corresponds to unique values of (N, M). Radial symmetry of the petal group is maintained at each level or layer. The radii of the petals may be the same or different for each lithographic level or layer and the centers of the petals of each group on each layer define a unique radius for the group on a layer. Under the constraint that the sum of the absolute values of the increments are even, i.e,
|n|+|m|=2i
for integer i, superposition of the sub-patterns over multiple layers defines an overlay target in the form of a close-packed diagonal array. As shown in
Each of the square target groups in
The preferred level or layer alignment measurement method consists of determining the center of each petal, then using those sub-pattern centers to determine the center of the group of petals at each level or layer, and then determining the pair-wise difference in x and y values among the centers of all of the groups to determine alignment error between the targets on the lithographic levels or layers. Instead of the blossom targets, the optical targets may be other optical shapes, such as more simple lines and crosses.
The preferred chip-like structures used in the target of the present invention are those that resemble functional circuit or device structures such as shallow trench isolation structures (RX), transistor gates (PC), contacts (CA) and metal lines (M1).
The order of these chip like structures reflects normal front end of line (FEOL) lithographic process ordering on different levels. The size of these structures as exposed and produced on the wafer should be sufficiently small to determine CD and overlay errors by the mask and/or lithographic processing. The minimum linewidth dimensions of these features are preferably in the range of about 20 to 200 nm. The structures generally cannot be seen by optical microscopy, and require higher resolution methods such as SEM or AFM for measurement. The maximum density of these chip-like structures in the target is determined by the minimum pitch, which is on the order of twice the minimum linewidth dimension. This density is important in the preferred embodiment of the integrated target system of the present invention, wherein the chip-like structures have a density gradient that generally increases from a minimum density near the center of the target to a maximum density near the edges of the target away from the center.
A preferred integrated target 60 is shown in
The center cross 80 is an optical structure that comprises horizontal 82a, 82c and vertical 82b, 82d arms along the boundaries between the four quadrants of the target 60. The center region between the arms 82a, 82b, 82c, 82d is left open for a square field 40a that may contain low density chip-like structures or other target structures. Optical structure fields 50 contain either the blossom target or microblossom target described above, or other optical structures such as crosses 84. Crosses 84 are oriented to have ends of the cross lines 84a, 84b, 84c, 84d end at the outer peripheries of the fields 50. As will be described in more detail below, the elements of optical cross 80, as well as optical crosses 80, 84 themselves, may be stacked on alternate lithographic levels to enable overlay metrology among more than two levels.
Optical proximity correction (OPC) techniques are used on chip-like structures only. Preferably, the density of the chip-like structures in fields 40 increases on the diagonal toward the perimeter to minimize proximity effects on center cross 80 and crosses 84 and otherwise prevent interference with the optical structures in the target.
Buffer regions 70 are provided on the periphery of target 60 to minimize proximity effects from adjacent structures on the mask and enable pattern recognition during microscopic measurement of the target. The buffer regions have a desired width, here shown as about 0.4 μm, and have no target or other features therein. The location of the opposite quadrants of chip-like fields 40 and optical structure fields 50 provide diagonal and radial symmetry to nullify any proximity effect on overlay measurement metrology.
In use to control mask fabrication, a simulated exposure of the two masks is made sequentially by a system that uses an interferometric stage. The method is shown in
In use to control wafer fabrication, cross 80 and the RX chip-like structures (not shown) in fields 40 are exposed by the level 1 mask 110 (
Further target configurations are shown in
As indicated above, instead of the relatively large stacked cross structures 82a-d, 83a-d, 84 and 85 shown in
The lithographically induced errors are determined 214 by taking the difference of WaferCDN and MaskCDN to arrive at ΔCDN, the difference of WaferCDM and MaskCDM to arrive at ΔCDM and the difference of WaferOLMN and MaskOLMN to arrive at ΔOLMN. These lithographically induced deviations are used as feedback to determine and correct the lithographic processes 218 for the next layers to be deposited. The mask induced errors are then determined 216 by comparing the critical dimension and overlay errors between the wafer and mask, such as correlating the deviation of WaferCDM to MaskCDM, WaferCDN to MaskCDN and WaferOLMN to MaskOLMN. These wafer to mask deviations are then used as feedback to determine and correct the mask fabrication 220 for the next layers to be deposited. The determination of both the lithographic and wafer-to-mask deviations then leads to optimization of the wafer 222.
For the optical structures, measurements on the individual layers created by the mask may be done at any point in lithographic processing. For chip-like structures used in overlay measurements, however, typically measurements may not be made at any point in lithographic processing since they will have to be measured using a high resolution metrology tool like SEM or AFM, which can only be employed in post-etch processing steps. These high resolution tools cannot see through deposited levels as optical tools can, and are therefore less useful because after etching it is too late to correct the substrate level. On the other hand, these high resolution tools can still correlate 226 the optical measurement to SEM or AFM measurement of an actual fabricated chip-like structure to provide mask fabrication corrections.
Additionally, in evaluating litho-induced deviations 214, the deviation of wafer critical dimensions and overlay may be compared to the original circuit design. Because of various techniques employed in the mask itself, such as OPC, assist features and the like, the mask patterns may not look anything like the image that is exposed and created on the wafer. Since the mask is more and more distinct from what is actually printed on the wafer, these litho-induced deviations may be used to correct the original design itself 224, rather than just correct the mask.
The relationship of layers to levels in lithographic processing is depicted in
Thus, the present invention provides an improved target and method for determination of overlay error within a chip level which correlates mask-to-wafer variations of critical dimension and overlay and is able to distinguish mask and wafer components of critical dimension and overlay variation. Further, the present invention provides an improved target sufficiently small in size to measures mask and wafer registration, critical dimension at the same physical location to achieve the goal of minimizing on-wafer critical dimension and overlay variation.
While the present invention has been particularly described, in conjunction with specific preferred embodiments, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
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